1 | /* pci_interface.c |
---|
2 | * |
---|
3 | * Copyright 2004, Brookhaven National Laboratory and |
---|
4 | * Shuchen Kate Feng <feng1@bnl.gov> |
---|
5 | * |
---|
6 | * The license and distribution terms for this file may be |
---|
7 | * found in the file LICENSE in this distribution. |
---|
8 | * |
---|
9 | */ |
---|
10 | #include <libcpu/io.h> |
---|
11 | #include <rtems/bspIo.h> /* printk */ |
---|
12 | |
---|
13 | #include <bsp.h> |
---|
14 | #include <bsp/pci.h> |
---|
15 | #include <bsp/gtreg.h> |
---|
16 | #include <bsp/gtpcireg.h> |
---|
17 | |
---|
18 | #define PCI_DEBUG 0 |
---|
19 | |
---|
20 | /* Please reference the GT64260B datasheet, for the PCI interface, |
---|
21 | * Synchronization Barriers and PCI ordering. |
---|
22 | * |
---|
23 | * Some PCI devices require Synchronization Barriers or PCI ordering |
---|
24 | * for synchronization. For example, the VME-OMS58 motor controller we |
---|
25 | * used at NSLS requires either enhanced CPU Synchronization Barrier |
---|
26 | * or PCI-ordering (only one mechanism allowed. See section 11.1.2). |
---|
27 | * To use the former mechanism(default), one needs to call |
---|
28 | * CPU0_PciEnhanceSync() or CPU1_PciEnhanceSync() to perform software |
---|
29 | * synchronization between the CPU and PCI activities. |
---|
30 | * |
---|
31 | * To use the PCI-ordering, one can call pciToCpuSync() to trigger |
---|
32 | * the PCI-to-CPU sync barrier after the out_xx(). In this mode, |
---|
33 | * PCI configuration reads suffer sync barrier latency. Please reference |
---|
34 | * the datasheet to explore other options. |
---|
35 | * |
---|
36 | * Note : If PCI_ORDERING is needed for the PCI0, while disabling the |
---|
37 | * deadlock for the PCI0, one should keep the CommDLEn bit enabled |
---|
38 | * for the deadlock mechanism so that the 10/100 MB ethernet will |
---|
39 | * function correctly. |
---|
40 | * |
---|
41 | */ |
---|
42 | #define PCI_ORDERING |
---|
43 | |
---|
44 | /*#define PCI_DEADLOCK*/ |
---|
45 | |
---|
46 | /* So far, I do not see the need to disable the address pipelining. |
---|
47 | #define DIS_ADDR_PIPELINE*/ |
---|
48 | |
---|
49 | #ifdef PCI_ORDERING |
---|
50 | #define PCI_ACCCTLBASEL_VALUE 0x01009000 |
---|
51 | #else |
---|
52 | #define PCI_ACCCTLBASEL_VALUE 0x01001000 |
---|
53 | #endif |
---|
54 | |
---|
55 | #define ConfSBDis 0x10000000 /* 1: disable, 0: enable */ |
---|
56 | #define IOSBDis 0x20000000 /* 1: disable, 0: enable */ |
---|
57 | #define ConfIOSBDis 0x30000000 |
---|
58 | #define CpuPipeline 0x00002000 /* optional, 1:enable, 0:disable */ |
---|
59 | |
---|
60 | #define CPU0_SYNC_TRIGGER 0xD0 /* CPU0 Sync Barrier trigger */ |
---|
61 | #define CPU0_SYNC_VIRTUAL 0xC0 /* CPU0 Sync Barrier Virtual */ |
---|
62 | |
---|
63 | #define CPU1_SYNC_TRIGGER 0xD8 /* CPU1 Sync Barrier trigger */ |
---|
64 | #define CPU1_SYNC_VIRTUAL 0xC8 /* CPU1 Sync Barrier Virtual */ |
---|
65 | |
---|
66 | |
---|
67 | /* CPU to PCI ordering register */ |
---|
68 | #define DLOCK_ORDER_REG 0x2D0 /* Deadlock and Ordering register */ |
---|
69 | #define PCI0OrEn 0x00000001 |
---|
70 | #define PCI1OrEn 0x00000020 |
---|
71 | #define PCIOrEn 0x40000000 |
---|
72 | #define PCIOrEnMASK 0x40000021 |
---|
73 | |
---|
74 | #define CNT_SYNC_REG 0x2E0 /* Counters and Sync Barrier register */ |
---|
75 | #define L0SyncBar 0x00001000 |
---|
76 | #define L1SyncBar 0x00002000 |
---|
77 | #define DSyncBar 0x00004000 |
---|
78 | #define SyncBarMode 0x00008000 |
---|
79 | #define SyncBarMASK 0x0000f000 |
---|
80 | |
---|
81 | #define WRTBK_PRIO_BUFFER 0x2d8 /* writback priority and buffer depth */ |
---|
82 | |
---|
83 | #define ADDR_PIPELINE 0x00020000 |
---|
84 | |
---|
85 | void PCI_interface() |
---|
86 | { |
---|
87 | unsigned int data; |
---|
88 | |
---|
89 | #if (defined(PCI_ORDERING)||defined(DIS_ADDR_PIPELINE)) |
---|
90 | data = inl(0); /* needed : read to flush */ |
---|
91 | /* MOTLOad default disables Configuration and I/O Read Sync Barrier |
---|
92 | * which is needed for enhanced CPU sync. barrier */ |
---|
93 | #ifdef PCI_ORDERING |
---|
94 | /* enable Configuration Read Sync Barrier and IO read Sync Barrier*/ |
---|
95 | data &= ~ConfIOSBDis; |
---|
96 | #endif |
---|
97 | #ifdef DIS_ADDR_PIPELINE |
---|
98 | data &= ~ADDR_PIPELINE; |
---|
99 | |
---|
100 | #if PCI_DEBUG |
---|
101 | printk("data %x\n", data); |
---|
102 | #endif |
---|
103 | #endif |
---|
104 | outl(data, 0); |
---|
105 | /* read polling of the register until the new data is being read */ |
---|
106 | while ( inl(0)!=data); |
---|
107 | #endif |
---|
108 | |
---|
109 | #ifdef PCI_DEADLOCK |
---|
110 | outl(0x07fff600, CNT_SYNC_REG); |
---|
111 | #endif |
---|
112 | #ifdef PCI_ORDERING |
---|
113 | outl(0xc0060002, DLOCK_ORDER_REG); |
---|
114 | outl(0x07fff600, CNT_SYNC_REG); |
---|
115 | #else |
---|
116 | outl(inl(PCI0_CMD_CNTL)|PCI_COMMAND_SB_DIS, PCI0_CMD_CNTL); |
---|
117 | #endif |
---|
118 | |
---|
119 | /* asserts SERR upon various detection */ |
---|
120 | outl(0x3fffff, 0xc28); |
---|
121 | |
---|
122 | } |
---|
123 | |
---|
124 | /* Use MOTLoad default for Writeback Priority and Buffer Depth |
---|
125 | */ |
---|
126 | void pciAccessInit(int PciNum) |
---|
127 | { |
---|
128 | unsigned int data; |
---|
129 | |
---|
130 | /* MOTLoad combines the two banks of SDRAM into |
---|
131 | * one PCI access control because the top = 0x1ff |
---|
132 | */ |
---|
133 | data = inl(GT_SCS0_Low_Decode) & 0xfff; |
---|
134 | data |= PCI_ACCCTLBASEL_VALUE; |
---|
135 | data &= ~0x300000; |
---|
136 | outl(data, PCI0_ACCESS_CNTL_BASE0_LOW+(PciNum * 0x80)); |
---|
137 | #if PCI_DEBUG |
---|
138 | printk("PCI%d_ACCESS_CNTL_BASE0_LOW 0x%x\n",PciNum,inl(PCI0_ACCESS_CNTL_BASE0_LOW+(PciNum * 0x80))); |
---|
139 | #endif |
---|
140 | |
---|
141 | } |
---|
142 | |
---|
143 | /* Sync Barrier Trigger. A write to the CPU_SYNC_TRIGGER register triggers |
---|
144 | * the sync barrier process. The three bits, define which buffers should |
---|
145 | * be flushed. |
---|
146 | * Bit 0 = PCI0 slave write buffer. |
---|
147 | * Bit 1 = PCI1 slave write buffer. |
---|
148 | * Bit 2 = SDRAM snoop queue. |
---|
149 | */ |
---|
150 | void CPU0_PciEnhanceSync(unsigned int syncVal) |
---|
151 | { |
---|
152 | outl(syncVal,CPU0_SYNC_TRIGGER); |
---|
153 | while (inl(CPU0_SYNC_VIRTUAL)); |
---|
154 | } |
---|
155 | |
---|
156 | void CPU1_PciEnhanceSync(unsigned int syncVal) |
---|
157 | { |
---|
158 | outl(syncVal,CPU1_SYNC_TRIGGER); |
---|
159 | while (inl(CPU1_SYNC_VIRTUAL)); |
---|
160 | } |
---|
161 | |
---|
162 | /* Currently, if PCI_ordering is used for synchronization, configuration |
---|
163 | * reads is programmed to be the PCI slave "synchronization barrier" |
---|
164 | * cycles. |
---|
165 | */ |
---|
166 | void pciToCpuSync(int pci_num) |
---|
167 | { |
---|
168 | unsigned char data; |
---|
169 | |
---|
170 | PCIx_read_config_byte(pci_num, 0,0,0,4, &data); |
---|
171 | } |
---|