1 | /* pci_interface.c |
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2 | * |
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3 | * Copyright 2004, 2006, 2007 All rights reserved. (NDA items) |
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4 | * Brookhaven National Laboratory and Shuchen Kate Feng <feng1@bnl.gov> |
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5 | * |
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6 | * The license and distribution terms for this file may be |
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7 | * found in the file LICENSE in this distribution. |
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8 | * |
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9 | * 8/17/2006 : S. Kate Feng |
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10 | * uses in_le32()/out_le32(), instead of inl()/outl() for compatibility. |
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11 | * |
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12 | * 11/2008 : Enable "PCI Read Agressive Prefetch", |
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13 | * "PCI Read Line Agressive Prefetch", and |
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14 | * "PCI Read Multiple Agressive Prefetch" to improve the |
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15 | * performance of the PCI based applications (e.g. 1GHz NIC). |
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16 | */ |
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17 | |
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18 | #include <libcpu/io.h> |
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19 | #include <rtems/bspIo.h> /* printk */ |
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20 | |
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21 | #include <bsp.h> |
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22 | #include <bsp/pci.h> |
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23 | #include <bsp/gtreg.h> |
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24 | #include <bsp/gtpcireg.h> |
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25 | |
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26 | #define PCI_DEBUG 0 |
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27 | |
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28 | #if 0 |
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29 | #define CPU2PCI_ORDER |
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30 | #define PCI2CPU_ORDER |
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31 | #endif |
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32 | |
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33 | /* PCI Read Agressive Prefetch Enable (1<<16 ), |
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34 | * PCI Read Line Agressive Prefetch Enable( 1<<17), |
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35 | * PCI Read Multiple Agressive Prefetch Enable (1<<18). |
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36 | */ |
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37 | #ifdef PCI2CPU_ORDER |
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38 | #define PCI_ACCCTLBASEL_VALUE 0x01079000 |
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39 | #else |
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40 | #define PCI_ACCCTLBASEL_VALUE 0x01071000 |
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41 | #endif |
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42 | |
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43 | |
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44 | #define ConfSBDis 0x10000000 /* 1: disable, 0: enable */ |
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45 | #define IOSBDis 0x20000000 /* 1: disable, 0: enable */ |
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46 | #define ConfIOSBDis 0x30000000 |
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47 | #define CpuPipeline 0x00002000 /* optional, 1:enable, 0:disable */ |
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48 | |
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49 | /* CPU to PCI ordering register */ |
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50 | #define DLOCK_ORDER_REG 0x2D0 /* Deadlock and Ordering register */ |
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51 | #define PCI0OrEn 0x00000001 |
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52 | #define PCI1OrEn 0x00000020 |
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53 | #define PCIOrEn 0x40000000 |
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54 | #define PCIOrEnMASK 0x40000021 |
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55 | |
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56 | #define CNT_SYNC_REG 0x2E0 /* Counters and Sync Barrier register */ |
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57 | #define L0SyncBar 0x00001000 |
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58 | #define L1SyncBar 0x00002000 |
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59 | #define DSyncBar 0x00004000 |
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60 | #define SyncBarMode 0x00008000 |
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61 | #define SyncBarMASK 0x0000f000 |
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62 | |
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63 | #define WRTBK_PRIO_BUFFER 0x2d8 /* writback priority and buffer depth */ |
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64 | |
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65 | #define ADDR_PIPELINE 0x00020000 |
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66 | |
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67 | void pciAccessInit(void); |
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68 | |
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69 | void pci_interface(void) |
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70 | { |
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71 | |
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72 | #ifdef CPU2PCI_ORDER |
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73 | /* MOTLOad deafult : 0x07ff8600 */ |
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74 | out_le32((volatile unsigned int *)(GT64x60_REG_BASE+CNT_SYNC_REG), 0x07fff600); |
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75 | #endif |
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76 | /* asserts SERR upon various detection */ |
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77 | out_le32((volatile unsigned int *)(GT64x60_REG_BASE+0xc28), 0x3fffff); |
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78 | pciAccessInit(); |
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79 | } |
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80 | |
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81 | void pciAccessInit(void) |
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82 | { |
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83 | unsigned int PciLocal, data; |
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84 | |
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85 | for (PciLocal=0; PciLocal < 2; PciLocal++) { |
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86 | data = in_le32((volatile unsigned int *)(GT64x60_REG_BASE+PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80))); |
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87 | #if 0 |
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88 | printk("PCI%d_ACCESS_CNTL_BASE0_LOW was 0x%x\n",PciLocal,data); |
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89 | #endif |
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90 | data |= PCI_ACCCTLBASEL_VALUE; |
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91 | data &= ~0x300000; |
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92 | out_le32((volatile unsigned int *)(GT64x60_REG_BASE+PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80)), data); |
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93 | #if 0 |
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94 | printf("PCI%d_ACCESS_CNTL_BASE0_LOW now 0x%x\n",PciLocal,in_le32((volatile unsigned int *)(GT64x60_REG_BASE+PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80)))); |
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95 | #endif |
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96 | } |
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97 | } |
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98 | |
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