source: rtems/c/src/lib/libbsp/powerpc/mvme5500/pci/pci_interface.c @ 6771a9e7

4.104.114.9
Last change on this file since 6771a9e7 was 6771a9e7, checked in by Ralf Corsepius <ralf.corsepius@…>, on Aug 20, 2008 at 9:00:11 AM

Add missing prototypes.

  • Property mode set to 100644
File size: 4.9 KB
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1/* pci_interface.c
2 *
3 * Copyright 2004, 2006, 2007 All rights reserved. (NDA items)
4 *      Brookhaven National Laboratory and Shuchen Kate Feng <feng1@bnl.gov>
5 *
6 * The license and distribution terms for this file may be
7 * found in the file LICENSE in this distribution.
8 *
9 * 8/17/2006 : S. Kate Feng
10 *             uses in_le32()/out_le32(), instead of inl()/outl() so that
11 *             it is easier to be ported.
12 *
13 */
14#include <libcpu/io.h>
15#include <rtems/bspIo.h>            /* printk */
16
17#include <bsp.h>
18#include <bsp/pci.h>
19#include <bsp/gtreg.h>
20#include <bsp/gtpcireg.h> 
21
22#define REG32_READ(reg) in_le32((volatile unsigned int *)(GT64260_REG_BASE+reg))
23#define REG32_WRITE(data, reg) out_le32((volatile unsigned int *)(GT64260_REG_BASE+reg), data)
24
25#define PCI_DEBUG     0
26
27/* Please reference the GT64260B datasheet, for the PCI interface,
28 * Synchronization Barriers and PCI ordering.
29 *
30 * Some PCI devices require Synchronization Barriers or PCI ordering
31 * for synchronization (only one mechanism allowed. See section 11.1.2).
32 * To use the former mechanism(default), one needs to call
33 * CPU0_PciEnhanceSync() or CPU1_PciEnhanceSync() to perform software
34 * synchronization between the CPU and PCI activities.
35 *
36 * To use the PCI-ordering, one can call pciToCpuSync() to trigger
37 * the PCI-to-CPU sync barrier after the out_xx(). In this mode,
38 * PCI configuration reads suffer sync barrier latency. Please reference
39 * the datasheet to explore other options.
40 *
41 * Note : If PCI_ORDERING is needed for the PCI0, while disabling the
42 * deadlock  for the PCI0, one should keep the CommDLEn bit enabled
43 * for the deadlock mechanism so that the 10/100 MB ethernet will
44 * function correctly.
45 *
46 */
47/*#define PCI_ORDERING*/
48
49#define EN_SYN_BAR   /* take MOTLoad default for enhanced SYN Barrier mode */
50
51/*#define PCI_DEADLOCK*/
52
53#ifdef PCI_ORDERING
54#define PCI_ACCCTLBASEL_VALUE          0x01009000
55#else
56#define PCI_ACCCTLBASEL_VALUE          0x01001000
57#endif
58
59#define ConfSBDis     0x10000000  /* 1: disable, 0: enable */
60#define IOSBDis       0x20000000  /* 1: disable, 0: enable */
61#define ConfIOSBDis   0x30000000
62#define CpuPipeline   0x00002000  /* optional, 1:enable, 0:disable */
63
64#define CPU0_SYNC_TRIGGER   0xD0  /* CPU0 Sync Barrier trigger */
65#define CPU0_SYNC_VIRTUAL   0xC0  /* CPU0 Sync Barrier Virtual */
66
67#define CPU1_SYNC_TRIGGER   0xD8  /* CPU1 Sync Barrier trigger */
68#define CPU1_SYNC_VIRTUAL   0xC8  /* CPU1 Sync Barrier Virtual */
69
70
71/* CPU to PCI ordering register */
72#define DLOCK_ORDER_REG    0x2D0  /* Deadlock and Ordering register */
73#define PCI0OrEn      0x00000001
74#define PCI1OrEn      0x00000020
75#define PCIOrEn       0x40000000
76#define PCIOrEnMASK   0x40000021
77
78#define CNT_SYNC_REG       0x2E0  /* Counters and Sync Barrier register */
79#define L0SyncBar     0x00001000
80#define L1SyncBar     0x00002000
81#define DSyncBar      0x00004000
82#define SyncBarMode   0x00008000
83#define SyncBarMASK   0x0000f000
84
85#define WRTBK_PRIO_BUFFER  0x2d8  /* writback priority and buffer depth */
86
87#define ADDR_PIPELINE 0x00020000
88
89void  pciAccessInit(void);
90
91void pci_interface(void)
92{
93
94#ifdef PCI_DEADLOCK
95  REG32_WRITE(0x07fff600, CNT_SYNC_REG);
96#endif
97#ifdef PCI_ORDERING
98  /* Let's leave this to be MOTLOad deafult : 0x80070000
99     REG32_WRITE(0xc0070000, DLOCK_ORDER_REG);*/
100  /* Leave the CNT_SYNC_REG b/c MOTload default had the SyncBarMode set to 1 */
101#endif
102
103  /* asserts SERR upon various detection */
104  REG32_WRITE(0x3fffff, 0xc28);
105
106  pciAccessInit();
107}
108/* Use MOTLoad default for Writeback Priority and Buffer Depth
109 */
110void pciAccessInit(void)
111{
112  unsigned int PciLocal, data;
113
114  for (PciLocal=0; PciLocal < 2; PciLocal++) {
115    /* MOTLoad combines the two banks of SDRAM into
116     * one PCI access control because the top = 0x1ff
117     */
118    data = REG32_READ(GT_SCS0_Low_Decode) & 0xfff; 
119    data |= PCI_ACCCTLBASEL_VALUE;
120    data &= ~0x300000;
121    REG32_WRITE(data, PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80));
122#if PCI_DEBUG
123    printk("PCI%d_ACCESS_CNTL_BASE0_LOW 0x%x\n",PciLocal,REG32_READ(PCI_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80))); 
124#endif
125
126  }
127}
128
129/* Sync Barrier Trigger. A write to the CPU_SYNC_TRIGGER register triggers
130 * the sync barrier process.  The three bits, define which buffers should
131 * be flushed.
132 * Bit 0 = PCI0 slave write buffer.
133 * Bit 1 = PCI1 slave write buffer.
134 * Bit 2 = SDRAM snoop queue.
135 */
136void CPU0_PciEnhanceSync(unsigned int syncVal)
137{
138  REG32_WRITE(syncVal,CPU0_SYNC_TRIGGER);
139  while (REG32_READ(CPU0_SYNC_VIRTUAL));
140}
141
142void CPU1_PciEnhanceSync(unsigned int syncVal)
143{
144  REG32_WRITE(syncVal,CPU1_SYNC_TRIGGER);
145  while (REG32_READ(CPU1_SYNC_VIRTUAL));
146}
147
148/* Currently, if PCI_ordering is used for synchronization, configuration
149 * reads is programmed to be the PCI slave "synchronization barrier"
150 * cycles.
151 */
152void pciToCpuSync(int pci_num)
153{
154  unsigned char data;
155  unsigned char bus=0;
156
157  if (pci_num) bus += BSP_MAX_PCI_BUS_ON_PCI0;
158  pci_read_config_byte(bus,0,0,4, &data);
159}
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