1 | /* pci_interface.c |
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2 | * |
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3 | * Copyright 2004, 2006, 2007 All rights reserved. (NDA items) |
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4 | * Brookhaven National Laboratory and Shuchen Kate Feng <feng1@bnl.gov> |
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5 | * |
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6 | * The license and distribution terms for this file may be |
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7 | * found in the file LICENSE in this distribution. |
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8 | * |
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9 | * 8/17/2006 : S. Kate Feng |
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10 | * uses in_le32()/out_le32(), instead of inl()/outl() so that |
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11 | * it is easier to be ported. |
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12 | * |
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13 | */ |
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14 | #include <libcpu/io.h> |
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15 | #include <rtems/bspIo.h> /* printk */ |
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16 | |
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17 | #include <bsp.h> |
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18 | #include <bsp/pci.h> |
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19 | #include <bsp/gtreg.h> |
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20 | #include <bsp/gtpcireg.h> |
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21 | |
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22 | #define REG32_READ(reg) in_le32((volatile unsigned int *)(GT64260_REG_BASE+reg)) |
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23 | #define REG32_WRITE(data, reg) out_le32((volatile unsigned int *)(GT64260_REG_BASE+reg), data) |
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24 | |
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25 | #define PCI_DEBUG 0 |
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26 | |
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27 | /* Please reference the GT64260B datasheet, for the PCI interface, |
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28 | * Synchronization Barriers and PCI ordering. |
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29 | * |
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30 | * Some PCI devices require Synchronization Barriers or PCI ordering |
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31 | * for synchronization (only one mechanism allowed. See section 11.1.2). |
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32 | * To use the former mechanism(default), one needs to call |
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33 | * CPU0_PciEnhanceSync() or CPU1_PciEnhanceSync() to perform software |
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34 | * synchronization between the CPU and PCI activities. |
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35 | * |
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36 | * To use the PCI-ordering, one can call pciToCpuSync() to trigger |
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37 | * the PCI-to-CPU sync barrier after the out_xx(). In this mode, |
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38 | * PCI configuration reads suffer sync barrier latency. Please reference |
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39 | * the datasheet to explore other options. |
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40 | * |
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41 | * Note : If PCI_ORDERING is needed for the PCI0, while disabling the |
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42 | * deadlock for the PCI0, one should keep the CommDLEn bit enabled |
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43 | * for the deadlock mechanism so that the 10/100 MB ethernet will |
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44 | * function correctly. |
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45 | * |
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46 | */ |
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47 | /*#define PCI_ORDERING*/ |
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48 | |
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49 | #define EN_SYN_BAR /* take MOTLoad default for enhanced SYN Barrier mode */ |
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50 | |
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51 | /*#define PCI_DEADLOCK*/ |
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52 | |
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53 | #ifdef PCI_ORDERING |
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54 | #define PCI_ACCCTLBASEL_VALUE 0x01009000 |
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55 | #else |
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56 | #define PCI_ACCCTLBASEL_VALUE 0x01001000 |
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57 | #endif |
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58 | |
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59 | #define ConfSBDis 0x10000000 /* 1: disable, 0: enable */ |
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60 | #define IOSBDis 0x20000000 /* 1: disable, 0: enable */ |
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61 | #define ConfIOSBDis 0x30000000 |
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62 | #define CpuPipeline 0x00002000 /* optional, 1:enable, 0:disable */ |
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63 | |
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64 | #define CPU0_SYNC_TRIGGER 0xD0 /* CPU0 Sync Barrier trigger */ |
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65 | #define CPU0_SYNC_VIRTUAL 0xC0 /* CPU0 Sync Barrier Virtual */ |
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66 | |
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67 | #define CPU1_SYNC_TRIGGER 0xD8 /* CPU1 Sync Barrier trigger */ |
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68 | #define CPU1_SYNC_VIRTUAL 0xC8 /* CPU1 Sync Barrier Virtual */ |
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69 | |
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70 | |
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71 | /* CPU to PCI ordering register */ |
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72 | #define DLOCK_ORDER_REG 0x2D0 /* Deadlock and Ordering register */ |
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73 | #define PCI0OrEn 0x00000001 |
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74 | #define PCI1OrEn 0x00000020 |
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75 | #define PCIOrEn 0x40000000 |
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76 | #define PCIOrEnMASK 0x40000021 |
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77 | |
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78 | #define CNT_SYNC_REG 0x2E0 /* Counters and Sync Barrier register */ |
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79 | #define L0SyncBar 0x00001000 |
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80 | #define L1SyncBar 0x00002000 |
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81 | #define DSyncBar 0x00004000 |
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82 | #define SyncBarMode 0x00008000 |
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83 | #define SyncBarMASK 0x0000f000 |
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84 | |
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85 | #define WRTBK_PRIO_BUFFER 0x2d8 /* writback priority and buffer depth */ |
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86 | |
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87 | #define ADDR_PIPELINE 0x00020000 |
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88 | |
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89 | void pciAccessInit(); |
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90 | |
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91 | void pci_interface() |
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92 | { |
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93 | |
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94 | #ifdef PCI_DEADLOCK |
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95 | REG32_WRITE(0x07fff600, CNT_SYNC_REG); |
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96 | #endif |
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97 | #ifdef PCI_ORDERING |
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98 | /* Let's leave this to be MOTLOad deafult : 0x80070000 |
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99 | REG32_WRITE(0xc0070000, DLOCK_ORDER_REG);*/ |
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100 | /* Leave the CNT_SYNC_REG b/c MOTload default had the SyncBarMode set to 1 */ |
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101 | #endif |
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102 | |
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103 | /* asserts SERR upon various detection */ |
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104 | REG32_WRITE(0x3fffff, 0xc28); |
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105 | |
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106 | pciAccessInit(); |
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107 | } |
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108 | /* Use MOTLoad default for Writeback Priority and Buffer Depth |
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109 | */ |
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110 | void pciAccessInit() |
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111 | { |
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112 | unsigned int PciLocal, data; |
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113 | |
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114 | for (PciLocal=0; PciLocal < 2; PciLocal++) { |
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115 | /* MOTLoad combines the two banks of SDRAM into |
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116 | * one PCI access control because the top = 0x1ff |
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117 | */ |
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118 | data = REG32_READ(GT_SCS0_Low_Decode) & 0xfff; |
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119 | data |= PCI_ACCCTLBASEL_VALUE; |
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120 | data &= ~0x300000; |
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121 | REG32_WRITE(data, PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80)); |
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122 | #if PCI_DEBUG |
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123 | printk("PCI%d_ACCESS_CNTL_BASE0_LOW 0x%x\n",PciLocal,REG32_READ(PCI_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80))); |
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124 | #endif |
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125 | |
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126 | } |
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127 | } |
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128 | |
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129 | /* Sync Barrier Trigger. A write to the CPU_SYNC_TRIGGER register triggers |
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130 | * the sync barrier process. The three bits, define which buffers should |
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131 | * be flushed. |
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132 | * Bit 0 = PCI0 slave write buffer. |
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133 | * Bit 1 = PCI1 slave write buffer. |
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134 | * Bit 2 = SDRAM snoop queue. |
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135 | */ |
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136 | void CPU0_PciEnhanceSync(unsigned int syncVal) |
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137 | { |
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138 | REG32_WRITE(syncVal,CPU0_SYNC_TRIGGER); |
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139 | while (REG32_READ(CPU0_SYNC_VIRTUAL)); |
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140 | } |
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141 | |
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142 | void CPU1_PciEnhanceSync(unsigned int syncVal) |
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143 | { |
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144 | REG32_WRITE(syncVal,CPU1_SYNC_TRIGGER); |
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145 | while (REG32_READ(CPU1_SYNC_VIRTUAL)); |
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146 | } |
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147 | |
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148 | /* Currently, if PCI_ordering is used for synchronization, configuration |
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149 | * reads is programmed to be the PCI slave "synchronization barrier" |
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150 | * cycles. |
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151 | */ |
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152 | void pciToCpuSync(int pci_num) |
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153 | { |
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154 | unsigned char data; |
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155 | unsigned char bus=0; |
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156 | |
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157 | if (pci_num) bus += BSP_MAX_PCI_BUS_ON_PCI0; |
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158 | pci_read_config_byte(bus,0,0,4, &data); |
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159 | } |
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