1 | /* |
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2 | * pci.c : this file contains basic PCI Io functions. |
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3 | * |
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4 | * CopyRight (C) 1999 valette@crf.canon.fr |
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5 | * |
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6 | * This code is heavilly inspired by the public specification of STREAM V2 |
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7 | * that can be found at : |
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8 | * |
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9 | * <http://www.chorus.com/Documentation/index.html> by following |
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10 | * the STREAM API Specification Document link. |
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11 | * |
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12 | * The license and distribution terms for this file may be |
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13 | * found in the file LICENSE in this distribution or at |
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14 | * http://www.OARcorp.com/rtems/license.html. |
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15 | * |
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16 | * pci.c,v 1.2 2002/05/14 17:10:16 joel Exp |
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17 | * |
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18 | * Copyright 2004, Brookhaven National Laboratory and |
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19 | * Shuchen K. Feng, <feng1@bnl.gov>, 2004 |
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20 | * - modified and added support for MVME5500 board |
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21 | * - added 2nd PCI support for the mvme5500/GT64260 PCI bridge |
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22 | * |
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23 | */ |
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24 | #define PCI_MAIN |
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25 | |
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26 | #include <libcpu/io.h> |
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27 | #include <rtems/bspIo.h> /* printk */ |
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28 | |
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29 | #include <bsp/pci.h> |
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30 | #include <bsp/gtreg.h> |
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31 | #include <bsp/gtpcireg.h> |
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32 | |
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33 | #include <stdio.h> |
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34 | #include <string.h> |
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35 | |
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36 | #define PCI_DEBUG 0 |
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37 | #define PCI_PRINT 1 |
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38 | |
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39 | #define PCI_INVALID_VENDORDEVICEID 0xffffffff |
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40 | #define PCI_MULTI_FUNCTION 0x80 |
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41 | #define HOSTBRIDGET_ERROR 0xf0000000 |
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42 | |
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43 | typedef unsigned char unchar; |
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44 | |
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45 | #define MAX_NUM_PCI_DEVICES 20 |
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46 | |
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47 | static int numPCIDevs=0; |
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48 | extern void PCI_interface(), pciAccessInit(); |
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49 | |
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50 | /* Pack RegNum,FuncNum,DevNum,BusNum,and ConfigEnable for |
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51 | * PCI Configuration Address Register |
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52 | */ |
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53 | #define pciConfigPack(bus,dev,func,offset)\ |
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54 | (((func&7)<<8)|((dev&0x1f )<<11)|(( bus&0xff)<<16)|(offset&0xfc))|0x80000000 |
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55 | |
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56 | /* |
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57 | * Bit encode for PCI_CONFIG_HEADER_TYPE register |
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58 | */ |
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59 | unchar ucMaxPCIBus=0; |
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60 | |
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61 | /* Please note that PCI0 and PCI1 does not correlate with the busNum 0 and 1. |
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62 | */ |
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63 | int PCIx_read_config_byte(int npci, unchar bus, unchar dev, |
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64 | unchar func, unchar offset, unchar *val) |
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65 | { |
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66 | *val = 0xff; |
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67 | if (offset & ~0xff) return PCIBIOS_BAD_REGISTER_NUMBER; |
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68 | outl(pciConfigPack(bus,dev,func,offset),BSP_pci_config[npci].pci_config_addr); |
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69 | *val = inb(BSP_pci_config[npci].pci_config_data + (offset&3)); |
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70 | return PCIBIOS_SUCCESSFUL; |
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71 | } |
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72 | |
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73 | int PCIx_read_config_word(int npci, unchar bus, unchar dev, |
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74 | unchar func, unchar offset, unsigned short *val) |
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75 | { |
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76 | *val = 0xffff; |
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77 | if ((offset&1)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER; |
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78 | outl(pciConfigPack(bus,dev,func,offset),BSP_pci_config[npci].pci_config_addr); |
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79 | *val = inw(BSP_pci_config[npci].pci_config_data + (offset&2)); |
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80 | return PCIBIOS_SUCCESSFUL; |
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81 | } |
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82 | |
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83 | int PCIx_read_config_dword(int npci, unchar bus, unchar dev, |
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84 | unchar func, unchar offset, unsigned int *val) |
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85 | { |
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86 | *val = 0xffffffff; |
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87 | if ((offset&3)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER; |
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88 | #if 0 |
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89 | printk("addr %x, data %x, pack %x \n", BSP_pci_config[npci].pci_config_addr, |
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90 | BSP_pci_config[npci].pci_config_data,pciConfigPack(bus,dev,func,offset)); |
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91 | #endif |
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92 | outl(pciConfigPack(bus,dev,func,offset),BSP_pci_config[npci].pci_config_addr); |
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93 | *val = inl(BSP_pci_config[npci].pci_config_data); |
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94 | return PCIBIOS_SUCCESSFUL; |
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95 | } |
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96 | |
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97 | int PCIx_write_config_byte(int npci, unchar bus, unchar dev, |
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98 | unchar func, unchar offset, unchar val) |
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99 | { |
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100 | if (offset & ~0xff) return PCIBIOS_BAD_REGISTER_NUMBER; |
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101 | |
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102 | outl(pciConfigPack(bus,dev,func,offset),BSP_pci_config[npci].pci_config_addr); |
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103 | outb(val, BSP_pci_config[npci].pci_config_data + (offset&3)); |
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104 | return PCIBIOS_SUCCESSFUL; |
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105 | } |
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106 | |
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107 | int PCIx_write_config_word(int npci, unchar bus, unchar dev, |
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108 | unchar func, unchar offset, unsigned short val) |
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109 | { |
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110 | if ((offset&1)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER; |
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111 | outl(pciConfigPack(bus,dev,func,offset),BSP_pci_config[npci].pci_config_addr); |
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112 | outw(val, BSP_pci_config[npci].pci_config_data + (offset&3)); |
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113 | return PCIBIOS_SUCCESSFUL; |
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114 | } |
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115 | |
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116 | int PCIx_write_config_dword(int npci,unchar bus,unchar dev, |
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117 | unchar func, unchar offset, unsigned int val) |
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118 | { |
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119 | if ((offset&3)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER; |
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120 | #if 0 |
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121 | printk("addr %x, data %x, pack %x \n", BSP_pci_config[npci].pci_config_addr, |
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122 | BSP_pci_config[npci].pci_config_data,pciConfigPack(bus,dev,func,offset)); |
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123 | #endif |
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124 | outl(pciConfigPack(bus,dev,func,offset),BSP_pci_config[npci].pci_config_addr); |
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125 | outl(val,BSP_pci_config[npci].pci_config_data); |
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126 | return PCIBIOS_SUCCESSFUL; |
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127 | } |
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128 | |
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129 | /* backwards compatible with other PPC board for the vmeUniverse.c */ |
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130 | int pci_read_config_byte(unchar bus, unchar dev,unchar func,unchar offset, |
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131 | unchar *val) |
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132 | { |
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133 | return(PCIx_read_config_byte(0, bus, dev, func, offset, val)); |
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134 | } |
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135 | |
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136 | int pci_read_config_word(unchar bus, unchar dev, |
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137 | unchar func, unchar offset, unsigned short *val) |
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138 | { |
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139 | return(PCIx_read_config_word(0, bus, dev, func, offset, val)); |
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140 | } |
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141 | |
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142 | int pci_read_config_dword(unchar bus, unchar dev, |
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143 | unchar func, unchar offset, unsigned int *val) |
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144 | { |
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145 | return(PCIx_read_config_dword(0, bus, dev, func, offset, val)); |
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146 | } |
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147 | |
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148 | int pci_write_config_byte(unchar bus, unchar dev, |
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149 | unchar func, unchar offset, unchar val) |
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150 | { |
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151 | return(PCIx_write_config_byte(0, bus, dev, func, offset, val)); |
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152 | } |
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153 | |
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154 | int pci_write_config_word(unchar bus, unchar dev, |
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155 | unchar func, unchar offset, unsigned short val) |
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156 | { |
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157 | return(PCIx_write_config_word(0, bus, dev, func, offset, val)); |
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158 | } |
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159 | |
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160 | int pci_write_config_dword(unchar bus,unchar dev, |
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161 | unchar func, unchar offset, unsigned int val) |
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162 | { |
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163 | return(PCIx_write_config_dword(0, bus, dev, func, offset, val)); |
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164 | } |
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165 | |
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166 | |
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167 | pci_config BSP_pci_config[2] = { |
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168 | {PCI0_CONFIG_ADDR,PCI0_CONFIG_DATA/*,&pci_functions*/}, |
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169 | {PCI1_CONFIG_ADDR,PCI1_CONFIG_DATA/*,&pci_functions*/} |
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170 | }; |
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171 | |
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172 | /* |
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173 | * This routine determines the maximum bus number in the system |
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174 | */ |
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175 | void InitializePCI() |
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176 | { |
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177 | int PciNumber; |
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178 | unchar ucBusNumber, ucSlotNumber, ucFnNumber, ucNumFuncs; |
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179 | unchar ucMaxSubordinate; |
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180 | unsigned long ulHeader; |
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181 | unsigned int data, datal, datah, pcidata, ulClass, ulDeviceID; |
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182 | unsigned short sdata; |
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183 | |
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184 | PCI_interface(); |
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185 | |
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186 | /* |
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187 | * Scan PCI0 and PCI1 bus0 |
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188 | */ |
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189 | for (PciNumber=0; PciNumber < 2; PciNumber++) { |
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190 | pciAccessInit(PciNumber); |
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191 | for (ucBusNumber=0; ucBusNumber< 2; ucBusNumber++) { |
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192 | for (ucSlotNumber=0;ucSlotNumber<PCI_MAX_DEVICES;ucSlotNumber++) { |
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193 | ucFnNumber = 0; |
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194 | PCIx_read_config_dword(PciNumber, ucBusNumber, |
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195 | ucSlotNumber, |
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196 | 0, |
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197 | PCI0_VENDOR_ID, |
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198 | &ulDeviceID); |
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199 | |
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200 | if( ulDeviceID==PCI_INVALID_VENDORDEVICEID) { |
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201 | /* This slot is empty */ |
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202 | continue; |
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203 | } |
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204 | |
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205 | if (++numPCIDevs > MAX_NUM_PCI_DEVICES) { |
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206 | BSP_panic("Too many PCI devices found; increase MAX_NUM_PCI_DEVICES in pcicache.c\n"); |
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207 | } |
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208 | |
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209 | switch(ulDeviceID) { |
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210 | case (PCI_VENDOR_ID_MARVELL+(PCI_DEVICE_ID_MARVELL_GT6426xAB<<16)): |
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211 | #if PCI_PRINT |
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212 | printk("Marvell GT6426xA/B hostbridge detected at PCI%d bus%d slot%d\n", |
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213 | PciNumber,ucBusNumber,ucSlotNumber); |
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214 | #endif |
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215 | ucMaxPCIBus ++; |
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216 | break; |
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217 | case (PCI_VENDOR_ID_PLX2+(PCI_DEVICE_ID_PLX2_PCI6154_HB2<<16)): |
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218 | #if PCI_PRINT |
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219 | printk("PLX PCI6154 PCI-PCI bridge detected at PCI%d bus%d slot%d\n", |
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220 | PciNumber,ucBusNumber,ucSlotNumber); |
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221 | #endif |
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222 | ucMaxPCIBus ++; |
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223 | break; |
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224 | case PCI_VENDOR_ID_TUNDRA: |
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225 | #if PCI_PRINT |
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226 | printk("TUNDRA PCI-VME bridge detected at PCI%d bus%d slot%d\n", |
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227 | PciNumber,ucBusNumber,ucSlotNumber); |
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228 | #endif |
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229 | ucMaxPCIBus ++; |
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230 | break; |
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231 | case (PCI_VENDOR_ID_INTEL+(PCI_DEVICE_INTEL_82544EI_COPPER<<16)): |
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232 | #if PCI_PRINT |
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233 | printk("INTEL 82544EI COPPER network controller detected at PCI%d bus%d slot%d\n", |
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234 | PciNumber,ucBusNumber,ucSlotNumber); |
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235 | #endif |
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236 | ucMaxPCIBus ++; |
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237 | break; |
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238 | default : |
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239 | #if PCI_PRINT |
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240 | printk("PCI%d Bus%d Slot%d DeviceID 0x%x \n", |
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241 | PciNumber,ucBusNumber,ucSlotNumber, ulDeviceID); |
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242 | #endif |
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243 | break; |
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244 | } |
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245 | #if PCI_DEBUG |
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246 | PCIx_read_config_dword(PciNumber, ucBusNumber, |
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247 | ucSlotNumber, |
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248 | 0, |
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249 | PCI0_BASE_ADDRESS_0, |
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250 | &data); |
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251 | printk("PCI%d_BASE_ADDRESS_0 0x%x \n",PciNumber, data); |
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252 | PCIx_read_config_dword(PciNumber, ucBusNumber, |
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253 | ucSlotNumber, |
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254 | 0, |
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255 | PCI0_BASE_ADDRESS_1, |
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256 | &data); |
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257 | printk("PCI%d_BASE_ADDRESS_1 0x%x \n",PciNumber, data); |
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258 | PCIx_read_config_dword(PciNumber, ucBusNumber, |
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259 | ucSlotNumber, |
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260 | 0, |
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261 | PCI0_BASE_ADDRESS_2, |
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262 | &data); |
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263 | printk("PCI%d_BASE_ADDRESS_2 0x%x \n",PciNumber, data); |
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264 | |
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265 | PCIx_read_config_dword(PciNumber, ucBusNumber, |
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266 | ucSlotNumber, |
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267 | 0, |
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268 | PCI0_BASE_ADDRESS_3, |
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269 | &data); |
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270 | printk("PCI%d_BASE_ADDRESS_3 0x%x \n",PciNumber, data); |
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271 | |
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272 | PCIx_read_config_word(PciNumber, ucBusNumber, |
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273 | ucSlotNumber, |
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274 | 0, |
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275 | PCI0_INTERRUPT_LINE, |
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276 | &sdata); |
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277 | printk("PCI%d_INTERRUPT_LINE 0x%x \n",PciNumber, sdata); |
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278 | |
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279 | /* We always enable internal memory. */ |
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280 | PCIx_read_config_dword(PciNumber, ucBusNumber, |
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281 | ucSlotNumber, |
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282 | 0, |
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283 | PCI0_MEM_BASE_ADDR, |
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284 | &pcidata); |
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285 | printk("PCI%d_MEM_BASE_ADDR 0x%x \n", PciNumber,pcidata); |
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286 | |
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287 | /* We always enable internal IO. */ |
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288 | PCIx_read_config_dword(PciNumber, ucBusNumber, |
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289 | ucSlotNumber, |
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290 | 0, |
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291 | PCI0_IO_BASE_ADDR, |
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292 | &pcidata); |
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293 | printk("PCI%d_IO_BASE_ADDR 0x%x \n", PciNumber,pcidata); |
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294 | #endif |
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295 | |
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296 | PCIx_read_config_dword(PciNumber, ucBusNumber, |
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297 | ucSlotNumber, |
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298 | 0, |
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299 | PCI0_CACHE_LINE_SIZE, |
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300 | &ulHeader); |
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301 | if ((ulHeader>>16)&PCI_MULTI_FUNCTION) |
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302 | ucNumFuncs=PCI_MAX_FUNCTIONS; |
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303 | else |
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304 | ucNumFuncs=1; |
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305 | |
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306 | #if PCI_DEBUG |
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307 | printk("PCI%d Slot 0x%x HEADER/LAT/CACHE 0x%x \n", |
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308 | PciNumber,ucSlotNumber, ulHeader); |
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309 | |
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310 | for (ucFnNumber=1;ucFnNumber<ucNumFuncs;ucFnNumber++) { |
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311 | PCIx_read_config_dword(PciNumber, ucBusNumber, |
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312 | ucSlotNumber, |
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313 | ucFnNumber, |
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314 | PCI0_VENDOR_ID, |
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315 | &ulDeviceID); |
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316 | if (ulDeviceID==PCI_INVALID_VENDORDEVICEID) { |
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317 | /* This slot/function is empty */ |
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318 | continue; |
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319 | } |
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320 | if (++numPCIDevs > MAX_NUM_PCI_DEVICES) { |
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321 | BSP_panic("Too many PCI devices found; increase MAX_NUM_PCI_DEVICES in pcicache.c\n"); |
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322 | } |
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323 | |
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324 | /* This slot/function has a device fitted.*/ |
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325 | PCIx_read_config_dword(PciNumber, ucBusNumber, |
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326 | ucSlotNumber, |
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327 | ucFnNumber, |
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328 | PCI0_CLASS_REVISION, |
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329 | &ulClass); |
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330 | printk("PCI%d Slot 0x%x Func %d classID 0x%x \n",PciNumber,ucSlotNumber, |
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331 | ucFnNumber, ulClass); |
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332 | |
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333 | ulClass >>= 16; |
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334 | if (ulClass == PCI_CLASS_GT6426xAB) |
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335 | printk("GT64260-PCI%d bridge found \n", PciNumber); |
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336 | } |
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337 | #endif |
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338 | PCIx_read_config_dword(PciNumber, ucBusNumber, |
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339 | ucSlotNumber, |
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340 | 0, |
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341 | PCI0_COMMAND, |
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342 | &pcidata); |
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343 | #if PCI_DEBUG |
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344 | printk("MOTLoad command staus 0x%x, ", pcidata); |
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345 | #endif |
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346 | /* Clear the error on the host bridge */ |
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347 | if ( (ucBusNumber==0) && (ucSlotNumber==0)) |
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348 | pcidata |= PCI_STATUS_CLRERR_MASK; |
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349 | /* Enable bus,I/O and memory master access. */ |
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350 | pcidata |= (PCI_COMMAND_MASTER|PCI_COMMAND_IO|PCI_COMMAND_MEMORY); |
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351 | PCIx_write_config_dword(PciNumber, ucBusNumber, |
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352 | ucSlotNumber, |
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353 | 0, |
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354 | PCI0_COMMAND, |
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355 | pcidata); |
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356 | |
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357 | PCIx_read_config_dword(PciNumber, ucBusNumber, |
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358 | ucSlotNumber, |
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359 | 0, |
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360 | PCI0_COMMAND, |
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361 | &pcidata); |
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362 | #if PCI_DEBUG |
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363 | printk("Now command/staus 0x%x\n", pcidata); |
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364 | #endif |
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365 | |
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366 | } |
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367 | } |
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368 | } /* PCI number */ |
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369 | } |
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370 | |
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371 | /* |
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372 | * Return the number of PCI buses in the system |
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373 | */ |
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374 | unsigned char BusCountPCI() |
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375 | { |
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376 | return(ucMaxPCIBus); |
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377 | } |
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378 | |
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