1 | /* |
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2 | * pci.c : this file contains basic PCI Io functions. |
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3 | * |
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4 | * CopyRight (C) 1999 valette@crf.canon.fr |
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5 | * |
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6 | * This code is heavilly inspired by the public specification of STREAM V2 |
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7 | * that can be found at : |
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8 | * |
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9 | * <http://www.chorus.com/Documentation/index.html> by following |
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10 | * the STREAM API Specification Document link. |
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11 | * |
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12 | * The license and distribution terms for this file may be |
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13 | * found in the file LICENSE in this distribution or at |
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14 | * http://www.rtems.org/rtems/license.html. |
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15 | * |
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16 | * Copyright 2004, 2008 Brookhaven National Laboratory and |
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17 | * Shuchen K. Feng, <feng1@bnl.gov> |
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18 | * |
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19 | * - to be consistent with the original pci.c written by Eric Valette |
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20 | * - added 2nd PCI support for discovery based PCI bridge (e.g. mvme5500/mvme6100) |
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21 | * - added bus support for the expansion of PMCSpan as per request by Peter |
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22 | */ |
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23 | #define PCI_MAIN |
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24 | |
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25 | #include <libcpu/io.h> |
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26 | #include <rtems/bspIo.h> /* printk */ |
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27 | |
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28 | #include <bsp/irq.h> |
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29 | #include <bsp/pci.h> |
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30 | #include <bsp/gtreg.h> |
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31 | #include <bsp/gtpcireg.h> |
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32 | #include <bsp.h> |
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33 | |
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34 | #include <stdio.h> |
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35 | #include <string.h> |
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36 | #include <inttypes.h> |
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37 | |
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38 | #define PCI_DEBUG 0 |
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39 | #define PCI_PRINT 1 |
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40 | |
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41 | /* allow for overriding these definitions */ |
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42 | #ifndef PCI_CONFIG_ADDR |
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43 | #define PCI_CONFIG_ADDR 0xcf8 |
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44 | #endif |
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45 | #ifndef PCI_CONFIG_DATA |
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46 | #define PCI_CONFIG_DATA 0xcfc |
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47 | #endif |
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48 | |
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49 | #ifndef PCI1_CONFIG_ADDR |
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50 | #define PCI1_CONFIG_ADDR 0xc78 |
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51 | #endif |
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52 | #ifndef PCI1_CONFIG_DATA |
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53 | #define PCI1_CONFIG_DATA 0xc7c |
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54 | #endif |
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55 | |
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56 | #define HOSTBRIDGET_ERROR 0xf0000000 |
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57 | |
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58 | #define GT64x60_PCI_CONFIG_ADDR GT64x60_REG_BASE + PCI_CONFIG_ADDR |
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59 | #define GT64x60_PCI_CONFIG_DATA GT64x60_REG_BASE + PCI_CONFIG_DATA |
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60 | |
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61 | #define GT64x60_PCI1_CONFIG_ADDR GT64x60_REG_BASE + PCI1_CONFIG_ADDR |
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62 | #define GT64x60_PCI1_CONFIG_DATA GT64x60_REG_BASE + PCI1_CONFIG_DATA |
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63 | |
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64 | static int numPCIDevs=0; |
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65 | static DiscoveryChipVersion BSP_sysControllerVersion = 0; |
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66 | static BSP_VMEchipTypes BSP_VMEinterface = 0; |
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67 | static rtems_pci_config_t BSP_pci[2]={ |
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68 | {(volatile unsigned char*) (GT64x60_PCI_CONFIG_ADDR), |
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69 | (volatile unsigned char*) (GT64x60_PCI_CONFIG_DATA), |
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70 | 0 /* defined at BSP_pci_configuration */}, |
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71 | {(volatile unsigned char*) (GT64x60_PCI1_CONFIG_ADDR), |
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72 | (volatile unsigned char*) (GT64x60_PCI1_CONFIG_DATA), |
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73 | 0 /* defined at BSP_pci_configuration */} |
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74 | }; |
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75 | |
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76 | /* Pack RegNum,FuncNum,DevNum,BusNum,and ConfigEnable for |
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77 | * PCI Configuration Address Register |
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78 | */ |
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79 | #define pciConfigPack(bus,dev,func,offset)\ |
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80 | ((offset&~3)<<24)|(PCI_DEVFN(dev,func)<<16)|(bus<<8)|0x80 |
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81 | |
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82 | /* |
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83 | * Bit encode for PCI_CONFIG_HEADER_TYPE register |
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84 | */ |
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85 | static unsigned char ucMaxPCIBus=0; |
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86 | |
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87 | /* Please note that PCI0 and PCI1 does not correlate with the busNum 0 and 1. |
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88 | */ |
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89 | static int indirect_pci_read_config_byte(unsigned char bus,unsigned char dev,unsigned char func, |
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90 | unsigned char offset, uint8_t *val) |
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91 | { |
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92 | int n=0; |
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93 | |
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94 | if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) { |
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95 | bus-=BSP_MAX_PCI_BUS_ON_PCI0; |
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96 | n=1; |
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97 | } |
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98 | |
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99 | *val = 0xff; |
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100 | if (offset & ~0xff) return PCIBIOS_BAD_REGISTER_NUMBER; |
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101 | #if 0 |
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102 | printk("addr %x, data %x, pack %x \n", BSP_pci[n].pci_config_addr), |
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103 | BSP_pci[n].config_data,pciConfigPack(bus,dev,func,offset)); |
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104 | #endif |
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105 | |
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106 | out_be32((volatile uint32_t *) BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset)); |
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107 | *val = in_8(BSP_pci[n].pci_config_data + (offset&3)); |
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108 | return PCIBIOS_SUCCESSFUL; |
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109 | } |
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110 | |
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111 | static int indirect_pci_read_config_word(unsigned char bus, unsigned char dev, |
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112 | unsigned char func, unsigned char offset, uint16_t *val) |
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113 | { |
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114 | int n=0; |
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115 | |
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116 | if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) { |
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117 | bus-=BSP_MAX_PCI_BUS_ON_PCI0; |
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118 | n=1; |
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119 | } |
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120 | |
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121 | *val = 0xffff; |
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122 | if ((offset&1)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER; |
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123 | #if 0 |
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124 | printk("addr %x, data %x, pack %x \n", config_addr, |
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125 | config_data,pciConfigPack(bus,dev,func,offset)); |
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126 | #endif |
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127 | out_be32((volatile uint32_t *) BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset)); |
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128 | *val = in_le16((volatile uint16_t *) (BSP_pci[n].pci_config_data + (offset&2))); |
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129 | return PCIBIOS_SUCCESSFUL; |
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130 | } |
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131 | |
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132 | static int indirect_pci_read_config_dword(unsigned char bus, unsigned char dev, |
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133 | unsigned char func, unsigned char offset, uint32_t *val) |
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134 | { |
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135 | int n=0; |
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136 | |
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137 | if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) { |
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138 | bus-=BSP_MAX_PCI_BUS_ON_PCI0; |
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139 | n=1; |
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140 | } |
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141 | |
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142 | *val = 0xffffffff; |
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143 | if ((offset&3)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER; |
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144 | |
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145 | out_be32((volatile uint32_t *)BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset)); |
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146 | *val = in_le32((volatile uint32_t *)BSP_pci[n].pci_config_data); |
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147 | return PCIBIOS_SUCCESSFUL; |
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148 | } |
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149 | |
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150 | static int indirect_pci_write_config_byte(unsigned char bus, unsigned char dev,unsigned char func, unsigned char offset, uint8_t val) |
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151 | { |
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152 | int n=0; |
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153 | |
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154 | if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) { |
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155 | bus-=BSP_MAX_PCI_BUS_ON_PCI0; |
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156 | n=1; |
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157 | } |
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158 | |
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159 | if (offset & ~0xff) return PCIBIOS_BAD_REGISTER_NUMBER; |
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160 | |
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161 | out_be32((volatile uint32_t *)BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset)); |
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162 | out_8((volatile uint8_t *) (BSP_pci[n].pci_config_data + (offset&3)), val); |
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163 | return PCIBIOS_SUCCESSFUL; |
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164 | } |
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165 | |
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166 | static int indirect_pci_write_config_word(unsigned char bus, unsigned char dev,unsigned char func, unsigned char offset, uint16_t val) |
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167 | { |
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168 | int n=0; |
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169 | |
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170 | if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) { |
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171 | bus-=BSP_MAX_PCI_BUS_ON_PCI0; |
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172 | n=1; |
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173 | } |
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174 | |
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175 | if ((offset&1)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER; |
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176 | |
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177 | out_be32((volatile uint32_t *)BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset)); |
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178 | out_le16((volatile uint16_t *)(BSP_pci[n].pci_config_data + (offset&3)), val); |
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179 | return PCIBIOS_SUCCESSFUL; |
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180 | } |
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181 | |
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182 | static int indirect_pci_write_config_dword(unsigned char bus,unsigned char dev,unsigned char func, unsigned char offset, uint32_t val) |
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183 | { |
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184 | int n=0; |
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185 | |
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186 | if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) { |
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187 | bus-=BSP_MAX_PCI_BUS_ON_PCI0; |
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188 | n=1; |
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189 | } |
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190 | |
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191 | if ((offset&3)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER; |
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192 | |
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193 | out_be32((volatile uint32_t *)BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset)); |
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194 | out_le32((volatile uint32_t *)BSP_pci[n].pci_config_data, val); |
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195 | return PCIBIOS_SUCCESSFUL; |
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196 | } |
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197 | |
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198 | const pci_config_access_functions pci_indirect_functions = { |
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199 | indirect_pci_read_config_byte, |
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200 | indirect_pci_read_config_word, |
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201 | indirect_pci_read_config_dword, |
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202 | indirect_pci_write_config_byte, |
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203 | indirect_pci_write_config_word, |
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204 | indirect_pci_write_config_dword |
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205 | }; |
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206 | |
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207 | |
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208 | rtems_pci_config_t BSP_pci_configuration = { |
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209 | (volatile unsigned char*) (GT64x60_PCI_CONFIG_ADDR), |
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210 | (volatile unsigned char*) (GT64x60_PCI_CONFIG_DATA), |
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211 | &pci_indirect_functions}; |
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212 | |
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213 | DiscoveryChipVersion BSP_getDiscoveryChipVersion(void) |
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214 | { |
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215 | return(BSP_sysControllerVersion); |
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216 | } |
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217 | |
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218 | BSP_VMEchipTypes BSP_getVMEchipType(void) |
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219 | { |
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220 | return(BSP_VMEinterface); |
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221 | } |
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222 | |
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223 | /* |
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224 | * This routine determines the maximum bus number in the system. |
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225 | * The PCI_SUBORDINATE_BUS is not supported in GT6426xAB. Thus, |
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226 | * it's not used. |
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227 | * |
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228 | */ |
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229 | int pci_initialize(void) |
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230 | { |
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231 | int deviceFound; |
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232 | unsigned char ucBusNumber, ucSlotNumber, ucFnNumber, ucNumFuncs, data8; |
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233 | uint32_t ulHeader, ulClass, ulDeviceID; |
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234 | #if PCI_DEBUG |
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235 | uint32_t pcidata; |
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236 | #endif |
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237 | |
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238 | /* |
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239 | * Scan PCI0 and PCI1 buses |
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240 | */ |
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241 | for (ucBusNumber=0; ucBusNumber<BSP_MAX_PCI_BUS; ucBusNumber++) { |
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242 | deviceFound=0; |
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243 | for (ucSlotNumber=0;ucSlotNumber<PCI_MAX_DEVICES;ucSlotNumber++) { |
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244 | ucFnNumber = 0; |
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245 | pci_read_config_dword(ucBusNumber, |
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246 | ucSlotNumber, |
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247 | 0, |
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248 | PCI_VENDOR_ID, |
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249 | &ulDeviceID); |
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250 | |
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251 | if( ulDeviceID==PCI_INVALID_VENDORDEVICEID) { |
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252 | /* This slot is empty */ |
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253 | continue; |
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254 | } |
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255 | |
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256 | if (++numPCIDevs > PCI_MAX_DEVICES) { |
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257 | rtems_panic("Too many PCI devices found; increase PCI_MAX_DEVICES in pci.h\n"); |
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258 | } |
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259 | |
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260 | if (!deviceFound) deviceFound=1; |
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261 | switch(ulDeviceID) { |
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262 | case (PCI_VENDOR_ID_MARVELL+(PCI_DEVICE_ID_MARVELL_GT6426xAB<<16)): |
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263 | pci_read_config_byte(0,0,0,PCI_REVISION_ID, &data8); |
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264 | switch(data8) { |
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265 | case 0x10: |
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266 | BSP_sysControllerVersion = GT64260A; |
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267 | #if PCI_PRINT |
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268 | printk("Marvell GT64260A (Discovery I) hostbridge detected at bus%d slot%d\n", |
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269 | ucBusNumber,ucSlotNumber); |
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270 | #endif |
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271 | break; |
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272 | case 0x20: |
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273 | BSP_sysControllerVersion = GT64260B; |
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274 | #if PCI_PRINT |
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275 | printk("Marvell GT64260B (Discovery I) hostbridge detected at bus%d slot%d\n", |
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276 | ucBusNumber,ucSlotNumber); |
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277 | #endif |
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278 | break; |
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279 | default: |
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280 | printk("Undefined revsion of GT64260 chip\n"); |
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281 | break; |
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282 | } |
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283 | break; |
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284 | case PCI_VENDOR_ID_TUNDRA: |
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285 | #if PCI_PRINT |
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286 | printk("TUNDRA PCI-VME bridge detected at bus%d slot%d\n", |
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287 | ucBusNumber,ucSlotNumber); |
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288 | #endif |
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289 | break; |
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290 | case (PCI_VENDOR_ID_DEC+(PCI_DEVICE_ID_DEC_21150<<16)): |
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291 | #if PCI_PRINT |
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292 | printk("DEC21150 PCI-PCI bridge detected at bus%d slot%d\n", |
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293 | ucBusNumber,ucSlotNumber); |
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294 | #endif |
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295 | break; |
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296 | default : |
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297 | #if PCI_PRINT |
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298 | printk("BSP unlisted vendor, Bus%d Slot%d DeviceID 0x%" PRIx32 "\n", |
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299 | ucBusNumber,ucSlotNumber, ulDeviceID); |
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300 | #endif |
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301 | /* Kate Feng : device not supported by BSP needs to remap the IRQ line on mvme5500/mvme6100 */ |
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302 | pci_read_config_byte(ucBusNumber,ucSlotNumber,0,PCI_INTERRUPT_LINE,&data8); |
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303 | if (data8 < BSP_GPP_IRQ_LOWEST_OFFSET) pci_write_config_byte(ucBusNumber, |
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304 | ucSlotNumber,0,PCI_INTERRUPT_LINE,BSP_GPP_IRQ_LOWEST_OFFSET+data8); |
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305 | |
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306 | break; |
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307 | } |
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308 | |
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309 | #if PCI_DEBUG |
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310 | pci_read_config_dword(ucBusNumber, |
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311 | ucSlotNumber, |
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312 | 0, |
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313 | PCI_BASE_ADDRESS_0, |
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314 | &data); |
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315 | printk("Bus%d BASE_ADDRESS_0 0x%x \n",ucBusNumber, data); |
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316 | pci_read_config_dword(ucBusNumber, |
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317 | ucSlotNumber, |
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318 | 0, |
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319 | PCI_BASE_ADDRESS_1, |
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320 | &data); |
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321 | printk("Bus%d BASE_ADDRESS_1 0x%x \n",ucBusNumber, data); |
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322 | pci_read_config_dword(ucBusNumber, |
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323 | ucSlotNumber, |
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324 | 0, |
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325 | PCI_BASE_ADDRESS_2, |
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326 | &data); |
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327 | printk("Bus%d BASE_ADDRESS_2 0x%x \n", ucBusNumber, data); |
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328 | |
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329 | pci_read_config_dword(ucBusNumber, |
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330 | ucSlotNumber, |
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331 | 0, |
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332 | PCI_BASE_ADDRESS_3, |
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333 | &data); |
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334 | printk("Bus%d BASE_ADDRESS_3 0x%x \n", ucBusNumber, data); |
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335 | |
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336 | pci_read_config_word(ucBusNumber, |
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337 | ucSlotNumber, |
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338 | 0, |
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339 | PCI_INTERRUPT_LINE, |
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340 | &sdata); |
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341 | printk("Bus%d INTERRUPT_LINE 0x%x \n", ucBusNumber, sdata); |
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342 | |
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343 | /* We always enable internal memory. */ |
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344 | pci_read_config_dword(ucBusNumber, |
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345 | ucSlotNumber, |
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346 | 0, |
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347 | PCI_MEM_BASE_ADDR, |
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348 | &pcidata); |
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349 | printk("Bus%d MEM_BASE_ADDR 0x%x \n", ucBusNumber,pcidata); |
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350 | |
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351 | /* We always enable internal IO. */ |
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352 | pci_read_config_dword(ucBusNumber, |
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353 | ucSlotNumber, |
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354 | 0, |
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355 | PCI_IO_BASE_ADDR, |
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356 | &pcidata); |
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357 | printk("Bus%d IO_BASE_ADDR 0x%x \n", ucBusNumber,pcidata); |
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358 | #endif |
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359 | |
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360 | pci_read_config_dword(ucBusNumber, |
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361 | ucSlotNumber, |
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362 | 0, |
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363 | PCI_CACHE_LINE_SIZE, |
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364 | &ulHeader); |
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365 | if ((ulHeader>>16)&PCI_HEADER_TYPE_MULTI_FUNCTION) |
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366 | ucNumFuncs=PCI_MAX_FUNCTIONS; |
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367 | else |
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368 | ucNumFuncs=1; |
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369 | |
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370 | #if PCI_DEBUG |
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371 | printk("Bus%d Slot 0x%x HEADER/LAT/CACHE 0x%x \n", |
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372 | ucBusNumber, ucSlotNumber, ulHeader); |
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373 | #endif |
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374 | |
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375 | for (ucFnNumber=1;ucFnNumber<ucNumFuncs;ucFnNumber++) { |
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376 | pci_read_config_dword(ucBusNumber, |
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377 | ucSlotNumber, |
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378 | ucFnNumber, |
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379 | PCI_VENDOR_ID, |
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380 | &ulDeviceID); |
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381 | if (ulDeviceID==PCI_INVALID_VENDORDEVICEID) { |
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382 | /* This slot/function is empty */ |
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383 | continue; |
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384 | } |
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385 | |
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386 | /* This slot/function has a device fitted.*/ |
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387 | pci_read_config_dword(ucBusNumber, |
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388 | ucSlotNumber, |
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389 | ucFnNumber, |
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390 | PCI_CLASS_REVISION, |
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391 | &ulClass); |
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392 | #if PCI_DEBUG |
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393 | printk("Bus%d Slot 0x%x Func %d classID 0x%x \n",ucBusNumber,ucSlotNumber, |
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394 | ucFnNumber, ulClass); |
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395 | #endif |
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396 | |
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397 | } |
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398 | } |
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399 | if (deviceFound) ucMaxPCIBus++; |
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400 | } /* for (ucBusNumber=0; ucBusNumber<BSP_MAX_PCI_BUS; ... */ |
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401 | #if PCI_DEBUG |
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402 | printk("number of PCI buses: %d, numPCIDevs %d\n", |
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403 | pci_bus_count(), numPCIDevs); |
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404 | #endif |
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405 | pci_interface(); |
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406 | return(0); |
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407 | } |
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408 | |
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409 | void FixupPCI( const struct _int_map *bspmap, int (*swizzler)(int,int) ) |
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410 | { |
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411 | } |
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412 | |
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413 | /* |
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414 | * Return the number of PCI buses in the system |
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415 | */ |
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416 | unsigned char pci_bus_count() |
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417 | { |
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418 | return(ucMaxPCIBus); |
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419 | } |
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420 | |
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