[7be6ad9] | 1 | /* |
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| 2 | * pci.c : this file contains basic PCI Io functions. |
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| 3 | * |
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| 4 | * CopyRight (C) 1999 valette@crf.canon.fr |
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| 5 | * |
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| 6 | * This code is heavilly inspired by the public specification of STREAM V2 |
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| 7 | * that can be found at : |
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| 8 | * |
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| 9 | * <http://www.chorus.com/Documentation/index.html> by following |
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| 10 | * the STREAM API Specification Document link. |
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| 11 | * |
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| 12 | * The license and distribution terms for this file may be |
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| 13 | * found in the file LICENSE in this distribution or at |
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[54cb48f] | 14 | * http://www.rtems.com/rtems/license.html. |
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[7be6ad9] | 15 | * |
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[cf599996] | 16 | * pci.c,v 1.2 2002/05/14 17:10:16 joel Exp |
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[16fa78e] | 17 | * |
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[cf599996] | 18 | * Copyright 2004, 2008 Brookhaven National Laboratory and |
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| 19 | * Shuchen K. Feng, <feng1@bnl.gov> |
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| 20 | * |
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| 21 | * - to be consistent with the original pci.c written by Eric Valette |
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| 22 | * - added 2nd PCI support for discovery based PCI bridge (e.g. mvme5500/mvme6100) |
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| 23 | * - added bus support for the expansion of PMCSpan as per request by Peter |
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[7be6ad9] | 24 | */ |
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| 25 | #define PCI_MAIN |
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| 26 | |
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| 27 | #include <libcpu/io.h> |
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| 28 | #include <rtems/bspIo.h> /* printk */ |
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| 29 | |
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[cf599996] | 30 | #include <bsp/irq.h> |
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[7be6ad9] | 31 | #include <bsp/pci.h> |
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| 32 | #include <bsp/gtreg.h> |
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| 33 | #include <bsp/gtpcireg.h> |
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[cf599996] | 34 | #include <bsp.h> |
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[7be6ad9] | 35 | |
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| 36 | #include <stdio.h> |
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| 37 | #include <string.h> |
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| 38 | |
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[ee732739] | 39 | #define PCI_DEBUG 0 |
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[cf599996] | 40 | #define PCI_PRINT 1 |
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[54cb48f] | 41 | |
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| 42 | /* allow for overriding these definitions */ |
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| 43 | #ifndef PCI_CONFIG_ADDR |
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| 44 | #define PCI_CONFIG_ADDR 0xcf8 |
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| 45 | #endif |
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| 46 | #ifndef PCI_CONFIG_DATA |
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| 47 | #define PCI_CONFIG_DATA 0xcfc |
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| 48 | #endif |
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| 49 | |
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| 50 | #ifndef PCI1_CONFIG_ADDR |
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| 51 | #define PCI1_CONFIG_ADDR 0xc78 |
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| 52 | #endif |
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| 53 | #ifndef PCI1_CONFIG_DATA |
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| 54 | #define PCI1_CONFIG_DATA 0xc7c |
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| 55 | #endif |
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[7be6ad9] | 56 | |
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| 57 | #define PCI_INVALID_VENDORDEVICEID 0xffffffff |
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| 58 | #define PCI_MULTI_FUNCTION 0x80 |
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| 59 | #define HOSTBRIDGET_ERROR 0xf0000000 |
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| 60 | |
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[cf599996] | 61 | #define GT64x60_PCI_CONFIG_ADDR GT64x60_REG_BASE + PCI_CONFIG_ADDR |
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| 62 | #define GT64x60_PCI_CONFIG_DATA GT64x60_REG_BASE + PCI_CONFIG_DATA |
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| 63 | |
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| 64 | #define GT64x60_PCI1_CONFIG_ADDR GT64x60_REG_BASE + PCI1_CONFIG_ADDR |
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| 65 | #define GT64x60_PCI1_CONFIG_DATA GT64x60_REG_BASE + PCI1_CONFIG_DATA |
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| 66 | |
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| 67 | static int numPCIDevs=0; |
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| 68 | static DiscoveryChipVersion BSP_sysControllerVersion = 0; |
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| 69 | static BSP_VMEchipTypes BSP_VMEinterface = 0; |
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| 70 | static pci_config BSP_pci[2]={ |
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| 71 | {(volatile unsigned char*) (GT64x60_PCI_CONFIG_ADDR), |
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| 72 | (volatile unsigned char*) (GT64x60_PCI_CONFIG_DATA), |
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| 73 | 0 /* defined at BSP_pci_configuration */}, |
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| 74 | {(volatile unsigned char*) (GT64x60_PCI1_CONFIG_ADDR), |
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| 75 | (volatile unsigned char*) (GT64x60_PCI1_CONFIG_DATA), |
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| 76 | 0 /* defined at BSP_pci_configuration */} |
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| 77 | }; |
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[7be6ad9] | 78 | |
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[6771a9e7] | 79 | extern void pci_interface(void); |
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[7be6ad9] | 80 | |
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| 81 | /* Pack RegNum,FuncNum,DevNum,BusNum,and ConfigEnable for |
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| 82 | * PCI Configuration Address Register |
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| 83 | */ |
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| 84 | #define pciConfigPack(bus,dev,func,offset)\ |
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[cf599996] | 85 | ((offset&~3)<<24)|(PCI_DEVFN(dev,func)<<16)|(bus<<8)|0x80 |
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[7be6ad9] | 86 | |
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| 87 | /* |
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| 88 | * Bit encode for PCI_CONFIG_HEADER_TYPE register |
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| 89 | */ |
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[ea6c5d8] | 90 | unsigned char ucMaxPCIBus=0; |
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[7be6ad9] | 91 | |
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| 92 | /* Please note that PCI0 and PCI1 does not correlate with the busNum 0 and 1. |
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| 93 | */ |
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[cf599996] | 94 | static int indirect_pci_read_config_byte(unsigned char bus,unsigned char dev,unsigned char func, |
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[ee732739] | 95 | unsigned char offset,unsigned char *val) |
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[7be6ad9] | 96 | { |
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[cf599996] | 97 | int n=0; |
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[54cb48f] | 98 | |
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| 99 | if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) { |
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| 100 | bus-=BSP_MAX_PCI_BUS_ON_PCI0; |
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[cf599996] | 101 | n=1; |
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[54cb48f] | 102 | } |
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[cf599996] | 103 | |
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[7be6ad9] | 104 | *val = 0xff; |
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| 105 | if (offset & ~0xff) return PCIBIOS_BAD_REGISTER_NUMBER; |
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[54cb48f] | 106 | #if 0 |
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[cf599996] | 107 | printk("addr %x, data %x, pack %x \n", BSP_pci[n].pci_config_addr), |
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| 108 | BSP_pci[n].config_data,pciConfigPack(bus,dev,func,offset)); |
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[54cb48f] | 109 | #endif |
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[cf599996] | 110 | |
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| 111 | out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset)); |
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| 112 | *val = in_8(BSP_pci[n].pci_config_data + (offset&3)); |
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[7be6ad9] | 113 | return PCIBIOS_SUCCESSFUL; |
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| 114 | } |
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| 115 | |
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[cf599996] | 116 | static int indirect_pci_read_config_word(unsigned char bus, unsigned char dev, |
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[ee732739] | 117 | unsigned char func, unsigned char offset, unsigned short *val) |
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[7be6ad9] | 118 | { |
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[cf599996] | 119 | int n=0; |
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[54cb48f] | 120 | |
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| 121 | if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) { |
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| 122 | bus-=BSP_MAX_PCI_BUS_ON_PCI0; |
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[cf599996] | 123 | n=1; |
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[54cb48f] | 124 | } |
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| 125 | |
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[7be6ad9] | 126 | *val = 0xffff; |
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| 127 | if ((offset&1)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER; |
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[54cb48f] | 128 | #if 0 |
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| 129 | printk("addr %x, data %x, pack %x \n", config_addr, |
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| 130 | config_data,pciConfigPack(bus,dev,func,offset)); |
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| 131 | #endif |
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[cf599996] | 132 | out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset)); |
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| 133 | *val = in_le16(BSP_pci[n].pci_config_data + (offset&2)); |
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[7be6ad9] | 134 | return PCIBIOS_SUCCESSFUL; |
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| 135 | } |
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| 136 | |
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[cf599996] | 137 | static int indirect_pci_read_config_dword(unsigned char bus, unsigned char dev, |
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[ee732739] | 138 | unsigned char func, unsigned char offset, unsigned int *val) |
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[7be6ad9] | 139 | { |
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[cf599996] | 140 | int n=0; |
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[54cb48f] | 141 | |
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| 142 | if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) { |
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| 143 | bus-=BSP_MAX_PCI_BUS_ON_PCI0; |
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[cf599996] | 144 | n=1; |
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[54cb48f] | 145 | } |
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| 146 | |
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[7be6ad9] | 147 | *val = 0xffffffff; |
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| 148 | if ((offset&3)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER; |
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[cf599996] | 149 | |
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| 150 | out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset)); |
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| 151 | *val = in_le32(BSP_pci[n].pci_config_data); |
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[7be6ad9] | 152 | return PCIBIOS_SUCCESSFUL; |
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| 153 | } |
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| 154 | |
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[cf599996] | 155 | static int indirect_pci_write_config_byte(unsigned char bus, unsigned char dev,unsigned char func, unsigned char offset, unsigned char val) |
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[7be6ad9] | 156 | { |
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[cf599996] | 157 | int n=0; |
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[54cb48f] | 158 | |
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| 159 | if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) { |
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| 160 | bus-=BSP_MAX_PCI_BUS_ON_PCI0; |
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[cf599996] | 161 | n=1; |
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[54cb48f] | 162 | } |
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| 163 | |
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[7be6ad9] | 164 | if (offset & ~0xff) return PCIBIOS_BAD_REGISTER_NUMBER; |
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| 165 | |
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[cf599996] | 166 | out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset)); |
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| 167 | out_8(BSP_pci[n].pci_config_data + (offset&3), val); |
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[7be6ad9] | 168 | return PCIBIOS_SUCCESSFUL; |
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| 169 | } |
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| 170 | |
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[cf599996] | 171 | static int indirect_pci_write_config_word(unsigned char bus, unsigned char dev,unsigned char func, unsigned char offset, unsigned short val) |
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[7be6ad9] | 172 | { |
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[cf599996] | 173 | int n=0; |
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[54cb48f] | 174 | |
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| 175 | if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) { |
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| 176 | bus-=BSP_MAX_PCI_BUS_ON_PCI0; |
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[cf599996] | 177 | n=1; |
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[54cb48f] | 178 | } |
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| 179 | |
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[7be6ad9] | 180 | if ((offset&1)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER; |
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[cf599996] | 181 | |
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| 182 | out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset)); |
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| 183 | out_le16(BSP_pci[n].pci_config_data + (offset&3), val); |
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[7be6ad9] | 184 | return PCIBIOS_SUCCESSFUL; |
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| 185 | } |
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| 186 | |
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[cf599996] | 187 | static int indirect_pci_write_config_dword(unsigned char bus,unsigned char dev,unsigned char func, unsigned char offset, unsigned int val) |
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[7be6ad9] | 188 | { |
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[cf599996] | 189 | int n=0; |
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[54cb48f] | 190 | |
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| 191 | if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) { |
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| 192 | bus-=BSP_MAX_PCI_BUS_ON_PCI0; |
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[cf599996] | 193 | n=1; |
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[54cb48f] | 194 | } |
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| 195 | |
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[7be6ad9] | 196 | if ((offset&3)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER; |
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[cf599996] | 197 | |
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| 198 | out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset)); |
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| 199 | out_le32(BSP_pci[n].pci_config_data, val); |
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[7be6ad9] | 200 | return PCIBIOS_SUCCESSFUL; |
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| 201 | } |
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| 202 | |
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[cf599996] | 203 | const pci_config_access_functions pci_indirect_functions = { |
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| 204 | indirect_pci_read_config_byte, |
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| 205 | indirect_pci_read_config_word, |
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| 206 | indirect_pci_read_config_dword, |
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| 207 | indirect_pci_write_config_byte, |
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| 208 | indirect_pci_write_config_word, |
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| 209 | indirect_pci_write_config_dword |
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[54cb48f] | 210 | }; |
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[7be6ad9] | 211 | |
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| 212 | |
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[cf599996] | 213 | pci_config BSP_pci_configuration = { |
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| 214 | (volatile unsigned char*) (GT64x60_PCI_CONFIG_ADDR), |
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| 215 | (volatile unsigned char*) (GT64x60_PCI_CONFIG_DATA), |
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| 216 | &pci_indirect_functions}; |
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| 217 | |
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| 218 | DiscoveryChipVersion BSP_getDiscoveryChipVersion(void) |
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| 219 | { |
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| 220 | return(BSP_sysControllerVersion); |
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| 221 | } |
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| 222 | |
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| 223 | BSP_VMEchipTypes BSP_getVMEchipType(void) |
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| 224 | { |
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| 225 | return(BSP_VMEinterface); |
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| 226 | } |
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[7be6ad9] | 227 | |
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| 228 | /* |
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[54cb48f] | 229 | * This routine determines the maximum bus number in the system. |
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| 230 | * The PCI_SUBORDINATE_BUS is not supported in GT6426xAB. Thus, |
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| 231 | * it's not used. |
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| 232 | * |
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[7be6ad9] | 233 | */ |
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[6771a9e7] | 234 | int pci_initialize(void) |
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[7be6ad9] | 235 | { |
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[54cb48f] | 236 | int deviceFound; |
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[cf599996] | 237 | unsigned char ucBusNumber, ucSlotNumber, ucFnNumber, ucNumFuncs, data8; |
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| 238 | uint32_t ulHeader, ulClass, ulDeviceID; |
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| 239 | #if PCI_DEBUG |
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| 240 | uint32_t pcidata; |
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| 241 | #endif |
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[7be6ad9] | 242 | |
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| 243 | /* |
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[54cb48f] | 244 | * Scan PCI0 and PCI1 buses |
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[7be6ad9] | 245 | */ |
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[54cb48f] | 246 | for (ucBusNumber=0; ucBusNumber<BSP_MAX_PCI_BUS; ucBusNumber++) { |
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| 247 | deviceFound=0; |
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[7be6ad9] | 248 | for (ucSlotNumber=0;ucSlotNumber<PCI_MAX_DEVICES;ucSlotNumber++) { |
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| 249 | ucFnNumber = 0; |
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[54cb48f] | 250 | pci_read_config_dword(ucBusNumber, |
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[7be6ad9] | 251 | ucSlotNumber, |
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| 252 | 0, |
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[54cb48f] | 253 | PCI_VENDOR_ID, |
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[7be6ad9] | 254 | &ulDeviceID); |
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| 255 | |
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| 256 | if( ulDeviceID==PCI_INVALID_VENDORDEVICEID) { |
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| 257 | /* This slot is empty */ |
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| 258 | continue; |
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| 259 | } |
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| 260 | |
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[54cb48f] | 261 | if (++numPCIDevs > PCI_MAX_DEVICES) { |
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| 262 | BSP_panic("Too many PCI devices found; increase PCI_MAX_DEVICES in pci.h\n"); |
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[7be6ad9] | 263 | } |
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| 264 | |
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[54cb48f] | 265 | if (!deviceFound) deviceFound=1; |
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[7be6ad9] | 266 | switch(ulDeviceID) { |
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| 267 | case (PCI_VENDOR_ID_MARVELL+(PCI_DEVICE_ID_MARVELL_GT6426xAB<<16)): |
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[cf599996] | 268 | pci_read_config_byte(0,0,0,PCI_REVISION_ID, &data8); |
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| 269 | switch(data8) { |
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| 270 | case 0x10: |
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| 271 | BSP_sysControllerVersion = GT64260A; |
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[7be6ad9] | 272 | #if PCI_PRINT |
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[cf599996] | 273 | printk("Marvell GT64260A (Discovery I) hostbridge detected at bus%d slot%d\n", |
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[54cb48f] | 274 | ucBusNumber,ucSlotNumber); |
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[7be6ad9] | 275 | #endif |
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[cf599996] | 276 | break; |
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| 277 | case 0x20: |
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| 278 | BSP_sysControllerVersion = GT64260B; |
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[7be6ad9] | 279 | #if PCI_PRINT |
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[cf599996] | 280 | printk("Marvell GT64260B (Discovery I) hostbridge detected at bus%d slot%d\n", |
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[54cb48f] | 281 | ucBusNumber,ucSlotNumber); |
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[7be6ad9] | 282 | #endif |
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[cf599996] | 283 | break; |
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| 284 | default: |
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| 285 | printk("Undefined revsion of GT64260 chip\n"); |
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| 286 | break; |
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| 287 | } |
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| 288 | break; |
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[7be6ad9] | 289 | case PCI_VENDOR_ID_TUNDRA: |
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| 290 | #if PCI_PRINT |
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[54cb48f] | 291 | printk("TUNDRA PCI-VME bridge detected at bus%d slot%d\n", |
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| 292 | ucBusNumber,ucSlotNumber); |
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[7be6ad9] | 293 | #endif |
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| 294 | break; |
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[54cb48f] | 295 | case (PCI_VENDOR_ID_DEC+(PCI_DEVICE_ID_DEC_21150<<16)): |
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[cf599996] | 296 | #if PCI_PRINT |
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[54cb48f] | 297 | printk("DEC21150 PCI-PCI bridge detected at bus%d slot%d\n", |
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| 298 | ucBusNumber,ucSlotNumber); |
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[7be6ad9] | 299 | #endif |
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[54cb48f] | 300 | break; |
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| 301 | default : |
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[cf599996] | 302 | #if PCI_PRINT |
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[54cb48f] | 303 | printk("BSP unlisted vendor, Bus%d Slot%d DeviceID 0x%x \n", |
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| 304 | ucBusNumber,ucSlotNumber, ulDeviceID); |
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[cf599996] | 305 | #endif |
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| 306 | /* Kate Feng : device not supported by BSP needs to remap the IRQ line on mvme5500/mvme6100 */ |
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| 307 | pci_read_config_byte(ucBusNumber,ucSlotNumber,0,PCI_INTERRUPT_LINE,&data8); |
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| 308 | if (data8 < BSP_GPP_IRQ_LOWEST_OFFSET) pci_write_config_byte(ucBusNumber, |
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| 309 | ucSlotNumber,0,PCI_INTERRUPT_LINE,BSP_GPP_IRQ_LOWEST_OFFSET+data8); |
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| 310 | |
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[7be6ad9] | 311 | break; |
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| 312 | } |
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[54cb48f] | 313 | |
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[7be6ad9] | 314 | #if PCI_DEBUG |
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[54cb48f] | 315 | pci_read_config_dword(ucBusNumber, |
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[7be6ad9] | 316 | ucSlotNumber, |
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| 317 | 0, |
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[54cb48f] | 318 | PCI_BASE_ADDRESS_0, |
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[7be6ad9] | 319 | &data); |
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[54cb48f] | 320 | printk("Bus%d BASE_ADDRESS_0 0x%x \n",ucBusNumber, data); |
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| 321 | pci_read_config_dword(ucBusNumber, |
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[7be6ad9] | 322 | ucSlotNumber, |
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| 323 | 0, |
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[54cb48f] | 324 | PCI_BASE_ADDRESS_1, |
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[7be6ad9] | 325 | &data); |
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[54cb48f] | 326 | printk("Bus%d BASE_ADDRESS_1 0x%x \n",ucBusNumber, data); |
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| 327 | pci_read_config_dword(ucBusNumber, |
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[7be6ad9] | 328 | ucSlotNumber, |
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| 329 | 0, |
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[54cb48f] | 330 | PCI_BASE_ADDRESS_2, |
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[7be6ad9] | 331 | &data); |
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[54cb48f] | 332 | printk("Bus%d BASE_ADDRESS_2 0x%x \n", ucBusNumber, data); |
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[7be6ad9] | 333 | |
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[54cb48f] | 334 | pci_read_config_dword(ucBusNumber, |
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[7be6ad9] | 335 | ucSlotNumber, |
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| 336 | 0, |
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[54cb48f] | 337 | PCI_BASE_ADDRESS_3, |
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[7be6ad9] | 338 | &data); |
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[54cb48f] | 339 | printk("Bus%d BASE_ADDRESS_3 0x%x \n", ucBusNumber, data); |
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[7be6ad9] | 340 | |
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[54cb48f] | 341 | pci_read_config_word(ucBusNumber, |
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[7be6ad9] | 342 | ucSlotNumber, |
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| 343 | 0, |
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[54cb48f] | 344 | PCI_INTERRUPT_LINE, |
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[7be6ad9] | 345 | &sdata); |
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[54cb48f] | 346 | printk("Bus%d INTERRUPT_LINE 0x%x \n", ucBusNumber, sdata); |
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[7be6ad9] | 347 | |
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| 348 | /* We always enable internal memory. */ |
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[54cb48f] | 349 | pci_read_config_dword(ucBusNumber, |
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[7be6ad9] | 350 | ucSlotNumber, |
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| 351 | 0, |
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[54cb48f] | 352 | PCI_MEM_BASE_ADDR, |
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[7be6ad9] | 353 | &pcidata); |
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[54cb48f] | 354 | printk("Bus%d MEM_BASE_ADDR 0x%x \n", ucBusNumber,pcidata); |
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[7be6ad9] | 355 | |
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| 356 | /* We always enable internal IO. */ |
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[54cb48f] | 357 | pci_read_config_dword(ucBusNumber, |
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[7be6ad9] | 358 | ucSlotNumber, |
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| 359 | 0, |
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[54cb48f] | 360 | PCI_IO_BASE_ADDR, |
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[7be6ad9] | 361 | &pcidata); |
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[54cb48f] | 362 | printk("Bus%d IO_BASE_ADDR 0x%x \n", ucBusNumber,pcidata); |
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[7be6ad9] | 363 | #endif |
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| 364 | |
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[54cb48f] | 365 | pci_read_config_dword(ucBusNumber, |
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[7be6ad9] | 366 | ucSlotNumber, |
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| 367 | 0, |
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[54cb48f] | 368 | PCI_CACHE_LINE_SIZE, |
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[7be6ad9] | 369 | &ulHeader); |
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| 370 | if ((ulHeader>>16)&PCI_MULTI_FUNCTION) |
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| 371 | ucNumFuncs=PCI_MAX_FUNCTIONS; |
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| 372 | else |
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| 373 | ucNumFuncs=1; |
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| 374 | |
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| 375 | #if PCI_DEBUG |
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[54cb48f] | 376 | printk("Bus%d Slot 0x%x HEADER/LAT/CACHE 0x%x \n", |
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| 377 | ucBusNumber, ucSlotNumber, ulHeader); |
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| 378 | #endif |
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[7be6ad9] | 379 | |
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| 380 | for (ucFnNumber=1;ucFnNumber<ucNumFuncs;ucFnNumber++) { |
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[54cb48f] | 381 | pci_read_config_dword(ucBusNumber, |
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[7be6ad9] | 382 | ucSlotNumber, |
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| 383 | ucFnNumber, |
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[54cb48f] | 384 | PCI_VENDOR_ID, |
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[7be6ad9] | 385 | &ulDeviceID); |
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| 386 | if (ulDeviceID==PCI_INVALID_VENDORDEVICEID) { |
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| 387 | /* This slot/function is empty */ |
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| 388 | continue; |
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| 389 | } |
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| 390 | |
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| 391 | /* This slot/function has a device fitted.*/ |
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[54cb48f] | 392 | pci_read_config_dword(ucBusNumber, |
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[7be6ad9] | 393 | ucSlotNumber, |
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| 394 | ucFnNumber, |
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[54cb48f] | 395 | PCI_CLASS_REVISION, |
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| 396 | &ulClass); |
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| 397 | #if PCI_DEBUG |
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| 398 | printk("Bus%d Slot 0x%x Func %d classID 0x%x \n",ucBusNumber,ucSlotNumber, |
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[7be6ad9] | 399 | ucFnNumber, ulClass); |
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[54cb48f] | 400 | #endif |
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[7be6ad9] | 401 | |
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| 402 | } |
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| 403 | } |
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[54cb48f] | 404 | if (deviceFound) ucMaxPCIBus++; |
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| 405 | } /* for (ucBusNumber=0; ucBusNumber<BSP_MAX_PCI_BUS; ... */ |
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| 406 | #if PCI_DEBUG |
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| 407 | printk("number of PCI buses: %d, numPCIDevs %d\n", |
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| 408 | pci_bus_count(), numPCIDevs); |
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| 409 | #endif |
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[cf599996] | 410 | pci_interface(); |
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[54cb48f] | 411 | return(0); |
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| 412 | } |
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[3bfb6ef] | 413 | |
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[54cb48f] | 414 | void FixupPCI( struct _int_map *bspmap, int (*swizzler)(int,int) ) |
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| 415 | { |
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[7be6ad9] | 416 | } |
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| 417 | |
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| 418 | /* |
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| 419 | * Return the number of PCI buses in the system |
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| 420 | */ |
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[4cbb57da] | 421 | unsigned char pci_bus_count() |
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[7be6ad9] | 422 | { |
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| 423 | return(ucMaxPCIBus); |
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| 424 | } |
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| 425 | |
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