source: rtems/c/src/lib/libbsp/powerpc/mvme5500/pci/gtpcireg.h @ ac7af4a

4.104.115
Last change on this file since ac7af4a was ac7af4a, checked in by Ralf Corsepius <ralf.corsepius@…>, on Nov 30, 2009 at 4:37:44 AM

Whitespace removal.

  • Property mode set to 100644
File size: 4.4 KB
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1/*      $NetBSD: gtpcireg.h,v 1.2 2003/03/24 17:03:18 matt Exp $        */
2
3/*
4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 *    must display the following acknowledgement:
17 *      This product includes software developed for the NetBSD Project by
18 *      Allegro Networks, Inc., and Wasabi Systems, Inc.
19 * 4. The name of Allegro Networks, Inc. may not be used to endorse
20 *    or promote products derived from this software without specific prior
21 *    written permission.
22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse
23 *    or promote products derived from this software without specific prior
24 *    written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND
27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC.
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 */
39#define PCI_ARBCTL_EN   (1<<31)
40
41#define  PCI_COMMAND_SB_DIS     0x2000  /* PCI configuration read will stop
42                                         * acting as sync barrier transactin
43                                         */
44
45#define PCI_MEM_BASE_ADDR PCI_BASE_ADDRESS_4
46
47#define PCI_IO_BASE_ADDR  PCI_BASE_ADDRESS_5
48
49#define  PCI_STATUS_CLRERR_MASK 0xf9000000 /* <SKF> */
50
51#define PCI_BARE_IntMemEn     0x200
52
53#define PCI_ACCCTLBASEL_PrefetchEn     0x0001000
54#define PCI_ACCCTLBASEL_RdPrefetch     0x0010000
55#define PCI_ACCCTLBASEL_RdLinePrefetch 0x0020000
56#define PCI_ACCCTLBASEL_RdMulPrefetch  0x0040000
57#define PCI_ACCCTLBASEL_WBurst_8_QW    0x0100000
58#define PCI_ACCCTLBASEL_PCISwap_NoSwap 0x1000000
59
60#define PCI0_P2P_CONFIG                         0x1d14
61#define PCI_SNOOP_BASE0_LOW                     0x1f00
62#define PCI_SNOOP_BASE0_HIGH                    0x1f04
63#define PCI_SNOOP_TOP0                          0x1f08
64
65#define PCI0_SCS0_BAR_SIZE                      0x0c08
66#define PCI0_SCS1_BAR_SIZE                      0x0d08
67#define PCI0_SCS2_BAR_SIZE                      0x0c0c
68#define PCI0_SCS3_BAR_SIZE                      0x0d0c
69
70#define PCI0_BASE_ADDR_REG_ENABLE               0x0c3c
71#define PCI0_ARBITER_CNTL                       0x1d00
72#define PCI0_ACCESS_CNTL_BASE0_LOW              0x1e00
73#define PCI0_ACCESS_CNTL_BASE0_HIGH             0x1e04
74#define PCI0_ACCESS_CNTL_BASE0_TOP              0x1e08
75
76#define PCI0_ACCESS_CNTL_BASE1_LOW              0x1e10
77#define PCI0_ACCESS_CNTL_BASE1_HIGH             0x1e14
78#define PCI0_ACCESS_CNTL_BASE1_TOP              0x1e18
79
80#define PCI1_BASE_ADDR_REG_ENABLE               0x0cbc
81#define PCI1_ARBITER_CNTL                       0x1d80
82#define PCI1_ACCESS_CNTL_BASE0_LOW              0x1e80
83#define PCI1_ACCESS_CNTL_BASE0_HIGH             0x1e84
84#define PCI1_ACCESS_CNTL_BASE0_TOP              0x1e88
85
86#define PCI1_ACCESS_CNTL_BASE1_LOW              0x1e90
87#define PCI1_ACCESS_CNTL_BASE1_HIGH             0x1e94
88#define PCI1_ACCESS_CNTL_BASE1_TOP              0x1e98
89
90#define PCI_SNOOP_BASE1_LOW                     0x1f10
91#define PCI_SNOOP_BASE1_HIGH                    0x1f14
92#define PCI_SNOOP_TOP1                          0x1f18
93
94#define PCI0_CMD_CNTL                           0xc00
95
96#define PCI1_P2P_CONFIG                         0x1d94
97#define PCI1_CMD_CNTL                           0xc80
98#define PCI1_CONFIG_ADDR                        0xc78
99#define PCI1_CONFIG_DATA                        0xc7c
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