[7be6ad9] | 1 | /* $NetBSD: gtpcireg.h,v 1.2 2003/03/24 17:03:18 matt Exp $ */ |
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| 2 | |
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| 3 | /* |
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| 4 | * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. |
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| 5 | * All rights reserved. |
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| 6 | * |
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| 7 | * Redistribution and use in source and binary forms, with or without |
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| 8 | * modification, are permitted provided that the following conditions |
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| 9 | * are met: |
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| 10 | * 1. Redistributions of source code must retain the above copyright |
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| 11 | * notice, this list of conditions and the following disclaimer. |
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| 12 | * 2. Redistributions in binary form must reproduce the above copyright |
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| 13 | * notice, this list of conditions and the following disclaimer in the |
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| 14 | * documentation and/or other materials provided with the distribution. |
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| 15 | * 3. All advertising materials mentioning features or use of this software |
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| 16 | * must display the following acknowledgement: |
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| 17 | * This product includes software developed for the NetBSD Project by |
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| 18 | * Allegro Networks, Inc., and Wasabi Systems, Inc. |
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| 19 | * 4. The name of Allegro Networks, Inc. may not be used to endorse |
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| 20 | * or promote products derived from this software without specific prior |
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| 21 | * written permission. |
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| 22 | * 5. The name of Wasabi Systems, Inc. may not be used to endorse |
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| 23 | * or promote products derived from this software without specific prior |
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| 24 | * written permission. |
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| 25 | * |
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| 26 | * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND |
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| 27 | * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, |
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| 28 | * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY |
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| 29 | * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 30 | * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. |
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| 31 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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| 32 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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| 33 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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| 34 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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| 35 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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| 36 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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| 37 | * POSSIBILITY OF SUCH DAMAGE. |
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| 38 | */ |
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| 39 | #define PCI_ARBCTL_EN (1<<31) |
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| 40 | |
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[54cb48f] | 41 | #define PCI_COMMAND_SB_DIS 0x2000 /* PCI configuration read will stop |
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| 42 | * acting as sync barrier transactin |
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| 43 | */ |
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| 44 | |
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| 45 | #define PCI_MEM_BASE_ADDR PCI_BASE_ADDRESS_4 |
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| 46 | |
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| 47 | #define PCI_IO_BASE_ADDR PCI_BASE_ADDRESS_5 |
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| 48 | |
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| 49 | #define PCI_STATUS_CLRERR_MASK 0xf9000000 /* <SKF> */ |
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| 50 | |
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[7be6ad9] | 51 | #define PCI_BARE_IntMemEn 0x200 |
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| 52 | |
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| 53 | #define PCI_ACCCTLBASEL_PrefetchEn 0x0001000 |
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| 54 | #define PCI_ACCCTLBASEL_RdPrefetch 0x0010000 |
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| 55 | #define PCI_ACCCTLBASEL_RdLinePrefetch 0x0020000 |
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| 56 | #define PCI_ACCCTLBASEL_RdMulPrefetch 0x0040000 |
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| 57 | #define PCI_ACCCTLBASEL_WBurst_8_QW 0x0100000 |
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| 58 | #define PCI_ACCCTLBASEL_PCISwap_NoSwap 0x1000000 |
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| 59 | |
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| 60 | #define PCI0_P2P_CONFIG 0x1d14 |
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[ac7af4a] | 61 | #define PCI_SNOOP_BASE0_LOW 0x1f00 |
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| 62 | #define PCI_SNOOP_BASE0_HIGH 0x1f04 |
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[7be6ad9] | 63 | #define PCI_SNOOP_TOP0 0x1f08 |
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| 64 | |
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| 65 | #define PCI0_SCS0_BAR_SIZE 0x0c08 |
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| 66 | #define PCI0_SCS1_BAR_SIZE 0x0d08 |
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| 67 | #define PCI0_SCS2_BAR_SIZE 0x0c0c |
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| 68 | #define PCI0_SCS3_BAR_SIZE 0x0d0c |
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| 69 | |
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| 70 | #define PCI0_BASE_ADDR_REG_ENABLE 0x0c3c |
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| 71 | #define PCI0_ARBITER_CNTL 0x1d00 |
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| 72 | #define PCI0_ACCESS_CNTL_BASE0_LOW 0x1e00 |
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| 73 | #define PCI0_ACCESS_CNTL_BASE0_HIGH 0x1e04 |
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| 74 | #define PCI0_ACCESS_CNTL_BASE0_TOP 0x1e08 |
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| 75 | |
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| 76 | #define PCI0_ACCESS_CNTL_BASE1_LOW 0x1e10 |
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| 77 | #define PCI0_ACCESS_CNTL_BASE1_HIGH 0x1e14 |
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| 78 | #define PCI0_ACCESS_CNTL_BASE1_TOP 0x1e18 |
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| 79 | |
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| 80 | #define PCI1_BASE_ADDR_REG_ENABLE 0x0cbc |
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| 81 | #define PCI1_ARBITER_CNTL 0x1d80 |
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| 82 | #define PCI1_ACCESS_CNTL_BASE0_LOW 0x1e80 |
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| 83 | #define PCI1_ACCESS_CNTL_BASE0_HIGH 0x1e84 |
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| 84 | #define PCI1_ACCESS_CNTL_BASE0_TOP 0x1e88 |
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| 85 | |
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| 86 | #define PCI1_ACCESS_CNTL_BASE1_LOW 0x1e90 |
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| 87 | #define PCI1_ACCESS_CNTL_BASE1_HIGH 0x1e94 |
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| 88 | #define PCI1_ACCESS_CNTL_BASE1_TOP 0x1e98 |
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| 89 | |
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[ac7af4a] | 90 | #define PCI_SNOOP_BASE1_LOW 0x1f10 |
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| 91 | #define PCI_SNOOP_BASE1_HIGH 0x1f14 |
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[7be6ad9] | 92 | #define PCI_SNOOP_TOP1 0x1f18 |
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| 93 | |
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| 94 | #define PCI0_CMD_CNTL 0xc00 |
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| 95 | |
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| 96 | #define PCI1_P2P_CONFIG 0x1d94 |
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| 97 | #define PCI1_CMD_CNTL 0xc80 |
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| 98 | #define PCI1_CONFIG_ADDR 0xc78 |
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| 99 | #define PCI1_CONFIG_DATA 0xc7c |
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