source: rtems/c/src/lib/libbsp/powerpc/mvme5500/network/if_1GHz/pcireg.h @ ee732739

4.104.114.84.9
Last change on this file since ee732739 was ee732739, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 13, 2007 at 2:26:24 PM

2007-09-07 Kate Feng <feng1@…>

  • ChangeLog?, Makefile.am, README, README.booting, README.irq, preinstall.am, GT64260/MVME5500I2C.c, include/bsp.h, irq/irq.c, irq/irq.h, irq/irq_init.c, pci/detect_host_bridge.c, pci/pci.c, pci/pci_interface.c, pci/pcifinddevice.c, start/preload.S, startup/bspclean.c, startup/bspstart.c, startup/pgtbl_activate.c, startup/reboot.c, vectors/bspException.h, vectors/exceptionhandler.c: Merge my improvements in this BSP including a new network driver for the 1GHz NIC.
  • network/if_100MHz/GT64260eth.c, network/if_100MHz/GT64260eth.h, network/if_100MHz/GT64260ethreg.h, network/if_100MHz/Makefile.am, network/if_1GHz/Makefile.am, network/if_1GHz/POSSIBLEBUG, network/if_1GHz/if_wm.c, network/if_1GHz/if_wmreg.h, network/if_1GHz/pci_map.c, network/if_1GHz/pcireg.h: New files.
  • Property mode set to 100644
File size: 12.9 KB
Line 
1/*      $NetBSD: pcireg.h,v 1.44 2003/12/02 16:31:06 briggs Exp $       */
2
3/*
4 * Copyright (c) 1995, 1996, 1999, 2000
5 *     Christopher G. Demetriou.  All rights reserved.
6 * Copyright (c) 1994, 1996 Charles M. Hannum.  All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 *    must display the following acknowledgement:
18 *      This product includes software developed by Charles M. Hannum.
19 * 4. The name of the author may not be used to endorse or promote products
20 *    derived from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34/*
35 * PCI Class and Revision Register; defines type and revision of device.
36 */
37#define PCI_CLASS_REG                   0x08
38
39#define PCI_CLASS_SHIFT                         24
40#define PCI_CLASS_MASK                          0xff
41#define PCI_CLASS(cr) \
42            (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK)
43
44#define PCI_SUBCLASS_SHIFT                      16
45#define PCI_SUBCLASS_MASK                       0xff
46#define PCI_SUBCLASS(cr) \
47            (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK)
48
49#define PCI_INTERFACE_SHIFT                     8
50#define PCI_INTERFACE_MASK                      0xff
51#define PCI_INTERFACE(cr) \
52            (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK)
53
54#define PCI_REVISION_SHIFT                      0
55#define PCI_REVISION_MASK                       0xff
56#define PCI_REVISION(cr) \
57            (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK)
58
59#define PCI_CLASS_CODE(mainclass, subclass, interface) \
60            ((((mainclass) & PCI_CLASS_MASK) << PCI_CLASS_SHIFT) | \
61             (((subclass) & PCI_SUBCLASS_MASK) << PCI_SUBCLASS_SHIFT) | \
62             (((interface) & PCI_INTERFACE_MASK) << PCI_INTERFACE_SHIFT))
63
64/* base classes */
65#define PCI_CLASS_PREHISTORIC                   0x00
66#define PCI_CLASS_MASS_STORAGE                  0x01
67#define PCI_CLASS_NETWORK                       0x02
68#define PCI_CLASS_DISPLAY                       0x03
69#define PCI_CLASS_MULTIMEDIA                    0x04
70#define PCI_CLASS_MEMORY                        0x05
71#define PCI_CLASS_BRIDGE                        0x06
72#define PCI_CLASS_COMMUNICATIONS                0x07
73#define PCI_CLASS_SYSTEM                        0x08
74#define PCI_CLASS_INPUT                         0x09
75#define PCI_CLASS_DOCK                          0x0a
76#define PCI_CLASS_PROCESSOR                     0x0b
77#define PCI_CLASS_SERIALBUS                     0x0c
78#define PCI_CLASS_WIRELESS                      0x0d
79#define PCI_CLASS_I2O                           0x0e
80#define PCI_CLASS_SATCOM                        0x0f
81#define PCI_CLASS_CRYPTO                        0x10
82#define PCI_CLASS_DASP                          0x11
83#define PCI_CLASS_UNDEFINED                     0xff
84
85/* 0x00 prehistoric subclasses */
86#define PCI_SUBCLASS_PREHISTORIC_MISC           0x00
87#define PCI_SUBCLASS_PREHISTORIC_VGA            0x01
88
89/* 0x01 mass storage subclasses */
90#define PCI_SUBCLASS_MASS_STORAGE_SCSI          0x00
91#define PCI_SUBCLASS_MASS_STORAGE_IDE           0x01
92#define PCI_SUBCLASS_MASS_STORAGE_FLOPPY        0x02
93#define PCI_SUBCLASS_MASS_STORAGE_IPI           0x03
94#define PCI_SUBCLASS_MASS_STORAGE_RAID          0x04
95#define PCI_SUBCLASS_MASS_STORAGE_ATA           0x05
96#define PCI_SUBCLASS_MASS_STORAGE_SATA          0x06
97#define PCI_SUBCLASS_MASS_STORAGE_MISC          0x80
98
99/* 0x02 network subclasses */
100#define PCI_SUBCLASS_NETWORK_ETHERNET           0x00
101#define PCI_SUBCLASS_NETWORK_TOKENRING          0x01
102#define PCI_SUBCLASS_NETWORK_FDDI               0x02
103#define PCI_SUBCLASS_NETWORK_ATM                0x03
104#define PCI_SUBCLASS_NETWORK_ISDN               0x04
105#define PCI_SUBCLASS_NETWORK_WORLDFIP           0x05
106#define PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP     0x06
107#define PCI_SUBCLASS_NETWORK_MISC               0x80
108
109/* 0x03 display subclasses */
110#define PCI_SUBCLASS_DISPLAY_VGA                0x00
111#define PCI_SUBCLASS_DISPLAY_XGA                0x01
112#define PCI_SUBCLASS_DISPLAY_3D                 0x02
113#define PCI_SUBCLASS_DISPLAY_MISC               0x80
114
115/* 0x04 multimedia subclasses */
116#define PCI_SUBCLASS_MULTIMEDIA_VIDEO           0x00
117#define PCI_SUBCLASS_MULTIMEDIA_AUDIO           0x01
118#define PCI_SUBCLASS_MULTIMEDIA_TELEPHONY       0x02
119#define PCI_SUBCLASS_MULTIMEDIA_MISC            0x80
120
121/* 0x05 memory subclasses */
122#define PCI_SUBCLASS_MEMORY_RAM                 0x00
123#define PCI_SUBCLASS_MEMORY_FLASH               0x01
124#define PCI_SUBCLASS_MEMORY_MISC                0x80
125
126/* 0x06 bridge subclasses */
127#define PCI_SUBCLASS_BRIDGE_HOST                0x00
128#define PCI_SUBCLASS_BRIDGE_ISA                 0x01
129#define PCI_SUBCLASS_BRIDGE_EISA                0x02
130#define PCI_SUBCLASS_BRIDGE_MC                  0x03    /* XXX _MCA? */
131#define PCI_SUBCLASS_BRIDGE_PCI                 0x04
132#define PCI_SUBCLASS_BRIDGE_PCMCIA              0x05
133#define PCI_SUBCLASS_BRIDGE_NUBUS               0x06
134#define PCI_SUBCLASS_BRIDGE_CARDBUS             0x07
135#define PCI_SUBCLASS_BRIDGE_RACEWAY             0x08
136#define PCI_SUBCLASS_BRIDGE_STPCI               0x09
137#define PCI_SUBCLASS_BRIDGE_INFINIBAND          0x0a
138#define PCI_SUBCLASS_BRIDGE_MISC                0x80
139
140/* 0x07 communications subclasses */
141#define PCI_SUBCLASS_COMMUNICATIONS_SERIAL      0x00
142#define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL    0x01
143#define PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL    0x02
144#define PCI_SUBCLASS_COMMUNICATIONS_MODEM       0x03
145#define PCI_SUBCLASS_COMMUNICATIONS_GPIB        0x04
146#define PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD   0x05
147#define PCI_SUBCLASS_COMMUNICATIONS_MISC        0x80
148
149/* 0x08 system subclasses */
150#define PCI_SUBCLASS_SYSTEM_PIC                 0x00
151#define PCI_SUBCLASS_SYSTEM_DMA                 0x01
152#define PCI_SUBCLASS_SYSTEM_TIMER               0x02
153#define PCI_SUBCLASS_SYSTEM_RTC                 0x03
154#define PCI_SUBCLASS_SYSTEM_PCIHOTPLUG          0x04
155#define PCI_SUBCLASS_SYSTEM_MISC                0x80
156
157/* 0x09 input subclasses */
158#define PCI_SUBCLASS_INPUT_KEYBOARD             0x00
159#define PCI_SUBCLASS_INPUT_DIGITIZER            0x01
160#define PCI_SUBCLASS_INPUT_MOUSE                0x02
161#define PCI_SUBCLASS_INPUT_SCANNER              0x03
162#define PCI_SUBCLASS_INPUT_GAMEPORT             0x04
163#define PCI_SUBCLASS_INPUT_MISC                 0x80
164
165/* 0x0a dock subclasses */
166#define PCI_SUBCLASS_DOCK_GENERIC               0x00
167#define PCI_SUBCLASS_DOCK_MISC                  0x80
168
169/* 0x0b processor subclasses */
170#define PCI_SUBCLASS_PROCESSOR_386              0x00
171#define PCI_SUBCLASS_PROCESSOR_486              0x01
172#define PCI_SUBCLASS_PROCESSOR_PENTIUM          0x02
173#define PCI_SUBCLASS_PROCESSOR_ALPHA            0x10
174#define PCI_SUBCLASS_PROCESSOR_POWERPC          0x20
175#define PCI_SUBCLASS_PROCESSOR_MIPS             0x30
176#define PCI_SUBCLASS_PROCESSOR_COPROC           0x40
177
178/* 0x0c serial bus subclasses */
179#define PCI_SUBCLASS_SERIALBUS_FIREWIRE         0x00
180#define PCI_SUBCLASS_SERIALBUS_ACCESS           0x01
181#define PCI_SUBCLASS_SERIALBUS_SSA              0x02
182#define PCI_SUBCLASS_SERIALBUS_USB              0x03
183#define PCI_SUBCLASS_SERIALBUS_FIBER            0x04    /* XXX _FIBRECHANNEL */
184#define PCI_SUBCLASS_SERIALBUS_SMBUS            0x05
185#define PCI_SUBCLASS_SERIALBUS_INFINIBAND       0x06
186#define PCI_SUBCLASS_SERIALBUS_IPMI             0x07
187#define PCI_SUBCLASS_SERIALBUS_SERCOS           0x08
188#define PCI_SUBCLASS_SERIALBUS_CANBUS           0x09
189
190/* 0x0d wireless subclasses */
191#define PCI_SUBCLASS_WIRELESS_IRDA              0x00
192#define PCI_SUBCLASS_WIRELESS_CONSUMERIR        0x01
193#define PCI_SUBCLASS_WIRELESS_RF                0x10
194#define PCI_SUBCLASS_WIRELESS_BLUETOOTH         0x11
195#define PCI_SUBCLASS_WIRELESS_BROADBAND         0x12
196#define PCI_SUBCLASS_WIRELESS_802_11A           0x20
197#define PCI_SUBCLASS_WIRELESS_802_11B           0x21
198#define PCI_SUBCLASS_WIRELESS_MISC              0x80
199
200/* 0x0e I2O (Intelligent I/O) subclasses */
201#define PCI_SUBCLASS_I2O_STANDARD               0x00
202
203/* 0x0f satellite communication subclasses */
204/*      PCI_SUBCLASS_SATCOM_???                 0x00    / * XXX ??? */
205#define PCI_SUBCLASS_SATCOM_TV                  0x01
206#define PCI_SUBCLASS_SATCOM_AUDIO               0x02
207#define PCI_SUBCLASS_SATCOM_VOICE               0x03
208#define PCI_SUBCLASS_SATCOM_DATA                0x04
209
210/* 0x10 encryption/decryption subclasses */
211#define PCI_SUBCLASS_CRYPTO_NETCOMP             0x00
212#define PCI_SUBCLASS_CRYPTO_ENTERTAINMENT       0x10
213#define PCI_SUBCLASS_CRYPTO_MISC                0x80
214
215/* 0x11 data acquisition and signal processing subclasses */
216#define PCI_SUBCLASS_DASP_DPIO                  0x00
217#define PCI_SUBCLASS_DASP_TIMEFREQ              0x01
218#define PCI_SUBCLASS_DASP_SYNC                  0x10
219#define PCI_SUBCLASS_DASP_MGMT                  0x20
220#define PCI_SUBCLASS_DASP_MISC                  0x80
221
222/*
223 * PCI BIST/Header Type/Latency Timer/Cache Line Size Register.
224 */
225#define PCI_BHLC_REG                    0x0c
226
227#define PCI_BIST_SHIFT                          24
228#define PCI_BIST_MASK                           0xff
229#define PCI_BIST(bhlcr) \
230            (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK)
231
232#define PCI_HDRTYPE_SHIFT                       16
233#define PCI_HDRTYPE_MASK                        0xff
234#define PCI_HDRTYPE(bhlcr) \
235            (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK)
236
237#define PCI_HDRTYPE_TYPE(bhlcr) \
238            (PCI_HDRTYPE(bhlcr) & 0x7f)
239#define PCI_HDRTYPE_MULTIFN(bhlcr) \
240            ((PCI_HDRTYPE(bhlcr) & 0x80) != 0)
241
242#define PCI_LATTIMER_SHIFT                      8
243#define PCI_LATTIMER_MASK                       0xff
244#define PCI_LATTIMER(bhlcr) \
245            (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK)
246
247#define PCI_CACHELINE_SHIFT                     0
248#define PCI_CACHELINE_MASK                      0xff
249#define PCI_CACHELINE(bhlcr) \
250            (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK)
251
252#define PCI_BHLC_CODE(bist,type,multi,latency,cacheline)                \
253            ((((bist) & PCI_BIST_MASK) << PCI_BIST_SHIFT) |             \
254             (((type) & PCI_HDRTYPE_MASK) << PCI_HDRTYPE_SHIFT) |       \
255             (((multi)?0x80:0) << PCI_HDRTYPE_SHIFT) |                  \
256             (((latency) & PCI_LATTIMER_MASK) << PCI_LATTIMER_SHIFT) |  \
257             (((cacheline) & PCI_CACHELINE_MASK) << PCI_CACHELINE_SHIFT))
258
259/*
260 * PCI header type
261 */
262#define PCI_HDRTYPE_DEVICE      0
263#define PCI_HDRTYPE_PPB         1
264#define PCI_HDRTYPE_PCB         2
265
266/*
267 * Mapping registers
268 */
269#define PCI_MAPREG_START                0x10
270#define PCI_MAPREG_END                  0x28
271#define PCI_MAPREG_ROM                  0x30
272#define PCI_MAPREG_PPB_END              0x18
273#define PCI_MAPREG_PCB_END              0x14
274
275#define PCI_MAPREG_TYPE(mr)                                             \
276            ((mr) & PCI_MAPREG_TYPE_MASK)
277#define PCI_MAPREG_TYPE_MASK                    0x00000001
278
279#define PCI_MAPREG_TYPE_MEM                     0x00000000
280#define PCI_MAPREG_TYPE_IO                      0x00000001
281#define PCI_MAPREG_ROM_ENABLE                   0x00000001
282
283#define PCI_MAPREG_MEM_TYPE(mr)                                         \
284            ((mr) & PCI_MAPREG_MEM_TYPE_MASK)
285#define PCI_MAPREG_MEM_TYPE_MASK                0x00000006
286
287#define PCI_MAPREG_MEM_TYPE_32BIT               0x00000000
288#define PCI_MAPREG_MEM_TYPE_32BIT_1M            0x00000002
289#define PCI_MAPREG_MEM_TYPE_64BIT               0x00000004
290
291#define PCI_MAPREG_MEM_PREFETCHABLE(mr)                         \
292            (((mr) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0)
293#define PCI_MAPREG_MEM_PREFETCHABLE_MASK        0x00000008
294
295#define PCI_MAPREG_MEM_ADDR(mr)                                         \
296            ((mr) & PCI_MAPREG_MEM_ADDR_MASK)
297#define PCI_MAPREG_MEM_SIZE(mr)                                         \
298            (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr))
299#define PCI_MAPREG_MEM_ADDR_MASK                0xfffffff0
300
301#define PCI_MAPREG_MEM64_ADDR(mr)                                       \
302            ((mr) & PCI_MAPREG_MEM64_ADDR_MASK)
303#define PCI_MAPREG_MEM64_SIZE(mr)                                       \
304            (PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr))
305#define PCI_MAPREG_MEM64_ADDR_MASK              0xfffffffffffffff0ULL
306
307#define PCI_MAPREG_IO_ADDR(mr)                                          \
308            ((mr) & PCI_MAPREG_IO_ADDR_MASK)
309#define PCI_MAPREG_IO_SIZE(mr)                                          \
310            (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr))
311#define PCI_MAPREG_IO_ADDR_MASK                 0xfffffffc
312
313#define PCI_MAPREG_SIZE_TO_MASK(size)                                   \
314            (-(size))
315
316#define PCI_MAPREG_NUM(offset)                                          \
317            (((unsigned)(offset)-PCI_MAPREG_START)/4)
318
319
320/*
321 * Cardbus CIS pointer (PCI rev. 2.1)
322 */
323#define PCI_CARDBUS_CIS_REG 0x28
324
325/*
326 * Subsystem identification register; contains a vendor ID and a device ID.
327 * Types/macros for PCI_ID_REG apply.
328 * (PCI rev. 2.1)
329 */
330#define PCI_SUBSYS_ID_REG 0x2c
331
332/*
333 * capabilities link list (PCI rev. 2.2)
334 */
335#define PCI_CAPLISTPTR_REG              0x34    /* header type 0 */
336#define PCI_CARDBUS_CAPLISTPTR_REG      0x14    /* header type 2 */
337#define PCI_CAPLIST_PTR(cpr)    ((cpr) & 0xff)
338#define PCI_CAPLIST_NEXT(cr)    (((cr) >> 8) & 0xff)
339#define PCI_CAPLIST_CAP(cr)     ((cr) & 0xff)
340
341#define PCI_CAP_RESERVED0       0x00
342#define PCI_CAP_PWRMGMT         0x01
343#define PCI_CAP_AGP             0x02
344#define PCI_CAP_VPD             0x03
345#define PCI_CAP_SLOTID          0x04
346#define PCI_CAP_MSI             0x05
347#define PCI_CAP_CPCI_HOTSWAP    0x06
348#define PCI_CAP_PCIX            0x07
349#define PCI_CAP_LDT             0x08
350#define PCI_CAP_VENDSPEC        0x09
351#define PCI_CAP_DEBUGPORT       0x0a
352#define PCI_CAP_CPCI_RSRCCTL    0x0b
353#define PCI_CAP_HOTPLUG         0x0c
354#define PCI_CAP_AGP8            0x0e
355#define PCI_CAP_SECURE          0x0f
356#define PCI_CAP_PCIEXPRESS      0x10
357#define PCI_CAP_MSIX            0x11
358
359/*
360 * Vital Product Data; access via capability pointer (PCI rev 2.2).
361 */
362#define PCI_VPD_ADDRESS_MASK    0x7fff
363#define PCI_VPD_ADDRESS_SHIFT   16
364#define PCI_VPD_ADDRESS(ofs)    \
365        (((ofs) & PCI_VPD_ADDRESS_MASK) << PCI_VPD_ADDRESS_SHIFT)
366#define PCI_VPD_DATAREG(ofs)    ((ofs) + 4)
367#define PCI_VPD_OPFLAG          0x80000000
368
369/*
370 * Power Management Capability; access via capability pointer.
371 */
372
373/* Power Management Capability Register */
374#define PCI_PMCR                0x02
375#define PCI_PMCR_D1SUPP         0x0200
376#define PCI_PMCR_D2SUPP         0x0400
377/* Power Management Control Status Register */
378#define PCI_PMCSR               0x04
379#define PCI_PMCSR_STATE_MASK    0x03
380#define PCI_PMCSR_STATE_D0      0x00
381#define PCI_PMCSR_STATE_D1      0x01
382#define PCI_PMCSR_STATE_D2      0x02
383#define PCI_PMCSR_STATE_D3      0x03
384
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