1 | /* $NetBSD: pcireg.h,v 1.44 2003/12/02 16:31:06 briggs Exp $ */ |
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2 | |
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3 | /* |
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4 | * Copyright (c) 1995, 1996, 1999, 2000 |
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5 | * Christopher G. Demetriou. All rights reserved. |
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6 | * Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved. |
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7 | * Copyright (C) 2007 Brookhaven National Laboratory, Shuchen Kate Feng |
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8 | * |
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9 | * Redistribution and use in source and binary forms, with or without |
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10 | * modification, are permitted provided that the following conditions |
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11 | * are met: |
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12 | * 1. Redistributions of source code must retain the above copyright |
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13 | * notice, this list of conditions and the following disclaimer. |
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14 | * 2. Redistributions in binary form must reproduce the above copyright |
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15 | * notice, this list of conditions and the following disclaimer in the |
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16 | * documentation and/or other materials provided with the distribution. |
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17 | * 3. All advertising materials mentioning features or use of this software |
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18 | * must display the following acknowledgement: |
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19 | * This product includes software developed by Charles M. Hannum. |
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20 | * 4. The name of the author may not be used to endorse or promote products |
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21 | * derived from this software without specific prior written permission. |
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22 | * |
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23 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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24 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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25 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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26 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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27 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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28 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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29 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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30 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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31 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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32 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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33 | */ |
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34 | #include <bsp.h> |
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35 | |
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36 | /* |
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37 | * PCI Class and Revision Register; defines type and revision of device. |
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38 | */ |
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39 | #define PCI_CLASS_REG 0x08 |
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40 | |
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41 | #define PCI_CLASS_SHIFT 24 |
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42 | #define PCI_CLASS_MASK 0xff |
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43 | #define PCI_CLASS(cr) \ |
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44 | (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK) |
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45 | |
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46 | #define PCI_SUBCLASS_SHIFT 16 |
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47 | #define PCI_SUBCLASS_MASK 0xff |
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48 | #define PCI_SUBCLASS(cr) \ |
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49 | (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK) |
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50 | |
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51 | #define PCI_INTERFACE_SHIFT 8 |
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52 | #define PCI_INTERFACE_MASK 0xff |
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53 | #define PCI_INTERFACE(cr) \ |
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54 | (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK) |
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55 | |
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56 | #define PCI_REVISION_SHIFT 0 |
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57 | #define PCI_REVISION_MASK 0xff |
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58 | #define PCI_REVISION(cr) \ |
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59 | (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK) |
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60 | |
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61 | #define PCI_CLASS_CODE(mainclass, subclass, interface) \ |
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62 | ((((mainclass) & PCI_CLASS_MASK) << PCI_CLASS_SHIFT) | \ |
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63 | (((subclass) & PCI_SUBCLASS_MASK) << PCI_SUBCLASS_SHIFT) | \ |
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64 | (((interface) & PCI_INTERFACE_MASK) << PCI_INTERFACE_SHIFT)) |
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65 | |
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66 | /* base classes */ |
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67 | #define PCI_CLASS_PREHISTORIC 0x00 |
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68 | #define PCI_CLASS_MASS_STORAGE 0x01 |
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69 | #define PCI_CLASS_NETWORK 0x02 |
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70 | #define PCI_CLASS_DISPLAY 0x03 |
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71 | #define PCI_CLASS_MULTIMEDIA 0x04 |
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72 | #define PCI_CLASS_MEMORY 0x05 |
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73 | #define PCI_CLASS_BRIDGE 0x06 |
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74 | #define PCI_CLASS_COMMUNICATIONS 0x07 |
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75 | #define PCI_CLASS_SYSTEM 0x08 |
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76 | #define PCI_CLASS_INPUT 0x09 |
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77 | #define PCI_CLASS_DOCK 0x0a |
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78 | #define PCI_CLASS_PROCESSOR 0x0b |
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79 | #define PCI_CLASS_SERIALBUS 0x0c |
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80 | #define PCI_CLASS_WIRELESS 0x0d |
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81 | #define PCI_CLASS_I2O 0x0e |
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82 | #define PCI_CLASS_SATCOM 0x0f |
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83 | #define PCI_CLASS_CRYPTO 0x10 |
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84 | #define PCI_CLASS_DASP 0x11 |
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85 | #define PCI_CLASS_UNDEFINED 0xff |
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86 | |
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87 | /* 0x00 prehistoric subclasses */ |
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88 | #define PCI_SUBCLASS_PREHISTORIC_MISC 0x00 |
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89 | #define PCI_SUBCLASS_PREHISTORIC_VGA 0x01 |
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90 | |
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91 | /* 0x01 mass storage subclasses */ |
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92 | #define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00 |
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93 | #define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01 |
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94 | #define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02 |
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95 | #define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03 |
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96 | #define PCI_SUBCLASS_MASS_STORAGE_RAID 0x04 |
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97 | #define PCI_SUBCLASS_MASS_STORAGE_ATA 0x05 |
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98 | #define PCI_SUBCLASS_MASS_STORAGE_SATA 0x06 |
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99 | #define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80 |
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100 | |
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101 | /* 0x02 network subclasses */ |
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102 | #define PCI_SUBCLASS_NETWORK_ETHERNET 0x00 |
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103 | #define PCI_SUBCLASS_NETWORK_TOKENRING 0x01 |
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104 | #define PCI_SUBCLASS_NETWORK_FDDI 0x02 |
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105 | #define PCI_SUBCLASS_NETWORK_ATM 0x03 |
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106 | #define PCI_SUBCLASS_NETWORK_ISDN 0x04 |
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107 | #define PCI_SUBCLASS_NETWORK_WORLDFIP 0x05 |
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108 | #define PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP 0x06 |
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109 | #define PCI_SUBCLASS_NETWORK_MISC 0x80 |
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110 | |
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111 | /* 0x03 display subclasses */ |
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112 | #define PCI_SUBCLASS_DISPLAY_VGA 0x00 |
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113 | #define PCI_SUBCLASS_DISPLAY_XGA 0x01 |
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114 | #define PCI_SUBCLASS_DISPLAY_3D 0x02 |
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115 | #define PCI_SUBCLASS_DISPLAY_MISC 0x80 |
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116 | |
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117 | /* 0x04 multimedia subclasses */ |
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118 | #define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00 |
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119 | #define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01 |
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120 | #define PCI_SUBCLASS_MULTIMEDIA_TELEPHONY 0x02 |
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121 | #define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80 |
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122 | |
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123 | /* 0x05 memory subclasses */ |
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124 | #define PCI_SUBCLASS_MEMORY_RAM 0x00 |
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125 | #define PCI_SUBCLASS_MEMORY_FLASH 0x01 |
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126 | #define PCI_SUBCLASS_MEMORY_MISC 0x80 |
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127 | |
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128 | /* 0x06 bridge subclasses */ |
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129 | #define PCI_SUBCLASS_BRIDGE_HOST 0x00 |
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130 | #define PCI_SUBCLASS_BRIDGE_ISA 0x01 |
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131 | #define PCI_SUBCLASS_BRIDGE_EISA 0x02 |
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132 | #define PCI_SUBCLASS_BRIDGE_MC 0x03 /* XXX _MCA? */ |
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133 | #define PCI_SUBCLASS_BRIDGE_PCI 0x04 |
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134 | #define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05 |
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135 | #define PCI_SUBCLASS_BRIDGE_NUBUS 0x06 |
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136 | #define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07 |
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137 | #define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08 |
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138 | #define PCI_SUBCLASS_BRIDGE_STPCI 0x09 |
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139 | #define PCI_SUBCLASS_BRIDGE_INFINIBAND 0x0a |
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140 | #define PCI_SUBCLASS_BRIDGE_MISC 0x80 |
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141 | |
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142 | /* 0x07 communications subclasses */ |
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143 | #define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00 |
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144 | #define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01 |
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145 | #define PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL 0x02 |
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146 | #define PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03 |
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147 | #define PCI_SUBCLASS_COMMUNICATIONS_GPIB 0x04 |
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148 | #define PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD 0x05 |
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149 | #define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80 |
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150 | |
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151 | /* 0x08 system subclasses */ |
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152 | #define PCI_SUBCLASS_SYSTEM_PIC 0x00 |
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153 | #define PCI_SUBCLASS_SYSTEM_DMA 0x01 |
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154 | #define PCI_SUBCLASS_SYSTEM_TIMER 0x02 |
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155 | #define PCI_SUBCLASS_SYSTEM_RTC 0x03 |
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156 | #define PCI_SUBCLASS_SYSTEM_PCIHOTPLUG 0x04 |
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157 | #define PCI_SUBCLASS_SYSTEM_MISC 0x80 |
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158 | |
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159 | /* 0x09 input subclasses */ |
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160 | #define PCI_SUBCLASS_INPUT_KEYBOARD 0x00 |
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161 | #define PCI_SUBCLASS_INPUT_DIGITIZER 0x01 |
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162 | #define PCI_SUBCLASS_INPUT_MOUSE 0x02 |
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163 | #define PCI_SUBCLASS_INPUT_SCANNER 0x03 |
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164 | #define PCI_SUBCLASS_INPUT_GAMEPORT 0x04 |
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165 | #define PCI_SUBCLASS_INPUT_MISC 0x80 |
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166 | |
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167 | /* 0x0a dock subclasses */ |
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168 | #define PCI_SUBCLASS_DOCK_GENERIC 0x00 |
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169 | #define PCI_SUBCLASS_DOCK_MISC 0x80 |
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170 | |
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171 | /* 0x0b processor subclasses */ |
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172 | #define PCI_SUBCLASS_PROCESSOR_386 0x00 |
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173 | #define PCI_SUBCLASS_PROCESSOR_486 0x01 |
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174 | #define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02 |
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175 | #define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10 |
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176 | #define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20 |
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177 | #define PCI_SUBCLASS_PROCESSOR_MIPS 0x30 |
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178 | #define PCI_SUBCLASS_PROCESSOR_COPROC 0x40 |
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179 | |
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180 | /* 0x0c serial bus subclasses */ |
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181 | #define PCI_SUBCLASS_SERIALBUS_FIREWIRE 0x00 |
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182 | #define PCI_SUBCLASS_SERIALBUS_ACCESS 0x01 |
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183 | #define PCI_SUBCLASS_SERIALBUS_SSA 0x02 |
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184 | #define PCI_SUBCLASS_SERIALBUS_USB 0x03 |
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185 | #define PCI_SUBCLASS_SERIALBUS_FIBER 0x04 /* XXX _FIBRECHANNEL */ |
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186 | #define PCI_SUBCLASS_SERIALBUS_SMBUS 0x05 |
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187 | #define PCI_SUBCLASS_SERIALBUS_INFINIBAND 0x06 |
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188 | #define PCI_SUBCLASS_SERIALBUS_IPMI 0x07 |
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189 | #define PCI_SUBCLASS_SERIALBUS_SERCOS 0x08 |
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190 | #define PCI_SUBCLASS_SERIALBUS_CANBUS 0x09 |
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191 | |
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192 | /* 0x0d wireless subclasses */ |
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193 | #define PCI_SUBCLASS_WIRELESS_IRDA 0x00 |
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194 | #define PCI_SUBCLASS_WIRELESS_CONSUMERIR 0x01 |
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195 | #define PCI_SUBCLASS_WIRELESS_RF 0x10 |
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196 | #define PCI_SUBCLASS_WIRELESS_BLUETOOTH 0x11 |
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197 | #define PCI_SUBCLASS_WIRELESS_BROADBAND 0x12 |
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198 | #define PCI_SUBCLASS_WIRELESS_802_11A 0x20 |
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199 | #define PCI_SUBCLASS_WIRELESS_802_11B 0x21 |
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200 | #define PCI_SUBCLASS_WIRELESS_MISC 0x80 |
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201 | |
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202 | /* 0x0e I2O (Intelligent I/O) subclasses */ |
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203 | #define PCI_SUBCLASS_I2O_STANDARD 0x00 |
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204 | |
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205 | /* 0x0f satellite communication subclasses */ |
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206 | /* PCI_SUBCLASS_SATCOM_??? 0x00 / * XXX ??? */ |
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207 | #define PCI_SUBCLASS_SATCOM_TV 0x01 |
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208 | #define PCI_SUBCLASS_SATCOM_AUDIO 0x02 |
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209 | #define PCI_SUBCLASS_SATCOM_VOICE 0x03 |
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210 | #define PCI_SUBCLASS_SATCOM_DATA 0x04 |
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211 | |
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212 | /* 0x10 encryption/decryption subclasses */ |
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213 | #define PCI_SUBCLASS_CRYPTO_NETCOMP 0x00 |
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214 | #define PCI_SUBCLASS_CRYPTO_ENTERTAINMENT 0x10 |
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215 | #define PCI_SUBCLASS_CRYPTO_MISC 0x80 |
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216 | |
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217 | /* 0x11 data acquisition and signal processing subclasses */ |
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218 | #define PCI_SUBCLASS_DASP_DPIO 0x00 |
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219 | #define PCI_SUBCLASS_DASP_TIMEFREQ 0x01 |
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220 | #define PCI_SUBCLASS_DASP_SYNC 0x10 |
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221 | #define PCI_SUBCLASS_DASP_MGMT 0x20 |
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222 | #define PCI_SUBCLASS_DASP_MISC 0x80 |
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223 | |
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224 | /* |
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225 | * PCI BIST/Header Type/Latency Timer/Cache Line Size Register. |
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226 | */ |
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227 | #define PCI_BHLC_REG 0x0c |
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228 | |
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229 | #define PCI_BIST_SHIFT 24 |
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230 | #define PCI_BIST_MASK 0xff |
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231 | #define PCI_BIST(bhlcr) \ |
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232 | (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK) |
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233 | |
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234 | #define PCI_HDRTYPE_SHIFT 16 |
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235 | #define PCI_HDRTYPE_MASK 0xff |
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236 | #define PCI_HDRTYPE(bhlcr) \ |
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237 | (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK) |
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238 | |
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239 | #define PCI_HDRTYPE_TYPE(bhlcr) \ |
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240 | (PCI_HDRTYPE(bhlcr) & 0x7f) |
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241 | #define PCI_HDRTYPE_MULTIFN(bhlcr) \ |
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242 | ((PCI_HDRTYPE(bhlcr) & 0x80) != 0) |
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243 | |
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244 | #define PCI_LATTIMER_SHIFT 8 |
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245 | #define PCI_LATTIMER_MASK 0xff |
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246 | #define PCI_LATTIMER(bhlcr) \ |
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247 | (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK) |
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248 | |
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249 | #define PCI_CACHELINE_SHIFT 0 |
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250 | #define PCI_CACHELINE_MASK 0xff |
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251 | #define PCI_CACHELINE(bhlcr) \ |
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252 | (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK) |
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253 | |
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254 | #define PCI_BHLC_CODE(bist,type,multi,latency,cacheline) \ |
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255 | ((((bist) & PCI_BIST_MASK) << PCI_BIST_SHIFT) | \ |
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256 | (((type) & PCI_HDRTYPE_MASK) << PCI_HDRTYPE_SHIFT) | \ |
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257 | (((multi)?0x80:0) << PCI_HDRTYPE_SHIFT) | \ |
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258 | (((latency) & PCI_LATTIMER_MASK) << PCI_LATTIMER_SHIFT) | \ |
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259 | (((cacheline) & PCI_CACHELINE_MASK) << PCI_CACHELINE_SHIFT)) |
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260 | |
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261 | /* |
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262 | * PCI header type |
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263 | */ |
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264 | #define PCI_HDRTYPE_DEVICE 0 |
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265 | #define PCI_HDRTYPE_PPB 1 |
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266 | #define PCI_HDRTYPE_PCB 2 |
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267 | |
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268 | /* |
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269 | * Mapping registers |
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270 | */ |
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271 | #define PCI_MAPREG_START 0x10 |
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272 | #define PCI_MAPREG_END 0x28 |
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273 | #define PCI_MAPREG_ROM 0x30 |
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274 | #define PCI_MAPREG_PPB_END 0x18 |
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275 | #define PCI_MAPREG_PCB_END 0x14 |
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276 | |
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277 | #define PCI_MAPREG_TYPE(mr) \ |
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278 | ((mr) & PCI_MAPREG_TYPE_MASK) |
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279 | #define PCI_MAPREG_TYPE_MASK 0x00000001 |
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280 | |
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281 | #define PCI_MAPREG_TYPE_MEM 0x00000000 |
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282 | #define PCI_MAPREG_TYPE_IO 0x00000001 |
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283 | #define PCI_MAPREG_ROM_ENABLE 0x00000001 |
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284 | |
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285 | #define PCI_MAPREG_MEM_TYPE(mr) \ |
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286 | ((mr) & PCI_MAPREG_MEM_TYPE_MASK) |
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287 | #define PCI_MAPREG_MEM_TYPE_MASK 0x00000006 |
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288 | |
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289 | #define PCI_MAPREG_MEM_TYPE_32BIT 0x00000000 |
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290 | #define PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002 |
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291 | #define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004 |
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292 | |
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293 | #define PCI_MAPREG_MEM_PREFETCHABLE(mr) \ |
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294 | (((mr) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0) |
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295 | #define PCI_MAPREG_MEM_PREFETCHABLE_MASK 0x00000008 |
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296 | |
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297 | #define PCI_MAPREG_MEM_ADDR(mr) \ |
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298 | ((mr) & PCI_MAPREG_MEM_ADDR_MASK) |
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299 | #define PCI_MAPREG_MEM_SIZE(mr) \ |
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300 | (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr)) |
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301 | #define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0 |
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302 | |
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303 | #define PCI_MAPREG_MEM64_ADDR(mr) \ |
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304 | ((mr) & PCI_MAPREG_MEM64_ADDR_MASK) |
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305 | #define PCI_MAPREG_MEM64_SIZE(mr) \ |
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306 | (PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr)) |
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307 | #define PCI_MAPREG_MEM64_ADDR_MASK 0xfffffffffffffff0ULL |
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308 | |
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309 | #define PCI_MAPREG_IO_ADDR(mr) \ |
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310 | ((mr+PCI0_IO_BASE) & PCI_MAPREG_IO_ADDR_MASK) |
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311 | #define PCI_MAPREG_IO_SIZE(mr) \ |
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312 | (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr)) |
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313 | #define PCI_MAPREG_IO_ADDR_MASK 0xfffffffc |
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314 | |
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315 | #define PCI_MAPREG_SIZE_TO_MASK(size) \ |
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316 | (-(size)) |
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317 | |
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318 | #define PCI_MAPREG_NUM(offset) \ |
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319 | (((unsigned)(offset)-PCI_MAPREG_START)/4) |
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320 | |
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321 | |
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322 | /* |
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323 | * Cardbus CIS pointer (PCI rev. 2.1) |
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324 | */ |
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325 | #define PCI_CARDBUS_CIS_REG 0x28 |
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326 | |
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327 | /* |
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328 | * Subsystem identification register; contains a vendor ID and a device ID. |
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329 | * Types/macros for PCI_ID_REG apply. |
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330 | * (PCI rev. 2.1) |
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331 | */ |
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332 | #define PCI_SUBSYS_ID_REG 0x2c |
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333 | |
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334 | /* |
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335 | * capabilities link list (PCI rev. 2.2) |
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336 | */ |
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337 | #define PCI_CAPLISTPTR_REG 0x34 /* header type 0 */ |
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338 | #define PCI_CARDBUS_CAPLISTPTR_REG 0x14 /* header type 2 */ |
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339 | #define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff) |
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340 | #define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff) |
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341 | #define PCI_CAPLIST_CAP(cr) ((cr) & 0xff) |
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342 | |
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343 | #define PCI_CAP_RESERVED0 0x00 |
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344 | #define PCI_CAP_PWRMGMT 0x01 |
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345 | #define PCI_CAP_AGP 0x02 |
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346 | #define PCI_CAP_VPD 0x03 |
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347 | #define PCI_CAP_SLOTID 0x04 |
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348 | #define PCI_CAP_MSI 0x05 |
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349 | #define PCI_CAP_CPCI_HOTSWAP 0x06 |
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350 | #define PCI_CAP_PCIX 0x07 |
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351 | #define PCI_CAP_LDT 0x08 |
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352 | #define PCI_CAP_VENDSPEC 0x09 |
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353 | #define PCI_CAP_DEBUGPORT 0x0a |
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354 | #define PCI_CAP_CPCI_RSRCCTL 0x0b |
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355 | #define PCI_CAP_HOTPLUG 0x0c |
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356 | #define PCI_CAP_AGP8 0x0e |
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357 | #define PCI_CAP_SECURE 0x0f |
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358 | #define PCI_CAP_PCIEXPRESS 0x10 |
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359 | #define PCI_CAP_MSIX 0x11 |
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360 | |
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361 | /* |
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362 | * Vital Product Data; access via capability pointer (PCI rev 2.2). |
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363 | */ |
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364 | #define PCI_VPD_ADDRESS_MASK 0x7fff |
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365 | #define PCI_VPD_ADDRESS_SHIFT 16 |
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366 | #define PCI_VPD_ADDRESS(ofs) \ |
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367 | (((ofs) & PCI_VPD_ADDRESS_MASK) << PCI_VPD_ADDRESS_SHIFT) |
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368 | #define PCI_VPD_DATAREG(ofs) ((ofs) + 4) |
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369 | #define PCI_VPD_OPFLAG 0x80000000 |
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370 | |
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371 | /* |
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372 | * Power Management Capability; access via capability pointer. |
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373 | */ |
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374 | |
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375 | /* Power Management Capability Register */ |
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376 | #define PCI_PMCR 0x02 |
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377 | #define PCI_PMCR_D1SUPP 0x0200 |
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378 | #define PCI_PMCR_D2SUPP 0x0400 |
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379 | /* Power Management Control Status Register */ |
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380 | #define PCI_PMCSR 0x04 |
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381 | #define PCI_PMCSR_STATE_MASK 0x03 |
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382 | #define PCI_PMCSR_STATE_D0 0x00 |
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383 | #define PCI_PMCSR_STATE_D1 0x01 |
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384 | #define PCI_PMCSR_STATE_D2 0x02 |
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385 | #define PCI_PMCSR_STATE_D3 0x03 |
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386 | |
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