source: rtems/c/src/lib/libbsp/powerpc/mvme5500/network/if_1GHz/if_wm.c @ cf599996

4.9
Last change on this file since cf599996 was cf599996, checked in by Joel Sherrill <joel.sherrill@…>, on May 8, 2009 at 6:22:51 PM

2009-05-08 Kate Feng <feng1@…>

PR1395/bsps

  • Updated the changes from RTEMS-4.8.0, which were made since Oct. 2007.
  • network/if_1GHz/if_wm.c: fixed some bugs in the 1GHz driver.
  • pci/pci_interface.c: + Enabled PCI "Read", "Read Line", and "Read Multiple" + Agressive Prefetch to improve the performance of the PCI based

applications (e.g. 1GHz NIC).

  • irq/BSP_irq.c : Replaced the irq/irq.c, and used GT_GPP_Value register to monitor the cause of the level sensitive interrupts. This unique solution solves various bugs in the 1GHz network drivers Fixed bugs in compute_pic_masks_from_prio()
  • pci/pci.c : Updated it to be consistent with the original pci.c
  • written by Eric Valette. There is no change in its function.
  • irq/irq_init.c : set defaultIrq->next_handler to be 0
  • for BSP_SHARED_HANDLER_SUPPORT.
  • Property mode set to 100644
File size: 48.7 KB
Line 
1/*
2 * Copyright (c) 2004,2005 RTEMS/Mvme5500 port by S. Kate Feng <feng1@bnl.gov>
3 *      under the Deaprtment of Energy contract DE-AC02-98CH10886
4 *      Brookhaven National Laboratory, All rights reserved
5 *
6 * Acknowledgements:
7 * netBSD : Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
8 *          Jason R. Thorpe for Wasabi Systems, Inc.
9 * Intel : NDA document
10 *
11 * Some notes from the author, S. Kate Feng :
12 *
13 * 1) The error reporting routine i82544EI_error() employs two pointers
14 *    for the error report buffer. One for the ISR and another one for
15 *    the error report.
16 * 2) Enable the hardware Auto-Negotiation state machine.
17 * 3) Set Big Endian mode in the WMREG_CTRL so that we do not need htole32
18 *    because PPC is big endian mode.
19 *    However, the data packet structure defined in if_wmreg.h
20 *    should be redefined for the big endian mode.
21 * 4) To ensure the cache coherence, the MOTLoad had the PCI
22 *    snoop control registers (0x1f00) set to "snoop to WB region" for
23 *    the entire 512MB of memory.
24 * 5) MOTLoad default :
25 *    little endian mode, cache line size is 32 bytes, no checksum control,
26 *    hardware auto-neg. state machine disabled. PCI control "snoop
27 *    to WB region", MII mode (PHY) instead of TBI mode.
28 * 6) We currently only use 32-bit (instead of 64-bit) DMA addressing.
29 * 7) Implementation for Jumbo Frame and TCP checksum is not completed yet.
30 *   
31 */
32
33#define BYTE_ORDER BIG_ENDIAN
34
35#define INET
36
37/*#define RTEMS_ETHERMTU_JUMBO*/
38
39#include <rtems.h>
40#include <rtems/bspIo.h>      /* printk */
41
42#include <stdio.h>            /* printf for statistics */
43#include <string.h>
44
45#include <libcpu/io.h>        /* inp & friends */
46#include <libcpu/spr.h>       /* registers.h is included here */
47#include <bsp.h>
48
49#include <sys/param.h>
50#include <sys/systm.h>
51#include <sys/mbuf.h>
52
53#include <rtems/rtems_bsdnet.h>
54#include <rtems/rtems_bsdnet_internal.h>
55#include <rtems/error.h>          
56#include <errno.h>
57
58#include <rtems/rtems/types.h>
59#include <rtems/score/cpu.h>
60
61#include <sys/queue.h>
62
63#include <sys/ioctl.h>
64#include <sys/socket.h>
65#include <sys/sockio.h>             /* SIOCADDMULTI, SIOC...     */
66#include <net/if.h>
67#include <net/if_dl.h>
68#include <netinet/in.h>
69#include <netinet/if_ether.h>
70#include <net/ethernet.h>
71
72#ifdef INET
73#include <netinet/in_var.h>
74#endif
75
76#include <bsp/irq.h>
77#include <bsp/pci.h>
78#include <bsp/pcireg.h>
79#include <bsp/if_wmreg.h>
80#define WMREG_RADV      0x282c  /* Receive Interrupt Absolute Delay Timer */
81
82#define ETHERTYPE_FLOWCONTROL   0x8808  /* 802.3x flow control packet */
83
84#define i82544EI_TASK_NAME "IGHz"
85#define SOFTC_ALIGN        4095
86
87#define IF_ERR_BUFSZE        16
88
89/*#define WM_DEBUG*/
90#ifdef WM_DEBUG
91#define WM_DEBUG_LINK           0x01
92#define WM_DEBUG_TX             0x02
93#define WM_DEBUG_RX             0x04
94#define WM_DEBUG_GMII           0x08
95static int      wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK; /* May 7, 2009 */
96
97#define DPRINTF(x, y)   if (wm_debug & (x)) printk y
98#else
99#define DPRINTF(x, y)   /* nothing */
100#endif /* WM_DEBUG */
101
102/* RTEMS event to kill the daemon */
103#define KILL_EVENT              RTEMS_EVENT_1
104/* RTEMS event to (re)start the transmitter */
105#define START_TRANSMIT_EVENT    RTEMS_EVENT_2
106/* RTEMS events used by the ISR */
107#define RX_EVENT                RTEMS_EVENT_3
108#define TX_EVENT                RTEMS_EVENT_4
109#define ERR_EVENT               RTEMS_EVENT_5
110#define INIT_EVENT              RTEMS_EVENT_6
111 
112#define ALL_EVENTS (KILL_EVENT|START_TRANSMIT_EVENT|RX_EVENT|TX_EVENT|ERR_EVENT|INIT_EVENT)
113
114/* <skf> used 64 in 4.8.0, TOD; try 4096 */
115#define NTXDESC                 256
116#define NTXDESC_MASK            (NTXDESC - 1)
117#define WM_NEXTTX(x)            (((x) + 1) & NTXDESC_MASK)
118
119#define NRXDESC                 256
120#define NRXDESC_MASK            (NRXDESC - 1)
121#define WM_NEXTRX(x)            (((x) + 1) & NRXDESC_MASK)
122#define WM_PREVRX(x)            (((x) - 1) & NRXDESC_MASK)
123
124#define WM_CDOFF(x)     offsetof(struct wm_control_data, x)
125#define WM_CDTXOFF(x)   WM_CDOFF(sc_txdescs[(x)])
126#define WM_CDRXOFF(x)   WM_CDOFF(sc_rxdescs[(x)])
127
128#define TXQ_HiLmt_OFF 32
129
130static uint32_t TxDescCmd;
131static unsigned BSP_1GHz_membase;
132
133/*
134 * Software state per device.
135 */
136struct wm_softc {
137        wiseman_txdesc_t sc_txdescs[NTXDESC]; /* transmit descriptor memory */
138        wiseman_rxdesc_t sc_rxdescs[NRXDESC]; /* receive descriptor memory */
139        struct mbuf *txs_mbuf[NTXDESC];        /* transmit buffer memory */
140        struct mbuf *rxs_mbuf[NRXDESC];        /* receive buffer memory */
141        struct wm_softc *next_module;
142        volatile unsigned int if_errsts[IF_ERR_BUFSZE]; /* intr_status */
143        unsigned int if_err_ptr1;     /* ptr used in i82544EI_error() */
144        unsigned int if_err_ptr2;     /* ptr used in ISR */
145        int txs_firstdesc;              /* first descriptor in packet */
146        int txs_lastdesc;               /* last descriptor in packet */
147        int txs_ndesc;                  /* # of descriptors used */
148        unsigned sc_membase;            /* Memory space base address */
149        unsigned sc_memsize;            /* Memory space size */
150
151        char    dv_xname[16];           /* external name (name + unit) */
152        void *sc_sdhook;                /* shutdown hook */
153        struct arpcom arpcom;           /* rtems if structure, contains ifnet */
154        int sc_flags;                   /* flags; see below */
155        int sc_bus_speed;               /* PCI/PCIX bus speed */
156        int sc_flowflags;               /* 802.3x flow control flags */
157
158        void *sc_ih;                    /* interrupt cookie */
159
160        int sc_ee_addrbits;             /* EEPROM address bits */
161        rtems_id        daemonTid;
162        rtems_id        daemonSync;     /* synchronization with the daemon */
163
164        int      txq_next;              /* next Tx descriptor ready for transmitting */
165        uint32_t txq_nactive;           /* number of active TX descriptors */
166        uint32_t txq_fi;                /* next free Tx descriptor */
167        uint32_t txq_free;              /* number of free Tx jobs */
168        uint32_t sc_txctx_ipcs;         /* cached Tx IP cksum ctx */
169        uint32_t sc_txctx_tucs;         /* cached Tx TCP/UDP cksum ctx */
170
171        int     sc_rxptr;               /* next ready Rx descriptor/queue ent */
172        int     sc_rxdiscard;
173        int     sc_rxlen;
174
175        uint32_t sc_ctrl;               /* prototype CTRL register */
176        uint32_t sc_ctrl_ext;           /* prototype CTRL_EXT register */
177
178        uint32_t sc_icr;                /* prototype interrupt bits */
179        uint32_t sc_tctl;               /* prototype TCTL register */
180        uint32_t sc_rctl;               /* prototype RCTL register */
181        uint32_t sc_tipg;               /* prototype TIPG register */
182        uint32_t sc_fcrtl;              /* prototype FCRTL register */
183        uint32_t sc_pba;                /* prototype PBA register */
184
185        int sc_mchash_type;             /* multicast filter offset */
186
187        /* statistics */
188        struct {
189          volatile unsigned long     rxInterrupts;
190          volatile unsigned long     txInterrupts;
191          unsigned long     linkInterrupts;
192          unsigned long     length_errors;
193          unsigned long     frame_errors;
194          unsigned long     crc_errors;
195          unsigned long     rxOvrRunInterrupts; /* Rx overrun interrupt */
196          unsigned long     rxSeqErr;
197          unsigned long     rxC_ordered;
198          unsigned long     ghostInterrupts;
199          unsigned long     linkStatusChng;
200        } stats;
201};
202
203/* <skf> our memory address seen from the PCI bus should be 1:1 */
204#define htole32(x)  le32toh(x)
205#define le32toh(x)  CPU_swap_u32((unsigned int) x)
206#define le16toh(x)  CPU_swap_u16(x)
207
208/* sc_flags */
209#define WM_F_HAS_MII            0x01    /* has MII */
210/* 82544 EI does not perform EEPROM handshake, EEPROM interface is not SPI */
211#define WM_F_EEPROM_HANDSHAKE   0x02    /* requires EEPROM handshake */
212#define WM_F_EEPROM_SPI         0x04    /* EEPROM is SPI */
213#define WM_F_IOH_VALID          0x10    /* I/O handle is valid */
214#define WM_F_BUS64              0x20    /* bus is 64-bit */
215#define WM_F_PCIX               0x40    /* bus is PCI-X */
216
217#define CSR_READ(sc,reg) in_le32((volatile unsigned *)(sc->sc_membase+reg))
218#define CSR_WRITE(sc,reg,val) out_le32((volatile unsigned *)(sc->sc_membase+reg), val)
219
220#define WM_CDTXADDR(sc) ( (uint32_t) &sc->sc_txdescs[0] )
221#define WM_CDRXADDR(sc) ( (uint32_t) &sc->sc_rxdescs[0] )
222
223static struct wm_softc *root_i82544EI_dev = NULL;
224
225static void i82544EI_ifstart(struct ifnet *ifp);
226static int  wm_ioctl(struct ifnet *ifp, ioctl_command_t cmd,caddr_t data);
227static void i82544EI_ifinit(void *arg);
228static void wm_stop(struct ifnet *ifp, int disable);
229static void wm_gmii_mediainit(struct wm_softc *sc);
230
231static void wm_rxdrain(struct wm_softc *sc);
232static int  wm_add_rxbuf(struct wm_softc *sc, int idx);
233static int  wm_read_eeprom(struct wm_softc *sc,int word,int wordcnt, uint16_t *data);
234static void i82544EI_daemon(void *arg);
235static void wm_set_filter(struct wm_softc *sc);
236static void i82544EI_rx(struct wm_softc *sc);
237static void i82544EI_isr(rtems_irq_hdl_param handle);
238static void i82544EI_sendpacket(struct wm_softc *sc, struct mbuf *m);
239extern int  pci_mem_find(), pci_io_find(), pci_get_capability();
240
241static void i82544EI_irq_on(const rtems_irq_connect_data *irq)
242{
243  struct wm_softc *sc;
244  unsigned int irqMask=  ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | ICR_RXO | ICR_RXT0 | ICR_RXCFG;
245 
246  for (sc= root_i82544EI_dev; sc; sc= sc-> next_module) {
247    CSR_WRITE(sc,WMREG_IMS,(CSR_READ(sc,WMREG_IMS)| irqMask) );
248    return;
249  }
250}
251
252static void i82544EI_irq_off(const rtems_irq_connect_data *irq)
253{
254  struct wm_softc *sc;
255  unsigned int irqMask=  ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | ICR_RXO | ICR_RXT0 |ICR_RXCFG ;
256
257  for (sc= root_i82544EI_dev; sc; sc= sc-> next_module) {
258    CSR_WRITE(sc,WMREG_IMS, (CSR_READ(sc,WMREG_IMS) & ~irqMask) );
259    return;
260  }
261}
262
263static int i82544EI_irq_is_on(const rtems_irq_connect_data *irq)
264{
265  return(CSR_READ(root_i82544EI_dev,WMREG_ICR) & root_i82544EI_dev->sc_icr);
266}
267
268static rtems_irq_connect_data i82544IrqData={
269        BSP_GPP_82544_IRQ,
270        (rtems_irq_hdl) i82544EI_isr,
271        (rtems_irq_hdl_param) NULL,
272        (rtems_irq_enable) i82544EI_irq_on,
273        (rtems_irq_disable) i82544EI_irq_off,
274        (rtems_irq_is_enabled) i82544EI_irq_is_on, 
275};
276
277int rtems_i82544EI_driver_attach(struct rtems_bsdnet_ifconfig *config, int attach)
278{
279  struct wm_softc *sc;
280  struct ifnet *ifp;
281  uint8_t enaddr[ETHER_ADDR_LEN];
282  uint16_t myea[ETHER_ADDR_LEN / 2], cfg1, cfg2, swdpin;
283  unsigned reg;
284  int b,d,f; /* PCI bus/device/function */
285  int unit;
286  void     *softc_mem;
287  char     *name;
288
289  unit = rtems_bsdnet_parse_driver_name(config, &name);
290  if (unit < 0) return 0;
291
292  if ( !strncmp((const char *)name,"autoz",5))
293     memcpy(name,"gtGHz",5);
294         
295  printk("\nAttaching MVME5500 1GHz NIC%d\n", unit); 
296  printk("RTEMS-mvme5500 BSP Copyright (c) 2004,2005,2008, Brookhaven National Lab., Shuchen Kate Feng \n");
297
298  /* Make sure certain elements e.g. descriptor lists are aligned.*/ 
299  softc_mem = rtems_bsdnet_malloc(sizeof(*sc) + SOFTC_ALIGN, M_FREE, M_NOWAIT);
300
301  /* Check for the very unlikely case of no memory. */
302  if (softc_mem == NULL)
303     rtems_panic("i82544EI: OUT OF MEMORY");
304
305  sc = (void *)(((long)softc_mem + SOFTC_ALIGN) & ~SOFTC_ALIGN);
306  memset(sc, 0, sizeof(*sc));
307
308  sprintf(sc->dv_xname, "%s%d", name, unit);
309
310  if (pci_find_device(PCI_VENDOR_ID_INTEL,PCI_DEVICE_INTEL_82544EI_COPPER,
311                        unit-1,&b, &d, &f))
312    rtems_panic("i82544EI device ID not found\n");
313
314#ifdef WM_DEBUG
315  printk("82544EI:b%d, d%d, f%d\n", b, d,f);
316#endif
317
318  /* Memory-mapped acccess is required for normal operation.*/
319  if ( pci_mem_find(b,d,f,PCI_MAPREG_START, &sc->sc_membase, &sc->sc_memsize))
320     rtems_panic("i82544EI: unable to map memory space\n");
321
322#ifdef WM_DEBUG
323  printk("Memory base addr 0x%x\n", sc->sc_membase);
324#endif
325  BSP_1GHz_membase= sc->sc_membase;
326
327#ifdef WM_DEBUG
328  printk("Memory base addr 0x%x\n", sc->sc_membase);
329  printk("txdesc[0] addr:0x%x, rxdesc[0] addr:0x%x, sizeof sc %d\n",&sc->sc_txdescs[0], &sc->sc_rxdescs[0], sizeof(*sc));     
330#endif
331
332
333  sc->sc_ctrl=CSR_READ(sc,WMREG_CTRL); 
334  /*
335   * Determine a few things about the bus we're connected to.
336   */
337  reg = CSR_READ(sc,WMREG_STATUS); 
338  if (reg & STATUS_BUS64) sc->sc_flags |= WM_F_BUS64;
339  sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33;
340#ifdef WM_DEBUG
341  printk("%s%d: %d-bit %dMHz PCI bus\n",name, unit,
342         (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed);
343#endif
344
345  /*
346   * Setup some information about the EEPROM.
347   */
348
349  sc->sc_ee_addrbits = 6;
350
351#ifdef WM_DEBUG
352  printk("%s%d: %u word (%d address bits) MicroWire EEPROM\n",
353            name, unit, 1U << sc->sc_ee_addrbits,
354            sc->sc_ee_addrbits);
355#endif
356
357  /*
358   * Read the Ethernet address from the EEPROM.
359   */
360  if (wm_read_eeprom(sc, EEPROM_OFF_MACADDR,
361            sizeof(myea) / sizeof(myea[0]), myea)) 
362     rtems_panic("i82544ei 1GHZ ethernet: unable to read Ethernet address");
363
364  enaddr[0] = myea[0] & 0xff;
365  enaddr[1] = myea[0] >> 8;
366  enaddr[2] = myea[1] & 0xff;
367  enaddr[3] = myea[1] >> 8;
368  enaddr[4] = myea[2] & 0xff;
369  enaddr[5] = myea[2] >> 8;
370
371  memcpy(sc->arpcom.ac_enaddr, enaddr, ETHER_ADDR_LEN);
372#ifdef WM_DEBUG
373  printk("%s: Ethernet address %s\n", sc->dv_xname,
374            ether_sprintf(enaddr));
375#endif
376
377  /*
378   * Read the config info from the EEPROM, and set up various
379   * bits in the control registers based on their contents.
380   */
381  if (wm_read_eeprom(sc, EEPROM_OFF_CFG1, 1, &cfg1)) {
382     printk("%s: unable to read CFG1 from EEPROM\n",sc->dv_xname);
383     return(0);
384  }
385  if (wm_read_eeprom(sc, EEPROM_OFF_CFG2, 1, &cfg2)) {
386     printk("%s: unable to read CFG2 from EEPROM\n",sc->dv_xname);
387     return(0);
388  }
389  if (wm_read_eeprom(sc, EEPROM_OFF_SWDPIN, 1, &swdpin)) {
390     printk("%s: unable to read SWDPIN from EEPROM\n",sc->dv_xname);
391     return(0);
392  }
393
394  if (cfg1 & EEPROM_CFG1_ILOS) sc->sc_ctrl |= CTRL_ILOS;
395  sc->sc_ctrl|=((swdpin >> EEPROM_SWDPIN_SWDPIO_SHIFT) & 0xf) <<
396                CTRL_SWDPIO_SHIFT;
397  sc->sc_ctrl |= ((swdpin >> EEPROM_SWDPIN_SWDPIN_SHIFT) & 0xf) <<
398                CTRL_SWDPINS_SHIFT;
399
400  CSR_WRITE(sc,WMREG_CTRL, sc->sc_ctrl);
401#if 0
402  CSR_WRITE(sc,WMREG_CTRL_EXT, sc->sc_ctrl_ext);
403#endif
404
405  /*
406   * Determine if we're TBI or GMII mode, and initialize the
407   * media structures accordingly.
408   */
409  if ((CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) {
410    /* 1000BASE-X : fiber  (TBI mode)
411       wm_tbi_mediainit(sc); */
412  } else {   /* 1000BASE-T : copper (internal PHY mode), for the mvme5500 */
413           wm_gmii_mediainit(sc);
414  } 
415
416  ifp = &sc->arpcom.ac_if;
417  /* set this interface's name and unit */
418  ifp->if_unit = unit;
419  ifp->if_name = name;
420  ifp->if_softc = sc;
421  ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
422#ifdef RTEMS_ETHERMTU_JUMBO
423  sc->arpcom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
424  ifp->if_mtu = config->mtu ? config->mtu : ETHERMTU_JUMBO;
425#else
426  ifp->if_mtu = config->mtu ? config->mtu : ETHERMTU;
427#endif
428#ifdef RTEMS_CKSUM_OFFLOAD
429  /* < skf> The following is really not related to jumbo frame
430  sc->arpcom.ec_capabilities |= ETHERCAP_VLAN_MTU;*/
431  ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
432                    IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
433                    IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx |
434                    IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx |
435                    IFCAP_TSOv4;  /* TCP segmentation offload. */
436#endif
437
438  ifp->if_ioctl = wm_ioctl;
439  ifp->if_start = i82544EI_ifstart;
440  /*  ifp->if_watchdog = wm_watchdog;*/
441  ifp->if_init = i82544EI_ifinit;
442  if (ifp->if_snd.ifq_maxlen == 0)
443      ifp->if_snd.ifq_maxlen = ifqmaxlen;
444
445  ifp->if_output = ether_output;
446
447  /* create the synchronization semaphore */
448  if (RTEMS_SUCCESSFUL != rtems_semaphore_create(
449     rtems_build_name('I','G','H','Z'),0,0,0,&sc->daemonSync))
450     rtems_panic("i82544EI: semaphore creation failed");
451
452  i82544IrqData.handle= (rtems_irq_hdl_param) sc;
453  /* sc->next_module = root_i82544EI_dev;*/
454  root_i82544EI_dev = sc;
455
456  /* Attach the interface. */
457  if_attach(ifp);
458  ether_ifattach(ifp);
459#ifdef WM_DEBUG
460  printk("82544EI: Ethernet driver has been attached (handle 0x%08x,ifp 0x%08x)\n",sc, ifp);
461#endif
462
463  return(1);
464}
465
466/*
467 * wm_reset:
468 *
469 *      Reset the i82544 chip.
470 */
471static void wm_reset(struct wm_softc *sc)
472{
473  int i;
474
475 /* Packet Buffer Allocation (PBA)
476  * Writing PBA sets the receive portion of the buffer.
477  * the remainder is used for the transmit buffer.
478  *
479  * 82544 has a Packet Buffer of 64K.
480  * Default allocation : PBA=40K for Rx, leaving 24K for Tx.
481  * Default for jumbo: PBA=48K for Rx, leaving 16K for Tx.
482  */ 
483  sc->sc_pba = sc->arpcom.ac_if.if_mtu > 8192 ? PBA_40K : PBA_48K;
484  CSR_WRITE(sc, WMREG_PBA, sc->sc_pba);
485
486  /* device reset */
487  CSR_WRITE(sc, WMREG_CTRL, CTRL_RST);
488  rtems_bsp_delay(10000);
489
490  for (i = 0; i < 1000; i++) {
491      if ((CSR_READ(sc, WMREG_CTRL) & CTRL_RST) == 0)
492        break;
493      rtems_bsp_delay(20);
494  }
495  if (CSR_READ(sc, WMREG_CTRL) & CTRL_RST)
496      printk("Intel 82544 1GHz reset failed to complete\n");
497
498  sc->sc_ctrl_ext = CSR_READ(sc,WMREG_CTRL_EXT);
499  sc->sc_ctrl_ext |= CTRL_EXT_EE_RST;
500  CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 
501  CSR_READ(sc, WMREG_STATUS);
502  /* Wait for EEPROM reload */
503  rtems_bsp_delay(2000);
504  sc->sc_ctrl= CSR_READ(sc, WMREG_CTRL);
505}
506
507/*
508 * i82544EI_ifstart:            [ifnet interface function]
509 *
510 *      Start packet transmission on the interface.
511 */
512static void
513i82544EI_ifstart(struct ifnet *ifp)
514{
515  struct wm_softc *sc = ifp->if_softc;
516
517#ifdef WM_DEBUG
518  printk("i82544EI_ifstart(");
519#endif
520
521  if ((ifp->if_flags & IFF_RUNNING) == 0) {
522#ifdef WM_DEBUG
523     printk("IFF_RUNNING==0\n");
524#endif         
525     return;
526  }
527
528  ifp->if_flags |= IFF_OACTIVE;
529  rtems_event_send (sc->daemonTid, START_TRANSMIT_EVENT);
530#ifdef WM_DEBUG
531  printk(")\n");
532#endif
533}
534
535static void i82544EI_stats(struct wm_softc *sc)
536{
537  struct ifnet *ifp = &sc->arpcom.ac_if;
538
539  printf("    Ghost Interrupts:%-8lu\n", sc->stats.ghostInterrupts);
540  printf("       Rx Interrupts:%-8lu\n", sc->stats.rxInterrupts);
541  printf("     Receive Packets:%-8u\n", CSR_READ(sc,WMREG_GPRC));
542  printf("     Receive Overrun:%-8lu\n", sc->stats.rxOvrRunInterrupts);
543  printf("     Receive  errors:%-8u\n", CSR_READ(sc,WMREG_RXERRC));
544  printf("   Rx sequence error:%-8lu\n", sc->stats.rxSeqErr);
545  printf("      Rx /C/ ordered:%-8lu\n", sc->stats.rxC_ordered);
546  printf("    Rx Length Errors:%-8u\n", CSR_READ(sc,WMREG_RLEC));
547  printf("       Tx Interrupts:%-8lu\n", sc->stats.txInterrupts);
548  printf("   Transmitt Packets:%-8u\n", CSR_READ(sc,WMREG_GPTC));
549  printf("   Transmitt  errors:%-8lu\n", ifp->if_oerrors);
550  printf("         Active Txqs:%-8lu\n", sc->txq_nactive); 
551  printf("          collisions:%-8u\n", CSR_READ(sc,WMREG_COLC));
552  printf("          Crc Errors:%-8u\n", CSR_READ(sc,WMREG_CRCERRS));
553  printf("  Link Status Change:%-8lu\n", sc->stats.linkStatusChng);
554}
555
556/*
557 * wm_ioctl:            [ifnet interface function]
558 *
559 *      Handle control requests from the operator.
560 */
561static int wm_ioctl(struct ifnet *ifp, ioctl_command_t cmd,caddr_t data)
562{
563  struct wm_softc *sc = ifp->if_softc;
564  int error=0;
565
566  switch (cmd) {
567    default:
568      error = ether_ioctl(ifp, cmd, data);
569      if (error == ENETRESET) {
570          /*
571           * Multicast list has changed; set the hardware filter
572           * accordingly.
573           */
574          wm_set_filter(sc);
575          error = 0;
576      }
577      break;
578    case SIO_RTEMS_SHOW_STATS:
579      i82544EI_stats(sc);
580      break;
581  }
582
583  /* Try to get more packets going.*/
584  i82544EI_ifstart(ifp);
585  return (error);
586}
587
588/*
589 * wm_isr:
590 *
591 *      Interrupt service routine.
592 */
593static void i82544EI_isr(rtems_irq_hdl_param handle)
594{
595  volatile struct wm_softc *sc = (struct wm_softc *) handle;
596  uint32_t icr;
597  rtems_event_set  events=0;
598
599  /* Reading the WMREG_ICR clears the interrupt bits */
600  icr = CSR_READ(sc,WMREG_ICR);
601
602  if ( icr & (ICR_RXDMT0|ICR_RXT0)) {
603     sc->stats.rxInterrupts++;
604     events |= RX_EVENT;
605  }
606
607  if (icr & ICR_TXDW) {
608     sc->stats.txInterrupts++;
609     events |= TX_EVENT;
610  }
611  /* <SKF> Rx overrun : no available receive buffer
612   * or PCI receive bandwidth inadequate.
613   */
614  if (icr & ICR_RXO) {
615     sc->stats.rxOvrRunInterrupts++;
616     events |= INIT_EVENT;
617  }
618  if (icr & ICR_RXSEQ) /* framing error */ {
619     sc->if_errsts[sc->if_err_ptr2++]=icr;
620     if ( sc->if_err_ptr2 ==IF_ERR_BUFSZE) sc->if_err_ptr2=0;
621     events |= ERR_EVENT;
622     sc->stats.rxSeqErr++;
623  }
624  if ( !icr) sc->stats.ghostInterrupts++;
625
626  if (icr & ICR_LSC) sc->stats.linkStatusChng++;
627  if (icr & ICR_RXCFG) sc->stats.rxC_ordered++;
628
629  rtems_event_send(sc->daemonTid, events);
630}
631
632/*
633 * i82544EI_sendpacket:
634 *
635 *      Helper; handle transmit interrupts.
636 */
637static void i82544EI_sendpacket(struct wm_softc *sc, struct mbuf *m)
638{
639
640#ifdef WM_DEBUG_TX
641  printk("sendpacket(");
642#endif
643
644  if ( !(m->m_next)) { /* single buffer packet */
645    sc->txs_mbuf[sc->txq_next]= m;
646    /* Note: we currently only use 32-bit DMA addresses. */
647    sc->sc_txdescs[sc->txq_next].wtx_addr.wa_low = htole32(mtod(m, void*));
648    sc->sc_txdescs[sc->txq_next].wtx_cmdlen =htole32(TxDescCmd | m->m_len);
649    sc->txs_lastdesc= sc->txq_next;
650    sc->txq_next = WM_NEXTTX(sc->txq_next);
651    sc->txq_nactive++;
652    sc->txq_free--;
653  }
654  else /* multiple mbufs in this packet */
655  { 
656    struct mbuf *mtp, *mdest;
657    volatile unsigned char *pt;
658    int len, y, loop=0;
659
660#ifdef WM_DEBUG_TX
661    printk("multi mbufs ");
662#endif
663    mtp = m;
664    while ( mtp) { 
665      MGETHDR(mdest, M_WAIT, MT_DATA);
666      MCLGET(mdest, M_WAIT);
667      pt = (volatile unsigned char *)mdest->m_data;
668      for ( len=0;mtp;mtp=mtp->m_next) {
669        loop++;
670        /* Each descriptor gets a 2k (MCLBYTES) buffer, although
671         * the length of each descriptor can be up to 16288 bytes.
672         * For packets which fill more than one buffer ( >2k), we
673         * chain them together.
674         * <Kate Feng> : This effective for packets > 2K
675         * The other way is effective for packets < 2K
676         */
677        if ( ((y=(len+mtp->m_len)) > sizeof(union mcluster))) {
678          printk(" >%d, use next descriptor\n", sizeof(union mcluster));
679          break; 
680        }
681        memcpy((void *)pt,(char *)mtp->m_data, mtp->m_len);
682        pt += mtp->m_len;
683        len += mtp->m_len;
684      } /* end for loop */
685      mdest->m_len=len;
686      sc->txs_mbuf[sc->txq_next] = mdest;
687      /* Note: we currently only use 32-bit DMA addresses. */
688      sc->sc_txdescs[sc->txq_next].wtx_addr.wa_low = htole32(mtod(mdest, void*));
689      sc->sc_txdescs[sc->txq_next].wtx_cmdlen = htole32(TxDescCmd|mdest->m_len);
690      sc->txs_lastdesc = sc->txq_next;
691      sc->txq_next = WM_NEXTTX(sc->txq_next);
692      sc->txq_nactive ++;
693      if (sc->txq_free) 
694         sc->txq_free--;
695      else
696         rtems_panic("i8254EI : no more free descriptors");
697    } /* end for while */
698    /* free old mbuf chain */
699    m_freem(m); 
700    m=0;
701  }  /* end  multiple mbufs */
702   
703  DPRINTF(WM_DEBUG_TX,("%s: TX: desc %d: cmdlen 0x%08x\n", sc->dv_xname,
704         sc->txs_lastdesc, le32toh(sc->sc_txdescs[sc->txs_lastdesc].wtx_cmdlen)));
705  DPRINTF(WM_DEBUG_TX,("status 0x%08x\n",sc->sc_txdescs[sc->txq_fi].wtx_fields.wtxu_status));
706
707  memBar();
708
709  /* This is the location where software writes the first NEW descriptor */
710  CSR_WRITE(sc,WMREG_TDT, sc->txq_next);
711
712  DPRINTF(WM_DEBUG_TX,("%s: addr 0x%08x, TX: TDH %d, TDT %d\n",sc->dv_xname,
713  le32toh(sc->sc_txdescs[sc->txs_lastdesc].wtx_addr.wa_low), CSR_READ(sc,WMREG_TDH),
714          CSR_READ(sc,WMREG_TDT)));
715
716  DPRINTF(WM_DEBUG_TX,("%s: TX: finished transmitting packet, job %d\n",
717                    sc->dv_xname, sc->txq_next));
718
719}
720
721static void i82544EI_txq_free(struct wm_softc *sc, uint8_t status)
722{
723  struct ifnet *ifp = &sc->arpcom.ac_if;
724
725  /* We might use the statistics registers instead of variables
726   * to keep tack of the network statistics
727   */ 
728
729  /* statistics */
730  ifp->if_opackets++;
731
732  if (status & (WTX_ST_EC|WTX_ST_LC)) {
733       ifp->if_oerrors++;
734
735     if (status & WTX_ST_LC) 
736        printf("%s: late collision\n", sc->dv_xname);
737     else if (status & WTX_ST_EC) {
738        ifp->if_collisions += 16;
739         printf("%s: excessive collisions\n", sc->dv_xname);
740     }
741  }
742  /* Free the original mbuf chain */
743  m_freem(sc->txs_mbuf[sc->txq_fi]);
744  sc->txs_mbuf[sc->txq_fi] = 0;
745  sc->sc_txdescs[sc->txq_fi].wtx_fields.wtxu_status=0;
746
747  sc->txq_free ++;
748  sc->txq_fi = WM_NEXTTX(sc->txq_fi);
749  --sc->txq_nactive;
750}
751
752static void i82544EI_txq_done(struct wm_softc *sc)
753{
754  uint8_t status;
755
756  /*
757   * Go through the Tx list and free mbufs for those
758   * frames which have been transmitted.
759   */
760  while ( sc->txq_nactive > 0) {
761    status = sc->sc_txdescs[sc->txq_fi].wtx_fields.wtxu_status;
762    if ((status & WTX_ST_DD) == 0) break;
763    i82544EI_txq_free(sc, status);
764    DPRINTF(WM_DEBUG_TX,("%s: TX: job %d done\n",
765                    sc->dv_xname, sc->txq_fi));
766  }
767}
768
769static void wm_init_rxdesc(struct wm_softc *sc, int x) 
770{                       
771  wiseman_rxdesc_t *__rxd = &(sc)->sc_rxdescs[(x)];             
772  struct mbuf *m;
773
774  m = sc->rxs_mbuf[x];
775               
776  __rxd->wrx_addr.wa_low=htole32(mtod(m, void*)); 
777  __rxd->wrx_addr.wa_high = 0;                                 
778  __rxd->wrx_len = 0;                                             
779  __rxd->wrx_cksum = 0;                                           
780  __rxd->wrx_status = 0;                                               
781  __rxd->wrx_errors = 0;                                         
782  __rxd->wrx_special = 0;                                         
783  /* Receive Descriptor Tail: add Rx desc. to H/W free list */   
784  CSR_WRITE(sc,WMREG_RDT, (x));                                         
785} 
786
787static void i82544EI_rx(struct wm_softc *sc)
788{
789  struct ifnet *ifp = &sc->arpcom.ac_if;
790  struct mbuf *m;
791  int i, len;
792  uint8_t status, errors;
793  struct ether_header *eh;
794
795#ifdef WM_DEBUG
796  printk("i82544EI_rx()\n");
797#endif
798
799  for (i = sc->sc_rxptr;; i = WM_NEXTRX(i)) {
800    DPRINTF(WM_DEBUG_RX, ("%s: RX: checking descriptor %d\n",
801                    sc->dv_xname, i));
802
803    status = sc->sc_rxdescs[i].wrx_status;
804    if ((status & WRX_ST_DD) == 0)  break; /* descriptor not done */
805
806    errors = sc->sc_rxdescs[i].wrx_errors;
807    len = le16toh(sc->sc_rxdescs[i].wrx_len);
808    m = sc->rxs_mbuf[i];
809    if (sc->sc_rxdiscard) {
810       printk("RX: discarding contents of descriptor %d\n", i);
811       wm_init_rxdesc(sc, i);
812       if (status & WRX_ST_EOP) {
813          /* Reset our state. */
814          printk("RX: resetting rxdiscard -> 0\n");
815          sc->sc_rxdiscard = 0;
816       }
817       continue;
818    }
819
820    /*
821     * If an error occurred, update stats and drop the packet.
822     */
823    if (errors &(WRX_ER_CE|WRX_ER_SE|WRX_ER_SEQ|WRX_ER_CXE|WRX_ER_RXE)) {
824       ifp->if_ierrors++;
825       if (errors & WRX_ER_SE)
826          printk("%s: symbol error\n",sc->dv_xname);
827       else if (errors & WRX_ER_SEQ)
828          printk("%s: receive sequence error\n",sc->dv_xname);
829            else if (errors & WRX_ER_CE)
830                 printk("%s: CRC error\n",sc->dv_xname);
831       m_freem(m);
832       goto give_it_back;
833    }
834
835    /*
836     * No errors.  Receive the packet.
837     *
838     * Note, we have configured the chip to include the
839     * CRC with every packet.
840     */
841    m->m_len = m->m_pkthdr.len = len - sizeof(struct ether_header);
842
843    DPRINTF(WM_DEBUG_RX,("%s: RX: buffer at %p len %d\n",
844                    sc->dv_xname, m->m_data, len));
845
846
847    eh = mtod (m, struct ether_header *);
848    m->m_data += sizeof(struct ether_header);
849    ether_input (ifp, eh, m);
850    /* Pass it on. */
851    ifp->if_ipackets++;
852   
853    give_it_back:
854    /* Add a new receive buffer to the ring.*/
855    if (wm_add_rxbuf(sc, i) != 0) {
856       /*
857        * Failed, throw away what we've done so
858        * far, and discard the rest of the packet.
859        */
860       printk("Failed in wm_add_rxbuf(), drop packet\n");
861       ifp->if_ierrors++;
862       wm_init_rxdesc(sc, i);
863       if ((status & WRX_ST_EOP) == 0)
864          sc->sc_rxdiscard = 1;
865       m_freem(m);
866    }
867  } /* end for */
868
869  /* Update the receive pointer. */
870  sc->sc_rxptr = i;
871  DPRINTF(WM_DEBUG_RX, ("%s: RX: rxptr -> %d\n", sc->dv_xname, i));
872}
873
874static int i82544EI_init_hw(struct wm_softc *sc)
875{
876  struct ifnet *ifp = &sc->arpcom.ac_if;
877  int i,error;
878  uint8_t cksumfields;
879
880#if 0
881  /* KATETODO : sc_align_tweak */
882        /*
883         * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set.
884         * There is a small but measurable benefit to avoiding the adjusment
885         * of the descriptor so that the headers are aligned, for normal mtu,
886         * on such platforms.  One possibility is that the DMA itself is
887         * slightly more efficient if the front of the entire packet (instead
888         * of the front of the headers) is aligned.
889         *
890         * Note we must always set align_tweak to 0 if we are using
891         * jumbo frames.
892         */
893#ifdef __NO_STRICT_ALIGNMENT
894        sc->sc_align_tweak = 0;
895#else
896        if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2))
897                sc->sc_align_tweak = 0;
898        else
899                sc->sc_align_tweak = 2;
900#endif /* __NO_STRICT_ALIGNMENT */
901#endif
902
903  /* Cancel any pending I/O. */
904  wm_stop(ifp, 0);
905
906  /* update statistics before reset */
907  ifp->if_collisions += CSR_READ(sc, WMREG_COLC);
908  ifp->if_ierrors += CSR_READ(sc, WMREG_RXERRC);
909
910  /* Reset the chip to a known state. */
911  wm_reset(sc);
912
913  /* Initialize the error buffer ring */
914  sc->if_err_ptr1=0;
915  sc->if_err_ptr2=0;
916  for (i=0; i< IF_ERR_BUFSZE; i++) sc->if_errsts[i]=0;
917
918  /* Initialize the transmit descriptor ring. */
919  memset( (void *) sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
920  sc->txq_free = NTXDESC;
921  sc->txq_next = 0;
922  sc->txs_lastdesc = 0;
923  sc->txq_next = 0;
924  sc->txq_free = NTXDESC;
925  sc->txq_nactive = 0;
926
927  sc->sc_txctx_ipcs = 0xffffffff;
928  sc->sc_txctx_tucs = 0xffffffff;
929
930  CSR_WRITE(sc,WMREG_TBDAH, 0);
931  CSR_WRITE(sc,WMREG_TBDAL, WM_CDTXADDR(sc));
932#ifdef WM_DEBUG
933  printk("TBDAL 0x%x, TDLEN %d\n", WM_CDTXADDR(sc), sizeof(sc->sc_txdescs));
934#endif
935  CSR_WRITE(sc,WMREG_TDLEN, sizeof(sc->sc_txdescs));
936  CSR_WRITE(sc,WMREG_TDH, 0);
937  CSR_WRITE(sc,WMREG_TDT, 0);
938  CSR_WRITE(sc,WMREG_TIDV, 0 ); 
939  /* CSR_WRITE(sc,WMREG_TADV, 128);  not for 82544 */
940
941  CSR_WRITE(sc,WMREG_TXDCTL, TXDCTL_PTHRESH(0) |
942                    TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0));
943  CSR_WRITE(sc,WMREG_RXDCTL, RXDCTL_PTHRESH(0) |
944                    RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1) | RXDCTL_GRAN );
945
946  CSR_WRITE(sc,WMREG_TQSA_LO, 0);
947  CSR_WRITE(sc,WMREG_TQSA_HI, 0);
948
949  /*
950   * Set up checksum offload parameters for
951   * this packet.
952   */
953#ifdef RTEMS_CKSUM_OFFLOAD
954  if (m0->m_pkthdr.csum_flags & (M_CSUM_TSOv4|M_CSUM_TSOv6|
955                    M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4|
956                                 M_CSUM_TCPv6|M_CSUM_UDPv6)) {
957     if (wm_tx_offload(sc, txs, &TxDescCmd,&cksumfields) != 0) {
958         /* Error message already displayed. */
959         continue;
960     }
961  } else {
962#endif
963     TxDescCmd = 0;
964     cksumfields = 0;
965#ifdef RTEMS_CKSUM_OFFLOAD
966  }
967#endif
968
969  TxDescCmd |= WTX_CMD_EOP|WTX_CMD_IFCS|WTX_CMD_RS; 
970
971  /* Initialize the transmit job descriptors. */
972  for (i = 0; i < NTXDESC; i++) {
973      sc->txs_mbuf[i] = 0;
974      sc->sc_txdescs[i].wtx_fields.wtxu_options=cksumfields;
975      sc->sc_txdescs[i].wtx_addr.wa_high = 0;
976      sc->sc_txdescs[i].wtx_addr.wa_low = 0;
977      sc->sc_txdescs[i].wtx_cmdlen = htole32(TxDescCmd); 
978  }
979
980  /*
981   * Initialize the receive descriptor and receive job
982   * descriptor rings.
983   */
984  memset( (void *) sc->sc_rxdescs, 0, sizeof(sc->sc_rxdescs));
985  CSR_WRITE(sc,WMREG_RDBAH, 0);
986  CSR_WRITE(sc,WMREG_RDBAL, WM_CDRXADDR(sc));
987  CSR_WRITE(sc,WMREG_RDLEN, sizeof(sc->sc_rxdescs));
988  CSR_WRITE(sc,WMREG_RDH, 0);
989  CSR_WRITE(sc,WMREG_RDT, 0);
990  CSR_WRITE(sc,WMREG_RDTR, 0 |RDTR_FPD); 
991  /* CSR_WRITE(sc, WMREG_RADV, 256);  not for 82544.  */
992
993  for (i = 0; i < NRXDESC; i++) {
994      if (sc->rxs_mbuf[i] == NULL) {
995         if ((error = wm_add_rxbuf(sc, i)) != 0) {
996            printk("%s%d: unable to allocate or map rx buffer"
997            "%d, error = %d\n",ifp->if_name,ifp->if_unit, i, error);
998            /*
999             * XXX Should attempt to run with fewer receive
1000             * XXX buffers instead of just failing.
1001             */
1002            wm_rxdrain(sc);
1003            return(error);
1004          }
1005      } else {
1006        printk("sc->rxs_mbuf[%d] not NULL.\n", i);
1007        wm_init_rxdesc(sc, i);
1008      }
1009  }
1010  sc->sc_rxptr = 0;
1011  sc->sc_rxdiscard = 0;
1012
1013  /*
1014   * Clear out the VLAN table -- we don't use it (yet).
1015   */
1016  CSR_WRITE(sc,WMREG_VET, 0);
1017  for (i = 0; i < WM_VLAN_TABSIZE; i++)
1018       CSR_WRITE(sc,WMREG_VFTA + (i << 2), 0);
1019
1020#if 0
1021  /* Use MOTLoad default
1022  /*
1023   * Set up flow-control parameters.
1024   */
1025  CSR_WRITE(sc,WMREG_FCAL, FCAL_CONST);/* same as MOTLOAD 0x00c28001 */
1026  CSR_WRITE(sc,WMREG_FCAH, FCAH_CONST);/* same as MOTLOAD 0x00000100 */
1027  CSR_WRITE(sc,WMREG_FCT, ETHERTYPE_FLOWCONTROL);/* same as MOTLoad 0x8808 */
1028
1029
1030  /* safe,even though MOTLoad default all 0 */
1031  sc->sc_fcrtl = FCRTL_DFLT;
1032
1033  CSR_WRITE(sc,WMREG_FCRTH, FCRTH_DFLT);
1034  CSR_WRITE(sc,WMREG_FCRTL, sc->sc_fcrtl);
1035  /*KATETO   CSR_WRITE(sc,WMREG_FCTTV, FCTTV_DFLT);*/
1036  CSR_WRITE(sc,WMREG_FCTTV, 0x100);
1037#endif
1038
1039  sc->sc_ctrl &= ~CTRL_VME;
1040  /* TODO : not here.
1041     Configures flow control settings after link is established
1042     sc->sc_ctrl |= CTRL_TFCE | CTRL_RFCE; */
1043
1044  /* Write the control registers. */
1045  CSR_WRITE(sc,WMREG_CTRL, sc->sc_ctrl);
1046#if 0
1047  CSR_WRITE(sc,WMREG_CTRL_EXT, sc->sc_ctrl_ext);
1048#endif
1049
1050  /* MOTLoad : WMREG_RXCSUM (0x5000)= 0, no Rx checksum offloading */ 
1051#ifdef RTEMS_CKSUM_OFFLOAD
1052  /*
1053   * Set up checksum offload parameters.
1054   */
1055   reg = CSR_READ(sc, WMREG_RXCSUM);
1056   reg &= ~(RXCSUM_IPOFL | RXCSUM_IPV6OFL | RXCSUM_TUOFL);
1057   if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx)
1058            reg |= RXCSUM_IPOFL;
1059   if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx))
1060            reg |= RXCSUM_IPOFL | RXCSUM_TUOFL;
1061   if (ifp->if_capenable & (IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx))
1062            reg |= RXCSUM_IPV6OFL | RXCSUM_TUOFL;
1063   CSR_WRITE(sc, WMREG_RXCSUM, reg);
1064#endif
1065
1066  /*
1067   * Set up the interrupt registers.
1068   */
1069  CSR_WRITE(sc,WMREG_IMC, 0xffffffffU);
1070
1071  /* Reading the WMREG_ICR clears the interrupt bits */
1072  CSR_READ(sc,WMREG_ICR);
1073
1074  /*  printf("WMREG_IMS 0x%x\n", CSR_READ(sc,WMREG_IMS));*/
1075
1076  sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXCFG | ICR_RXDMT0 | ICR_RXO | ICR_RXT0;
1077
1078  CSR_WRITE(sc,WMREG_IMS, sc->sc_icr);
1079
1080  /* Set up the inter-packet gap. */
1081  CSR_WRITE(sc,WMREG_TIPG, sc->sc_tipg);
1082
1083#if 0 /* XXXJRT */
1084  /* Set the VLAN ethernetype. */
1085  CSR_WRITE(sc,WMREG_VET, ETHERTYPE_VLAN);
1086#endif
1087
1088  /*
1089   * Set up the transmit control register; we start out with
1090   * a collision distance suitable for FDX, but update it when
1091   * we resolve the media type.
1092   */
1093  sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_CT(TX_COLLISION_THRESHOLD) |
1094            TCTL_COLD(TX_COLLISION_DISTANCE_FDX) |
1095            TCTL_RTLC /* retransmit on late collision */; 
1096
1097  /*
1098   * Set up the receive control register; we actually program
1099   * the register when we set the receive filter.  Use multicast
1100   * address offset type 0.
1101   *
1102   * Only the i82544 has the ability to strip the incoming
1103   * CRC (RCTL_SECRC).
1104   */
1105  sc->sc_mchash_type = 0;
1106  sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_LPE |
1107    RCTL_DPF | RCTL_MO(sc->sc_mchash_type)|RCTL_SECRC;
1108
1109  if (MCLBYTES == 2048) {
1110     sc->sc_rctl |= RCTL_2k;
1111  } else {
1112        switch(MCLBYTES) {
1113        case 4096:
1114             sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k;
1115             break;
1116        case 8192:
1117             sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k;
1118             break;
1119        case 16384:
1120             sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k;
1121             break;
1122        default:
1123             rtems_panic("wm_init: MCLBYTES %d unsupported",
1124                    MCLBYTES);
1125             break;
1126        }
1127  }
1128
1129#ifdef WM_DEBUG
1130  printk("RDBAL 0x%x,RDLEN %d, RDT %d\n",CSR_READ(sc,WMREG_RDBAL),CSR_READ(sc,WMREG_RDLEN), CSR_READ(sc,WMREG_RDT));
1131#endif
1132
1133  /* Set the receive filter. */
1134  wm_set_filter(sc);
1135
1136  CSR_WRITE(sc,WMREG_TCTL, sc->sc_tctl);
1137
1138  /* Map and establish our interrupt. */
1139  if (!BSP_install_rtems_irq_handler(&i82544IrqData))
1140     rtems_panic("1GHZ ethernet: unable to install ISR");
1141
1142  return(0);
1143}
1144
1145void BSP_rdTIDV()
1146{
1147  printf("Reg TIDV: 0x%x\n", in_le32((volatile unsigned *) (BSP_1GHz_membase+WMREG_TIDV)));
1148}
1149void BSP_rdRDTR()
1150{
1151  printf("Reg RDTR: 0x%x\n", in_le32((volatile unsigned *) (BSP_1GHz_membase+WMREG_RDTR)));
1152}
1153
1154void BSP_setTIDV(int val)
1155{
1156  out_le32((volatile unsigned *) (BSP_1GHz_membase+WMREG_TIDV), val);
1157}
1158
1159void BSP_setRDTR(int val)
1160{
1161  out_le32((volatile unsigned *) (BSP_1GHz_membase+WMREG_RDTR), val);
1162}
1163/*
1164 * i82544EI_ifinit:             [ifnet interface function]
1165 *
1166 *      Initialize the interface.
1167 */
1168static void i82544EI_ifinit(void *arg)
1169{
1170  struct wm_softc *sc = (struct wm_softc*)arg;
1171
1172#ifdef WM_DEBUG
1173  printk("i82544EI_ifinit(): daemon ID: 0x%08x)\n", sc->daemonTid);
1174#endif
1175  if (sc->daemonTid) {
1176#ifdef WM_DEBUG
1177     printk("i82544EI: daemon already up, doing nothing\n");
1178#endif
1179     return;
1180  }
1181  i82544EI_init_hw(sc);
1182
1183  sc->daemonTid = rtems_bsdnet_newproc(i82544EI_TASK_NAME,4096,i82544EI_daemon,arg);
1184
1185  /* ...all done! */
1186  sc->arpcom.ac_if.if_flags |= IFF_RUNNING; 
1187
1188#ifdef WM_DEBUG
1189  printk(")");
1190#endif
1191}
1192
1193/*
1194 * wm_txdrain:
1195 *
1196 *      Drain the transmit queue.
1197 */
1198static void wm_txdrain(struct wm_softc *sc)
1199{
1200  int i;
1201
1202  /* Release any queued transmit buffers. */
1203  for (i = 0; i <  NTXDESC; i++) {
1204      if (sc->txs_mbuf[i] != NULL) {
1205          m_freem(sc->txs_mbuf[i]);
1206          sc->txs_mbuf[i] = NULL;
1207      }
1208  }
1209}
1210
1211/*
1212 * wm_rxdrain:
1213 *
1214 *      Drain the receive queue.
1215 */
1216static void wm_rxdrain(struct wm_softc *sc)
1217{
1218  int i;
1219
1220  for (i = 0; i < NRXDESC; i++) {
1221      if (sc->rxs_mbuf[i] != NULL) {
1222          m_freem(sc->rxs_mbuf[i]);
1223          sc->rxs_mbuf[i] = NULL;
1224      }
1225  }
1226}
1227
1228static void i82544EI_tx_stop(struct wm_softc *sc)
1229{
1230  wm_txdrain(sc);
1231}
1232
1233static void i82544EI_rx_stop(struct wm_softc *sc)
1234{
1235  wm_rxdrain(sc);
1236}
1237
1238static void i82544EI_stop_hw(struct wm_softc *sc)
1239{
1240#ifdef WM_DEBUG
1241  printk("i82544EI_stop_hw(");
1242#endif
1243
1244  /* remove our interrupt handler which will also
1245  * disable interrupts at the MPIC and the device
1246  * itself
1247  */
1248  if (!BSP_remove_rtems_irq_handler(&i82544IrqData))
1249     rtems_panic("i82544EI: unable to remove IRQ handler!");
1250
1251  CSR_WRITE(sc,WMREG_IMS, 0);
1252
1253  sc->arpcom.ac_if.if_flags &= ~IFF_RUNNING;
1254  i82544EI_tx_stop(sc);
1255  i82544EI_rx_stop(sc);
1256#ifdef WM_DEBUG
1257  printk(")");
1258#endif
1259}
1260
1261/*
1262 * wm_stop:             [ifnet interface function]
1263 *
1264 *      Stop transmission on the interface.
1265 */
1266static void wm_stop(struct ifnet *ifp, int disable)
1267{
1268  struct wm_softc *sc = ifp->if_softc;
1269
1270#ifdef WM_DEBUG
1271  printk("wm_stop(");
1272#endif 
1273  /* Stop the transmit and receive processes. */
1274  CSR_WRITE(sc,WMREG_TCTL, 0);
1275  CSR_WRITE(sc,WMREG_RCTL, 0);
1276
1277  wm_txdrain(sc);
1278  wm_rxdrain(sc);
1279
1280  /* Mark the interface as down  */
1281  ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1282#ifdef WM_DEBUG
1283  printk(")\n");
1284#endif 
1285}
1286
1287/*
1288 * wm_eeprom_sendbits:
1289 *
1290 *      Send a series of bits to the EEPROM.
1291 */
1292static void wm_eeprom_sendbits(struct wm_softc *sc, uint32_t bits, int nbits)
1293{
1294  uint32_t reg;
1295  int x;
1296
1297  reg = CSR_READ(sc,WMREG_EECD);
1298
1299  for (x = nbits; x > 0; x--) {
1300      if (bits & (1U << (x - 1)))
1301         reg |= EECD_DI;
1302      else
1303         reg &= ~EECD_DI;
1304      CSR_WRITE(sc,WMREG_EECD, reg);
1305      rtems_bsp_delay(2);
1306      CSR_WRITE(sc,WMREG_EECD, reg | EECD_SK);
1307      rtems_bsp_delay(2);
1308      CSR_WRITE(sc,WMREG_EECD, reg);
1309      rtems_bsp_delay(2);
1310  }
1311}
1312
1313/*
1314 * wm_eeprom_recvbits:
1315 *
1316 *      Receive a series of bits from the EEPROM.
1317 */
1318static void wm_eeprom_recvbits(struct wm_softc *sc, uint32_t *valp, int nbits)
1319{
1320  uint32_t reg, val;
1321  int x;
1322
1323  reg = CSR_READ(sc,WMREG_EECD) & ~EECD_DI;
1324
1325  val = 0;
1326  for (x = nbits; x > 0; x--) {
1327      CSR_WRITE(sc,WMREG_EECD, reg | EECD_SK);
1328      rtems_bsp_delay(2);
1329      if (CSR_READ(sc,WMREG_EECD) & EECD_DO)
1330         val |= (1U << (x - 1));
1331      CSR_WRITE(sc,WMREG_EECD, reg);
1332      rtems_bsp_delay(2);
1333  }
1334  *valp = val;
1335}
1336
1337/*
1338 * wm_read_eeprom_uwire:
1339 *
1340 * Read a word from the EEPROM using the MicroWire protocol.
1341 *
1342 * (The 82544EI Gigabit Ethernet Controller is compatible with
1343 * most MicroWire interface, serial EEPROM devices.)
1344 */
1345static int wm_read_eeprom_uwire(struct wm_softc *sc, int word, int wordcnt, uint16_t *data)
1346{
1347  uint32_t reg, val;
1348  int i;
1349
1350  for (i = 0; i < wordcnt; i++) {
1351      /* Clear SK and DI. */
1352      reg = CSR_READ(sc,WMREG_EECD) & ~(EECD_SK | EECD_DI);
1353      CSR_WRITE(sc,WMREG_EECD, reg);
1354
1355      /* Set CHIP SELECT. */
1356      reg |= EECD_CS;
1357      CSR_WRITE(sc,WMREG_EECD, reg);
1358      rtems_bsp_delay(2);
1359
1360      /* Shift in the READ command. */
1361      wm_eeprom_sendbits(sc, UWIRE_OPC_READ, 3);
1362
1363      /* Shift in address. */
1364      wm_eeprom_sendbits(sc, word + i, sc->sc_ee_addrbits);
1365
1366      /* Shift out the data. */
1367      wm_eeprom_recvbits(sc, &val, 16);
1368      data[i] = val & 0xffff;
1369
1370      /* Clear CHIP SELECT. */
1371      reg = CSR_READ(sc,WMREG_EECD) & ~EECD_CS;
1372      CSR_WRITE(sc,WMREG_EECD, reg);
1373      rtems_bsp_delay(2);
1374  }
1375  return (0);
1376}
1377
1378#if 0
1379/*
1380 * wm_acquire_eeprom:
1381 *
1382 *      Perform the EEPROM handshake required on some chips.
1383 */
1384static int wm_acquire_eeprom(struct wm_softc *sc)
1385{
1386  uint32_t reg;
1387  int x;
1388
1389  reg = CSR_READ(sc,WMREG_EECD);
1390
1391  /* Request EEPROM access. */
1392  reg |= EECD_EE_REQ;
1393  CSR_WRITE(sc,WMREG_EECD, reg);
1394
1395  /* ..and wait for it to be granted. */
1396  for (x = 0; x < 100; x++) {
1397      reg = CSR_READ(sc,WMREG_EECD);
1398      if (reg & EECD_EE_GNT) break;
1399      rtems_bsp_delay(500);
1400  }
1401  if ((reg & EECD_EE_GNT) == 0) {
1402      printk("Could not acquire EEPROM GNT x= %d\n", x);
1403      reg &= ~EECD_EE_REQ;
1404      CSR_WRITE(sc,WMREG_EECD, reg);
1405      return (1);
1406  }
1407
1408  return (0);
1409}
1410#endif
1411
1412/*
1413 * wm_read_eeprom:
1414 *
1415 * Read data from the serial EEPROM.
1416 * 82544EI does not Perform the EEPROM handshake
1417 */
1418static int wm_read_eeprom(struct wm_softc *sc, int word, int wordcnt, uint16_t *data)
1419{
1420#if 0
1421  /* base on the datasheet, this does not seem to be applicable */
1422  if (wm_acquire_eeprom(sc))
1423     return(1);
1424#endif
1425  return(wm_read_eeprom_uwire(sc, word, wordcnt, data));
1426}
1427
1428/*
1429 * wm_add_rxbuf:
1430 *
1431 *      Add a receive buffer to the indiciated descriptor.
1432 */
1433static int wm_add_rxbuf(struct wm_softc *sc, int idx)
1434{
1435  struct mbuf *m;
1436
1437  MGETHDR(m, M_WAIT, MT_DATA);
1438  if (m == NULL) return (ENOBUFS);
1439  MCLGET(m, M_WAIT);
1440  if ((m->m_flags & M_EXT) == 0) {
1441     m_freem(m);
1442     return (ENOBUFS);
1443  }
1444  m->m_pkthdr.rcvif =  &sc->arpcom.ac_if;
1445  sc->rxs_mbuf[idx] = m;
1446  /*  m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;*/
1447  wm_init_rxdesc(sc, idx);
1448#if 0
1449  printk("sc->rxs_mbuf[%d]= 0x%x, mbuf @ 0x%x\n",
1450    idx, sc->rxs_mbuf[idx], le32toh(sc->sc_rxdescs[idx].wrx_addr.wa_low));
1451#endif
1452  return(0);
1453}
1454
1455/*
1456 * wm_set_ral:
1457 *
1458 *      Set an entery in the receive address list.
1459 */
1460static void
1461wm_set_ral(struct wm_softc *sc, const uint8_t *enaddr, int idx)
1462{
1463  uint32_t ral_lo, ral_hi;
1464
1465  if (enaddr != NULL) {
1466     ral_lo = enaddr[0]|(enaddr[1] << 8)|(enaddr[2] << 16)|(enaddr[3] << 24);
1467     ral_hi = enaddr[4] | (enaddr[5] << 8);
1468     ral_hi |= RAL_AV;
1469  } else {
1470     ral_lo = 0;
1471     ral_hi = 0;
1472  }
1473
1474  CSR_WRITE(sc,WMREG_RAL_LO(WMREG_CORDOVA_RAL_BASE, idx),ral_lo);
1475  CSR_WRITE(sc,WMREG_RAL_HI(WMREG_CORDOVA_RAL_BASE, idx),ral_hi);
1476}
1477
1478/*
1479 * wm_mchash:
1480 *
1481 *      Compute the hash of the multicast address for the 4096-bit
1482 *      multicast filter.
1483 */
1484static uint32_t
1485wm_mchash(struct wm_softc *sc, const uint8_t *enaddr)
1486{
1487  static const int lo_shift[4] = { 4, 3, 2, 0 };
1488  static const int hi_shift[4] = { 4, 5, 6, 8 };
1489  uint32_t hash;
1490
1491  hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) |
1492            (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]);
1493
1494  return (hash & 0xfff);
1495}
1496
1497/*
1498 * wm_set_filter: Set up the receive filter.
1499 */
1500static void wm_set_filter(struct wm_softc *sc)
1501{
1502  struct ifnet *ifp = &sc->arpcom.ac_if;
1503  struct ether_multi *enm;
1504  struct ether_multistep step;
1505  uint32_t mta_reg;
1506  uint32_t hash, reg, bit;
1507  int i;
1508
1509#ifdef WM_DEBUG
1510  printk("wm_set_filter(");
1511#endif 
1512  mta_reg = WMREG_CORDOVA_MTA;
1513  sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE);
1514
1515  if (ifp->if_flags & IFF_BROADCAST)
1516     sc->sc_rctl |= RCTL_BAM;
1517  if (ifp->if_flags & IFF_PROMISC) {
1518     sc->sc_rctl |= RCTL_UPE;
1519     goto allmulti;
1520  }
1521
1522  /*
1523   * Set the station address in the first RAL slot, and
1524   * clear the remaining slots.
1525   */
1526  wm_set_ral(sc, sc->arpcom.ac_enaddr, 0);
1527  for (i = 1; i < WM_RAL_TABSIZE; i++)
1528      wm_set_ral(sc, NULL, i);
1529
1530  /* Clear out the multicast table. */
1531  for (i = 0; i < WM_MC_TABSIZE; i++)
1532      CSR_WRITE(sc,mta_reg + (i << 2), 0);
1533
1534  ETHER_FIRST_MULTI(step, &sc->arpcom, enm);
1535  while (enm != NULL) {
1536        if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
1537            /*
1538             * We must listen to a range of multicast addresses.
1539             * For now, just accept all multicasts, rather than
1540             * trying to set only those filter bits needed to match
1541             * the range.  (At this time, the only use of address
1542             * ranges is for IP multicast routing, for which the
1543             * range is big enough to require all bits set.)
1544             */
1545            goto allmulti;
1546         }
1547
1548         hash = wm_mchash(sc, enm->enm_addrlo);
1549
1550         reg = (hash >> 5) & 0x7f;
1551         bit = hash & 0x1f;
1552
1553         hash = CSR_READ(sc,mta_reg + (reg << 2));
1554         hash |= 1U << bit;
1555
1556         /* XXX Hardware bug?? */
1557         if ((reg & 0xe) == 1) {
1558            bit = CSR_READ(sc,mta_reg + ((reg - 1) << 2));
1559            CSR_WRITE(sc,mta_reg + (reg << 2), hash);
1560            CSR_WRITE(sc,mta_reg + ((reg - 1) << 2), bit);
1561         } else
1562            CSR_WRITE(sc,mta_reg + (reg << 2), hash);
1563
1564         ETHER_NEXT_MULTI(step, enm);
1565  }
1566
1567  ifp->if_flags &= ~IFF_ALLMULTI;
1568  goto setit;
1569
1570 allmulti:
1571  ifp->if_flags |= IFF_ALLMULTI;
1572  sc->sc_rctl |= RCTL_MPE;
1573
1574 setit:
1575  CSR_WRITE(sc,WMREG_RCTL, sc->sc_rctl);
1576
1577#ifdef WM_DEBUG
1578  printk("RCTL 0x%x)\n", CSR_READ(sc,WMREG_RCTL));
1579#endif 
1580}
1581
1582static void i82544EI_error(struct wm_softc *sc)
1583{
1584  struct ifnet          *ifp = &sc->arpcom.ac_if;
1585  unsigned long         intr_status= sc->if_errsts[sc->if_err_ptr1];
1586
1587  /* read and reset the status; because this is written
1588   * by the ISR, we must disable interrupts here
1589   */
1590  if (intr_status) {
1591    printk("Error %s%d:", ifp->if_name, ifp->if_unit);
1592    if (intr_status & ICR_RXSEQ) {
1593       printk("Rxq framing error (ICR= %x), if_ierrors %d\n",
1594              intr_status, ifp->if_ierrors);
1595    }
1596  }
1597  else 
1598    printk("%s%d: Ghost interrupt ?\n",ifp->if_name,ifp->if_unit);
1599  sc->if_errsts[sc->if_err_ptr1]=0; 
1600  if ((++sc->if_err_ptr1)==IF_ERR_BUFSZE) sc->if_err_ptr1=0; /* Till Straumann */
1601}
1602
1603void i82544EI_printStats()
1604{
1605  i82544EI_stats(root_i82544EI_dev);
1606}
1607
1608/* The daemon does all of the work; RX, TX and cleaning up buffers/descriptors */
1609static void i82544EI_daemon(void *arg)
1610{
1611  struct wm_softc *sc = (struct wm_softc*)arg;
1612  rtems_event_set       events;
1613  struct mbuf   *m=0;
1614  struct ifnet  *ifp=&sc->arpcom.ac_if;
1615
1616#ifdef WM_DEBUG
1617  printk("i82544EI_daemon()\n");
1618#endif
1619
1620  /* NOTE: our creator possibly holds the bsdnet_semaphore.
1621   *       since that has PRIORITY_INVERSION enabled, our
1622   *       subsequent call to bsdnet_event_receive() will
1623   *       _not_ release it. It's still in posession of our
1624   *       owner.
1625   *       This is different from how killing this task
1626   *       is handled.
1627   */
1628
1629  for (;;) {
1630     /* sleep until there's work to be done */
1631     /* Note: bsdnet_event_receive() acquires
1632      *       the global bsdnet semaphore for
1633      *       mutual exclusion.
1634      */
1635     rtems_bsdnet_event_receive(ALL_EVENTS,
1636                                RTEMS_WAIT | RTEMS_EVENT_ANY,
1637                                RTEMS_NO_TIMEOUT,
1638                                &events);
1639     if (KILL_EVENT & events)  break;
1640
1641     if (events & RX_EVENT)  i82544EI_rx(sc); /* in ISR instead */
1642
1643     /* clean up and try sending packets */
1644     do { 
1645        i82544EI_txq_done(sc);
1646
1647        while (sc->txq_free>0) {
1648           if (sc->txq_free>TXQ_HiLmt_OFF) {
1649              m=0;
1650              IF_DEQUEUE(&ifp->if_snd,m);
1651              if (m==0) break;
1652              i82544EI_sendpacket(sc, m); 
1653           }
1654           else {
1655              i82544EI_txq_done(sc);
1656              break;
1657           }
1658        }
1659         /* we leave this loop
1660          *  - either because there's no free buffer
1661          *    (m=0 initializer && !sc->txq_free)
1662          *  - or there's nothing to send (IF_DEQUEUE
1663          *    returned 0
1664          */
1665     } while (m);
1666
1667     ifp->if_flags &= ~IFF_OACTIVE;
1668
1669     /* Log errors and other uncommon events. */
1670     if (events & ERR_EVENT) i82544EI_error(sc); 
1671     /* Rx overrun */
1672     if ( events & INIT_EVENT) {
1673        printk("Warnning, Rx overrun.  Make sure the old mbuf was free\n");
1674        i82544EI_ifinit(arg);
1675     }
1676
1677  } /* end for(;;) { rtems_bsdnet_event_receive() .....*/
1678
1679  printf("out of daemon\n");
1680  ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
1681
1682  /* shut down the hardware */
1683  i82544EI_stop_hw(sc);
1684  /* flush the output queue */
1685  for (;;) {
1686      IF_DEQUEUE(&ifp->if_snd,m);
1687      if (!m) break;
1688      m_freem(m);
1689  }
1690  /* as of 'rtems_bsdnet_event_receive()' we own the
1691   * networking semaphore
1692   */
1693  rtems_bsdnet_semaphore_release();
1694  rtems_semaphore_release(sc->daemonSync);
1695
1696  /* Note that I dont use sc->daemonTid here -
1697   * theoretically, that variable could already
1698   * hold a newly created TID
1699   */
1700  rtems_task_delete(RTEMS_SELF);
1701}
1702
1703/*
1704 * wm_gmii_reset:
1705 *
1706 *      Reset the PHY.
1707 */
1708static void wm_gmii_reset(struct wm_softc *sc)
1709{
1710
1711  CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET);
1712  rtems_bsp_delay(20000);
1713
1714  CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
1715  rtems_bsp_delay(20000);
1716
1717}
1718
1719/*
1720 * wm_gmii_mediainit:
1721 *
1722 *      Initialize media for use on 1000BASE-T devices.
1723 */
1724static void wm_gmii_mediainit(struct wm_softc *sc)
1725{
1726  /*  struct ifnet *ifp = &sc->arpcom.ac_if;*/
1727
1728  /* We have MII. */
1729  sc->sc_flags |= WM_F_HAS_MII;
1730
1731#if 1
1732  /* <skf> May 2009 : The value that should be programmed into IPGT is 10 */
1733  sc->sc_tipg = TIPG_IPGT(10)+TIPG_IPGR1(8)+TIPG_IPGR2(6); 
1734#else
1735  sc->sc_tipg = TIPG_1000T_DFLT; /* 0x602008 */
1736#endif
1737
1738  /*
1739   * Let the chip set speed/duplex on its own based on
1740   * signals from the PHY.
1741   * XXXbouyer - I'm not sure this is right for the 80003,
1742   * the em driver only sets CTRL_SLU here - but it seems to work.
1743   */
1744  sc->sc_ctrl |= CTRL_SLU;
1745  CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
1746
1747  wm_gmii_reset(sc);
1748
1749#if 0
1750  /* Initialize our media structures and probe the GMII. */
1751  sc->sc_mii.mii_ifp = ifp;
1752
1753  sc->sc_mii.mii_readreg = wm_gmii_i82544_readreg;
1754  sc->sc_mii.mii_writereg = wm_gmii_i82544_writereg;
1755  sc->sc_mii.mii_statchg = wm_gmii_statchg;
1756
1757  ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_gmii_mediachange,
1758            wm_gmii_mediastatus);
1759
1760  mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
1761            MII_OFFSET_ANY, MIIF_DOPAUSE);
1762  if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
1763     ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
1764     ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE);
1765  } else
1766      ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
1767#endif
1768}
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