source: rtems/c/src/lib/libbsp/powerpc/mvme5500/network/if_1GHz/if_wm.c @ 787f51f

5
Last change on this file since 787f51f was 787f51f, checked in by Sebastian Huber <sebastian.huber@…>, on 06/06/17 at 09:08:16

Do not include <sys/ioctl.h> in kernel-space

Update #2833.

  • Property mode set to 100644
File size: 48.6 KB
Line 
1/*
2 * Copyright (c) 2004,2005 RTEMS/Mvme5500 port by S. Kate Feng <feng1@bnl.gov>
3 *      under the Deaprtment of Energy contract DE-AC02-98CH10886
4 *      Brookhaven National Laboratory, All rights reserved
5 *
6 * Acknowledgements:
7 * netBSD : Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
8 *          Jason R. Thorpe for Wasabi Systems, Inc.
9 * Intel : NDA document
10 *
11 * Some notes from the author, S. Kate Feng :
12 *
13 * 1) The error reporting routine i82544EI_error() employs two pointers
14 *    for the error report buffer. One for the ISR and another one for
15 *    the error report.
16 * 2) Enable the hardware Auto-Negotiation state machine.
17 * 3) Set Big Endian mode in the WMREG_CTRL so that we do not need htole32
18 *    because PPC is big endian mode.
19 *    However, the data packet structure defined in if_wmreg.h
20 *    should be redefined for the big endian mode.
21 * 4) To ensure the cache coherence, the MOTLoad had the PCI
22 *    snoop control registers (0x1f00) set to "snoop to WB region" for
23 *    the entire 512MB of memory.
24 * 5) MOTLoad default :
25 *    little endian mode, cache line size is 32 bytes, no checksum control,
26 *    hardware auto-neg. state machine disabled. PCI control "snoop
27 *    to WB region", MII mode (PHY) instead of TBI mode.
28 * 6) We currently only use 32-bit (instead of 64-bit) DMA addressing.
29 * 7) Implementation for Jumbo Frame and TCP checksum is not completed yet.
30 *
31 */
32
33#define BYTE_ORDER BIG_ENDIAN
34
35#define INET
36
37/*#define RTEMS_ETHERMTU_JUMBO*/
38
39#include <rtems.h>
40#include <rtems/bspIo.h>      /* printk */
41
42#include <inttypes.h>
43#include <stdio.h>            /* printf for statistics */
44#include <string.h>
45
46#include <libcpu/io.h>        /* inp & friends */
47#include <libcpu/spr.h>       /* registers.h is included here */
48#include <bsp.h>
49
50#include <sys/param.h>
51#include <sys/systm.h>
52#include <sys/mbuf.h>
53
54#include <rtems/rtems_bsdnet.h>
55#include <rtems/rtems_bsdnet_internal.h>
56#include <rtems/error.h>
57#include <errno.h>
58
59#include <rtems/rtems/types.h>
60#include <rtems/score/cpu.h>
61
62/* #include <sys/queue.h> */
63
64#include <sys/socket.h>
65#include <sys/sockio.h>             /* SIOCADDMULTI, SIOC...     */
66#include <net/if.h>
67#include <net/if_dl.h>
68#include <netinet/in.h>
69#include <netinet/if_ether.h>
70#include <net/ethernet.h>
71
72#ifdef INET
73#include <netinet/in_var.h>
74#endif
75
76#include <bsp/irq.h>
77#include <bsp/pci.h>
78#include <bsp/pcireg.h>
79#include <bsp/if_wmreg.h>
80
81extern int pci_mem_find(int b, int d, int f, int reg, unsigned *basep,unsigned *sizep);
82
83#define WMREG_RADV      0x282c  /* Receive Interrupt Absolute Delay Timer */
84
85#define ETHERTYPE_FLOWCONTROL   0x8808  /* 802.3x flow control packet */
86
87#define i82544EI_TASK_NAME "IGHz"
88#define SOFTC_ALIGN        4095
89
90#define IF_ERR_BUFSZE        16
91
92/*#define WM_DEBUG*/
93#ifdef WM_DEBUG
94#define WM_DEBUG_LINK           0x01
95#define WM_DEBUG_TX             0x02
96#define WM_DEBUG_RX             0x04
97#define WM_DEBUG_GMII           0x08
98static int      wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK; /* May 7, 2009 */
99
100#define DPRINTF(x, y)   if (wm_debug & (x)) printk y
101#else
102#define DPRINTF(x, y)   /* nothing */
103#endif /* WM_DEBUG */
104
105/* RTEMS event to kill the daemon */
106#define KILL_EVENT              RTEMS_EVENT_1
107/* RTEMS event to (re)start the transmitter */
108#define START_TRANSMIT_EVENT    RTEMS_EVENT_2
109/* RTEMS events used by the ISR */
110#define RX_EVENT                RTEMS_EVENT_3
111#define TX_EVENT                RTEMS_EVENT_4
112#define ERR_EVENT               RTEMS_EVENT_5
113#define INIT_EVENT              RTEMS_EVENT_6
114
115#define ALL_EVENTS (KILL_EVENT|START_TRANSMIT_EVENT|RX_EVENT|TX_EVENT|ERR_EVENT|INIT_EVENT)
116
117/* <skf> used 64 in 4.8.0, TOD; try 4096 */
118#define NTXDESC                 256
119#define NTXDESC_MASK            (NTXDESC - 1)
120#define WM_NEXTTX(x)            (((x) + 1) & NTXDESC_MASK)
121
122#define NRXDESC                 256
123#define NRXDESC_MASK            (NRXDESC - 1)
124#define WM_NEXTRX(x)            (((x) + 1) & NRXDESC_MASK)
125#define WM_PREVRX(x)            (((x) - 1) & NRXDESC_MASK)
126
127#define WM_CDOFF(x)     offsetof(struct wm_control_data, x)
128#define WM_CDTXOFF(x)   WM_CDOFF(sc_txdescs[(x)])
129#define WM_CDRXOFF(x)   WM_CDOFF(sc_rxdescs[(x)])
130
131#define TXQ_HiLmt_OFF 32
132
133static uint32_t TxDescCmd;
134static unsigned BSP_1GHz_membase;
135
136/*
137 * Software state per device.
138 */
139struct wm_softc {
140        wiseman_txdesc_t sc_txdescs[NTXDESC]; /* transmit descriptor memory */
141        wiseman_rxdesc_t sc_rxdescs[NRXDESC]; /* receive descriptor memory */
142        struct mbuf *txs_mbuf[NTXDESC];        /* transmit buffer memory */
143        struct mbuf *rxs_mbuf[NRXDESC];        /* receive buffer memory */
144        struct wm_softc *next_module;
145        volatile unsigned int if_errsts[IF_ERR_BUFSZE]; /* intr_status */
146        unsigned int if_err_ptr1;     /* ptr used in i82544EI_error() */
147        unsigned int if_err_ptr2;     /* ptr used in ISR */
148        int txs_firstdesc;              /* first descriptor in packet */
149        int txs_lastdesc;               /* last descriptor in packet */
150        int txs_ndesc;                  /* # of descriptors used */
151        unsigned sc_membase;            /* Memory space base address */
152        unsigned sc_memsize;            /* Memory space size */
153
154        char    dv_xname[16];           /* external name (name + unit) */
155        void *sc_sdhook;                /* shutdown hook */
156        struct arpcom arpcom;           /* rtems if structure, contains ifnet */
157        int sc_flags;                   /* flags; see below */
158        int sc_bus_speed;               /* PCI/PCIX bus speed */
159        int sc_flowflags;               /* 802.3x flow control flags */
160
161        void *sc_ih;                    /* interrupt cookie */
162
163        int sc_ee_addrbits;             /* EEPROM address bits */
164        rtems_id        daemonTid;
165        rtems_id        daemonSync;     /* synchronization with the daemon */
166
167        int      txq_next;              /* next Tx descriptor ready for transmitting */
168        uint32_t txq_nactive;           /* number of active TX descriptors */
169        uint32_t txq_fi;                /* next free Tx descriptor */
170        uint32_t txq_free;              /* number of free Tx jobs */
171        uint32_t sc_txctx_ipcs;         /* cached Tx IP cksum ctx */
172        uint32_t sc_txctx_tucs;         /* cached Tx TCP/UDP cksum ctx */
173
174        int     sc_rxptr;               /* next ready Rx descriptor/queue ent */
175        int     sc_rxdiscard;
176        int     sc_rxlen;
177
178        uint32_t sc_ctrl;               /* prototype CTRL register */
179        uint32_t sc_ctrl_ext;           /* prototype CTRL_EXT register */
180
181        uint32_t sc_icr;                /* prototype interrupt bits */
182        uint32_t sc_tctl;               /* prototype TCTL register */
183        uint32_t sc_rctl;               /* prototype RCTL register */
184        uint32_t sc_tipg;               /* prototype TIPG register */
185        uint32_t sc_fcrtl;              /* prototype FCRTL register */
186        uint32_t sc_pba;                /* prototype PBA register */
187
188        int sc_mchash_type;             /* multicast filter offset */
189
190        /* statistics */
191        struct {
192          volatile unsigned long     rxInterrupts;
193          volatile unsigned long     txInterrupts;
194          unsigned long     linkInterrupts;
195          unsigned long     length_errors;
196          unsigned long     frame_errors;
197          unsigned long     crc_errors;
198          unsigned long     rxOvrRunInterrupts; /* Rx overrun interrupt */
199          unsigned long     rxSeqErr;
200          unsigned long     rxC_ordered;
201          unsigned long     ghostInterrupts;
202          unsigned long     linkStatusChng;
203        } stats;
204};
205
206/* <skf> our memory address seen from the PCI bus should be 1:1 */
207#define htole32(x)  le32toh(x)
208#define le32toh(x)  CPU_swap_u32((unsigned int) x)
209#define le16toh(x)  CPU_swap_u16(x)
210
211/* sc_flags */
212#define WM_F_HAS_MII            0x01    /* has MII */
213/* 82544 EI does not perform EEPROM handshake, EEPROM interface is not SPI */
214#define WM_F_EEPROM_HANDSHAKE   0x02    /* requires EEPROM handshake */
215#define WM_F_EEPROM_SPI         0x04    /* EEPROM is SPI */
216#define WM_F_IOH_VALID          0x10    /* I/O handle is valid */
217#define WM_F_BUS64              0x20    /* bus is 64-bit */
218#define WM_F_PCIX               0x40    /* bus is PCI-X */
219
220#define CSR_READ(sc,reg) in_le32((volatile uint32_t *)(sc->sc_membase+reg))
221#define CSR_WRITE(sc,reg,val) out_le32((volatile uint32_t *)(sc->sc_membase+reg), val)
222
223#define WM_CDTXADDR(sc) ( (uint32_t) &sc->sc_txdescs[0] )
224#define WM_CDRXADDR(sc) ( (uint32_t) &sc->sc_rxdescs[0] )
225
226static struct wm_softc *root_i82544EI_dev = NULL;
227
228static void i82544EI_ifstart(struct ifnet *ifp);
229static int  wm_ioctl(struct ifnet *ifp, ioctl_command_t cmd,caddr_t data);
230static void i82544EI_ifinit(void *arg);
231static void wm_stop(struct ifnet *ifp, int disable);
232static void wm_gmii_mediainit(struct wm_softc *sc);
233
234static void wm_rxdrain(struct wm_softc *sc);
235static int  wm_add_rxbuf(struct wm_softc *sc, int idx);
236static int  wm_read_eeprom(struct wm_softc *sc,int word,int wordcnt, uint16_t *data);
237static void i82544EI_daemon(void *arg);
238static void wm_set_filter(struct wm_softc *sc);
239static void i82544EI_rx(struct wm_softc *sc);
240static void i82544EI_isr(rtems_irq_hdl_param handle);
241static void i82544EI_sendpacket(struct wm_softc *sc, struct mbuf *m);
242
243static void i82544EI_irq_on(const rtems_irq_connect_data *irq)
244{
245  struct wm_softc *sc;
246  unsigned int irqMask=  ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | ICR_RXO | ICR_RXT0 | ICR_RXCFG;
247
248  for (sc= root_i82544EI_dev; sc; sc= sc-> next_module) {
249    CSR_WRITE(sc,WMREG_IMS,(CSR_READ(sc,WMREG_IMS)| irqMask) );
250    return;
251  }
252}
253
254static void i82544EI_irq_off(const rtems_irq_connect_data *irq)
255{
256  struct wm_softc *sc;
257  unsigned int irqMask=  ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | ICR_RXO | ICR_RXT0 |ICR_RXCFG ;
258
259  for (sc= root_i82544EI_dev; sc; sc= sc-> next_module) {
260    CSR_WRITE(sc,WMREG_IMS, (CSR_READ(sc,WMREG_IMS) & ~irqMask) );
261    return;
262  }
263}
264
265static int i82544EI_irq_is_on(const rtems_irq_connect_data *irq)
266{
267  return(CSR_READ(root_i82544EI_dev,WMREG_ICR) & root_i82544EI_dev->sc_icr);
268}
269
270static rtems_irq_connect_data i82544IrqData={
271        BSP_GPP_82544_IRQ,
272        (rtems_irq_hdl) i82544EI_isr,
273        (rtems_irq_hdl_param) NULL,
274        (rtems_irq_enable) i82544EI_irq_on,
275        (rtems_irq_disable) i82544EI_irq_off,
276        (rtems_irq_is_enabled) i82544EI_irq_is_on,
277};
278
279int rtems_i82544EI_driver_attach(struct rtems_bsdnet_ifconfig *config, int attach)
280{
281  struct wm_softc *sc;
282  struct ifnet *ifp;
283  uint8_t enaddr[ETHER_ADDR_LEN];
284  uint16_t myea[ETHER_ADDR_LEN / 2], cfg1, cfg2, swdpin;
285  unsigned reg;
286  int b,d,f; /* PCI bus/device/function */
287  int unit;
288  void     *softc_mem;
289  char     *name;
290
291  unit = rtems_bsdnet_parse_driver_name(config, &name);
292  if (unit < 0) return 0;
293
294  if ( !strncmp((const char *)name,"autoz",5))
295     memcpy(name,"gtGHz",5);
296
297  printk("\nAttaching MVME5500 1GHz NIC%d\n", unit);
298  printk("RTEMS-mvme5500 BSP Copyright (c) 2004,2005,2008, Brookhaven National Lab., Shuchen Kate Feng \n");
299
300  /* Make sure certain elements e.g. descriptor lists are aligned.*/
301  softc_mem = rtems_bsdnet_malloc(sizeof(*sc) + SOFTC_ALIGN, M_FREE, M_NOWAIT);
302
303  /* Check for the very unlikely case of no memory. */
304  if (softc_mem == NULL)
305     rtems_panic("i82544EI: OUT OF MEMORY");
306
307  sc = (void *)(((long)softc_mem + SOFTC_ALIGN) & ~SOFTC_ALIGN);
308  memset(sc, 0, sizeof(*sc));
309
310  sprintf(sc->dv_xname, "%s%d", name, unit);
311
312  if (pci_find_device(PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_82544EI_COPPER,
313                        unit-1,&b, &d, &f))
314    rtems_panic("i82544EI device ID not found\n");
315
316#ifdef WM_DEBUG
317  printk("82544EI:b%d, d%d, f%d\n", b, d,f);
318#endif
319
320  /* Memory-mapped acccess is required for normal operation.*/
321  if ( pci_mem_find(b,d,f,PCI_MAPREG_START, &sc->sc_membase, &sc->sc_memsize))
322     rtems_panic("i82544EI: unable to map memory space\n");
323
324#ifdef WM_DEBUG
325  printk("Memory base addr 0x%x\n", sc->sc_membase);
326#endif
327  BSP_1GHz_membase= sc->sc_membase;
328
329#ifdef WM_DEBUG
330  printk("Memory base addr 0x%x\n", sc->sc_membase);
331  printk("txdesc[0] addr:0x%x, rxdesc[0] addr:0x%x, sizeof sc %d\n",&sc->sc_txdescs[0], &sc->sc_rxdescs[0], sizeof(*sc));
332#endif
333
334
335  sc->sc_ctrl=CSR_READ(sc,WMREG_CTRL);
336  /*
337   * Determine a few things about the bus we're connected to.
338   */
339  reg = CSR_READ(sc,WMREG_STATUS);
340  if (reg & STATUS_BUS64) sc->sc_flags |= WM_F_BUS64;
341  sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33;
342#ifdef WM_DEBUG
343  printk("%s%d: %d-bit %dMHz PCI bus\n",name, unit,
344         (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed);
345#endif
346
347  /*
348   * Setup some information about the EEPROM.
349   */
350
351  sc->sc_ee_addrbits = 6;
352
353#ifdef WM_DEBUG
354  printk("%s%d: %u word (%d address bits) MicroWire EEPROM\n",
355            name, unit, 1U << sc->sc_ee_addrbits,
356            sc->sc_ee_addrbits);
357#endif
358
359  /*
360   * Read the Ethernet address from the EEPROM.
361   */
362  if (wm_read_eeprom(sc, EEPROM_OFF_MACADDR,
363            sizeof(myea) / sizeof(myea[0]), myea))
364     rtems_panic("i82544ei 1GHZ ethernet: unable to read Ethernet address");
365
366  enaddr[0] = myea[0] & 0xff;
367  enaddr[1] = myea[0] >> 8;
368  enaddr[2] = myea[1] & 0xff;
369  enaddr[3] = myea[1] >> 8;
370  enaddr[4] = myea[2] & 0xff;
371  enaddr[5] = myea[2] >> 8;
372
373  memcpy(sc->arpcom.ac_enaddr, enaddr, ETHER_ADDR_LEN);
374#ifdef WM_DEBUG
375  printk("%s: Ethernet address %s\n", sc->dv_xname,
376            ether_sprintf(enaddr));
377#endif
378
379  /*
380   * Read the config info from the EEPROM, and set up various
381   * bits in the control registers based on their contents.
382   */
383  if (wm_read_eeprom(sc, EEPROM_OFF_CFG1, 1, &cfg1)) {
384     printk("%s: unable to read CFG1 from EEPROM\n",sc->dv_xname);
385     return(0);
386  }
387  if (wm_read_eeprom(sc, EEPROM_OFF_CFG2, 1, &cfg2)) {
388     printk("%s: unable to read CFG2 from EEPROM\n",sc->dv_xname);
389     return(0);
390  }
391  if (wm_read_eeprom(sc, EEPROM_OFF_SWDPIN, 1, &swdpin)) {
392     printk("%s: unable to read SWDPIN from EEPROM\n",sc->dv_xname);
393     return(0);
394  }
395
396  if (cfg1 & EEPROM_CFG1_ILOS) sc->sc_ctrl |= CTRL_ILOS;
397  sc->sc_ctrl|=((swdpin >> EEPROM_SWDPIN_SWDPIO_SHIFT) & 0xf) <<
398                CTRL_SWDPIO_SHIFT;
399  sc->sc_ctrl |= ((swdpin >> EEPROM_SWDPIN_SWDPIN_SHIFT) & 0xf) <<
400                CTRL_SWDPINS_SHIFT;
401
402  CSR_WRITE(sc,WMREG_CTRL, sc->sc_ctrl);
403#if 0
404  CSR_WRITE(sc,WMREG_CTRL_EXT, sc->sc_ctrl_ext);
405#endif
406
407  /*
408   * Determine if we're TBI or GMII mode, and initialize the
409   * media structures accordingly.
410   */
411  if ((CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) {
412    /* 1000BASE-X : fiber  (TBI mode)
413       wm_tbi_mediainit(sc); */
414  } else {   /* 1000BASE-T : copper (internal PHY mode), for the mvme5500 */
415           wm_gmii_mediainit(sc);
416  }
417
418  ifp = &sc->arpcom.ac_if;
419  /* set this interface's name and unit */
420  ifp->if_unit = unit;
421  ifp->if_name = name;
422  ifp->if_softc = sc;
423  ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
424#ifdef RTEMS_ETHERMTU_JUMBO
425  sc->arpcom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
426  ifp->if_mtu = config->mtu ? config->mtu : ETHERMTU_JUMBO;
427#else
428  ifp->if_mtu = config->mtu ? config->mtu : ETHERMTU;
429#endif
430#ifdef RTEMS_CKSUM_OFFLOAD
431  /* < skf> The following is really not related to jumbo frame
432  sc->arpcom.ec_capabilities |= ETHERCAP_VLAN_MTU;*/
433  ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
434                    IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
435                    IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx |
436                    IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx |
437                    IFCAP_TSOv4;  /* TCP segmentation offload. */
438#endif
439
440  ifp->if_ioctl = wm_ioctl;
441  ifp->if_start = i82544EI_ifstart;
442  /*  ifp->if_watchdog = wm_watchdog;*/
443  ifp->if_init = i82544EI_ifinit;
444  if (ifp->if_snd.ifq_maxlen == 0)
445      ifp->if_snd.ifq_maxlen = ifqmaxlen;
446
447  ifp->if_output = ether_output;
448
449  /* create the synchronization semaphore */
450  if (RTEMS_SUCCESSFUL != rtems_semaphore_create(
451     rtems_build_name('I','G','H','Z'),0,0,0,&sc->daemonSync))
452     rtems_panic("i82544EI: semaphore creation failed");
453
454  i82544IrqData.handle= (rtems_irq_hdl_param) sc;
455  /* sc->next_module = root_i82544EI_dev;*/
456  root_i82544EI_dev = sc;
457
458  /* Attach the interface. */
459  if_attach(ifp);
460  ether_ifattach(ifp);
461#ifdef WM_DEBUG
462  printk("82544EI: Ethernet driver has been attached (handle 0x%08x,ifp 0x%08x)\n",sc, ifp);
463#endif
464
465  return(1);
466}
467
468/*
469 * wm_reset:
470 *
471 *      Reset the i82544 chip.
472 */
473static void wm_reset(struct wm_softc *sc)
474{
475  int i;
476
477 /* Packet Buffer Allocation (PBA)
478  * Writing PBA sets the receive portion of the buffer.
479  * the remainder is used for the transmit buffer.
480  *
481  * 82544 has a Packet Buffer of 64K.
482  * Default allocation : PBA=40K for Rx, leaving 24K for Tx.
483  * Default for jumbo: PBA=48K for Rx, leaving 16K for Tx.
484  */
485  sc->sc_pba = sc->arpcom.ac_if.if_mtu > 8192 ? PBA_40K : PBA_48K;
486  CSR_WRITE(sc, WMREG_PBA, sc->sc_pba);
487
488  /* device reset */
489  CSR_WRITE(sc, WMREG_CTRL, CTRL_RST);
490  rtems_bsp_delay(10000);
491
492  for (i = 0; i < 1000; i++) {
493      if ((CSR_READ(sc, WMREG_CTRL) & CTRL_RST) == 0)
494        break;
495      rtems_bsp_delay(20);
496  }
497  if (CSR_READ(sc, WMREG_CTRL) & CTRL_RST)
498      printk("Intel 82544 1GHz reset failed to complete\n");
499
500  sc->sc_ctrl_ext = CSR_READ(sc,WMREG_CTRL_EXT);
501  sc->sc_ctrl_ext |= CTRL_EXT_EE_RST;
502  CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext);
503  CSR_READ(sc, WMREG_STATUS);
504  /* Wait for EEPROM reload */
505  rtems_bsp_delay(2000);
506  sc->sc_ctrl= CSR_READ(sc, WMREG_CTRL);
507}
508
509/*
510 * i82544EI_ifstart:            [ifnet interface function]
511 *
512 *      Start packet transmission on the interface.
513 */
514static void
515i82544EI_ifstart(struct ifnet *ifp)
516{
517  struct wm_softc *sc = ifp->if_softc;
518
519#ifdef WM_DEBUG
520  printk("i82544EI_ifstart(");
521#endif
522
523  if ((ifp->if_flags & IFF_RUNNING) == 0) {
524#ifdef WM_DEBUG
525     printk("IFF_RUNNING==0\n");
526#endif
527     return;
528  }
529
530  ifp->if_flags |= IFF_OACTIVE;
531  rtems_bsdnet_event_send (sc->daemonTid, START_TRANSMIT_EVENT);
532#ifdef WM_DEBUG
533  printk(")\n");
534#endif
535}
536
537static void i82544EI_stats(struct wm_softc *sc)
538{
539  struct ifnet *ifp = &sc->arpcom.ac_if;
540
541  printf("    Ghost Interrupts:%-8lu\n", sc->stats.ghostInterrupts);
542  printf("       Rx Interrupts:%-8lu\n", sc->stats.rxInterrupts);
543  printf("     Receive Packets:%-8u\n", (unsigned)CSR_READ(sc,WMREG_GPRC));
544  printf("     Receive Overrun:%-8lu\n", sc->stats.rxOvrRunInterrupts);
545  printf("     Receive  errors:%-8u\n", (unsigned)CSR_READ(sc,WMREG_RXERRC));
546  printf("   Rx sequence error:%-8lu\n", sc->stats.rxSeqErr);
547  printf("      Rx /C/ ordered:%-8lu\n", sc->stats.rxC_ordered);
548  printf("    Rx Length Errors:%-8u\n", (unsigned)CSR_READ(sc,WMREG_RLEC));
549  printf("       Tx Interrupts:%-8lu\n", sc->stats.txInterrupts);
550  printf("   Transmitt Packets:%-8u\n", (unsigned)CSR_READ(sc,WMREG_GPTC));
551  printf("   Transmitt  errors:%-8lu\n", ifp->if_oerrors);
552  printf("         Active Txqs:%-8lu\n", sc->txq_nactive);
553  printf("          collisions:%-8u\n", (unsigned)CSR_READ(sc,WMREG_COLC));
554  printf("          Crc Errors:%-8u\n", (unsigned)CSR_READ(sc,WMREG_CRCERRS));
555  printf("  Link Status Change:%-8lu\n", sc->stats.linkStatusChng);
556}
557
558/*
559 * wm_ioctl:            [ifnet interface function]
560 *
561 *      Handle control requests from the operator.
562 */
563static int wm_ioctl(struct ifnet *ifp, ioctl_command_t cmd,caddr_t data)
564{
565  struct wm_softc *sc = ifp->if_softc;
566  int error=0;
567
568  switch (cmd) {
569    default:
570      error = ether_ioctl(ifp, cmd, data);
571      if (error == ENETRESET) {
572          /*
573           * Multicast list has changed; set the hardware filter
574           * accordingly.
575           */
576          wm_set_filter(sc);
577          error = 0;
578      }
579      break;
580    case SIO_RTEMS_SHOW_STATS:
581      i82544EI_stats(sc);
582      break;
583  }
584
585  /* Try to get more packets going.*/
586  i82544EI_ifstart(ifp);
587  return (error);
588}
589
590/*
591 * wm_isr:
592 *
593 *      Interrupt service routine.
594 */
595static void i82544EI_isr(rtems_irq_hdl_param handle)
596{
597  volatile struct wm_softc *sc = (struct wm_softc *) handle;
598  uint32_t icr;
599  rtems_event_set  events=0;
600
601  /* Reading the WMREG_ICR clears the interrupt bits */
602  icr = CSR_READ(sc,WMREG_ICR);
603
604  if ( icr & (ICR_RXDMT0|ICR_RXT0)) {
605     sc->stats.rxInterrupts++;
606     events |= RX_EVENT;
607  }
608
609  if (icr & ICR_TXDW) {
610     sc->stats.txInterrupts++;
611     events |= TX_EVENT;
612  }
613  /* <SKF> Rx overrun : no available receive buffer
614   * or PCI receive bandwidth inadequate.
615   */
616  if (icr & ICR_RXO) {
617     sc->stats.rxOvrRunInterrupts++;
618     events |= INIT_EVENT;
619  }
620  if (icr & ICR_RXSEQ) /* framing error */ {
621     sc->if_errsts[sc->if_err_ptr2++]=icr;
622     if ( sc->if_err_ptr2 ==IF_ERR_BUFSZE) sc->if_err_ptr2=0;
623     events |= ERR_EVENT;
624     sc->stats.rxSeqErr++;
625  }
626  if ( !icr) sc->stats.ghostInterrupts++;
627
628  if (icr & ICR_LSC) sc->stats.linkStatusChng++;
629  if (icr & ICR_RXCFG) sc->stats.rxC_ordered++;
630
631  rtems_bsdnet_event_send(sc->daemonTid, events);
632}
633
634/*
635 * i82544EI_sendpacket:
636 *
637 *      Helper; handle transmit interrupts.
638 */
639static void i82544EI_sendpacket(struct wm_softc *sc, struct mbuf *m)
640{
641
642#ifdef WM_DEBUG_TX
643  printk("sendpacket(");
644#endif
645
646  if ( !(m->m_next)) { /* single buffer packet */
647    sc->txs_mbuf[sc->txq_next]= m;
648    /* Note: we currently only use 32-bit DMA addresses. */
649    sc->sc_txdescs[sc->txq_next].wtx_addr.wa_low = htole32(mtod(m, void*));
650    sc->sc_txdescs[sc->txq_next].wtx_cmdlen =htole32(TxDescCmd | m->m_len);
651    sc->txs_lastdesc= sc->txq_next;
652    sc->txq_next = WM_NEXTTX(sc->txq_next);
653    sc->txq_nactive++;
654    sc->txq_free--;
655  }
656  else /* multiple mbufs in this packet */
657  {
658    struct mbuf *mtp, *mdest;
659    volatile unsigned char *pt;
660    int len, y, loop=0;
661
662#ifdef WM_DEBUG_TX
663    printk("multi mbufs ");
664#endif
665    mtp = m;
666    while ( mtp) {
667      MGETHDR(mdest, M_WAIT, MT_DATA);
668      MCLGET(mdest, M_WAIT);
669      pt = (volatile unsigned char *)mdest->m_data;
670      for ( len=0;mtp;mtp=mtp->m_next) {
671        loop++;
672        /* Each descriptor gets a 2k (MCLBYTES) buffer, although
673         * the length of each descriptor can be up to 16288 bytes.
674         * For packets which fill more than one buffer ( >2k), we
675         * chain them together.
676         * <Kate Feng> : This effective for packets > 2K
677         * The other way is effective for packets < 2K
678         */
679        if ( ((y=(len+mtp->m_len)) > sizeof(union mcluster))) {
680          printk(" >%d, use next descriptor\n", sizeof(union mcluster));
681          break;
682        }
683        memcpy((void *)pt,(char *)mtp->m_data, mtp->m_len);
684        pt += mtp->m_len;
685        len += mtp->m_len;
686      } /* end for loop */
687      mdest->m_len=len;
688      sc->txs_mbuf[sc->txq_next] = mdest;
689      /* Note: we currently only use 32-bit DMA addresses. */
690      sc->sc_txdescs[sc->txq_next].wtx_addr.wa_low = htole32(mtod(mdest, void*));
691      sc->sc_txdescs[sc->txq_next].wtx_cmdlen = htole32(TxDescCmd|mdest->m_len);
692      sc->txs_lastdesc = sc->txq_next;
693      sc->txq_next = WM_NEXTTX(sc->txq_next);
694      sc->txq_nactive ++;
695      if (sc->txq_free)
696         sc->txq_free--;
697      else
698         rtems_panic("i8254EI : no more free descriptors");
699    } /* end for while */
700    /* free old mbuf chain */
701    m_freem(m);
702    m=0;
703  }  /* end  multiple mbufs */
704
705  DPRINTF(WM_DEBUG_TX,("%s: TX: desc %d: cmdlen 0x%08x\n", sc->dv_xname,
706         sc->txs_lastdesc, le32toh(sc->sc_txdescs[sc->txs_lastdesc].wtx_cmdlen)));
707  DPRINTF(WM_DEBUG_TX,("status 0x%08x\n",sc->sc_txdescs[sc->txq_fi].wtx_fields.wtxu_status));
708
709  memBar();
710
711  /* This is the location where software writes the first NEW descriptor */
712  CSR_WRITE(sc,WMREG_TDT, sc->txq_next);
713
714  DPRINTF(WM_DEBUG_TX,("%s: addr 0x%08x, TX: TDH %d, TDT %d\n",sc->dv_xname,
715  le32toh(sc->sc_txdescs[sc->txs_lastdesc].wtx_addr.wa_low), CSR_READ(sc,WMREG_TDH),
716          CSR_READ(sc,WMREG_TDT)));
717
718  DPRINTF(WM_DEBUG_TX,("%s: TX: finished transmitting packet, job %d\n",
719                    sc->dv_xname, sc->txq_next));
720
721}
722
723static void i82544EI_txq_free(struct wm_softc *sc, uint8_t status)
724{
725  struct ifnet *ifp = &sc->arpcom.ac_if;
726
727  /* We might use the statistics registers instead of variables
728   * to keep tack of the network statistics
729   */
730
731  /* statistics */
732  ifp->if_opackets++;
733
734  if (status & (WTX_ST_EC|WTX_ST_LC)) {
735       ifp->if_oerrors++;
736
737     if (status & WTX_ST_LC)
738        printf("%s: late collision\n", sc->dv_xname);
739     else if (status & WTX_ST_EC) {
740        ifp->if_collisions += 16;
741         printf("%s: excessive collisions\n", sc->dv_xname);
742     }
743  }
744  /* Free the original mbuf chain */
745  m_freem(sc->txs_mbuf[sc->txq_fi]);
746  sc->txs_mbuf[sc->txq_fi] = 0;
747  sc->sc_txdescs[sc->txq_fi].wtx_fields.wtxu_status=0;
748
749  sc->txq_free ++;
750  sc->txq_fi = WM_NEXTTX(sc->txq_fi);
751  --sc->txq_nactive;
752}
753
754static void i82544EI_txq_done(struct wm_softc *sc)
755{
756  uint8_t status;
757
758  /*
759   * Go through the Tx list and free mbufs for those
760   * frames which have been transmitted.
761   */
762  while ( sc->txq_nactive > 0) {
763    status = sc->sc_txdescs[sc->txq_fi].wtx_fields.wtxu_status;
764    if ((status & WTX_ST_DD) == 0) break;
765    i82544EI_txq_free(sc, status);
766    DPRINTF(WM_DEBUG_TX,("%s: TX: job %d done\n",
767                    sc->dv_xname, sc->txq_fi));
768  }
769}
770
771static void wm_init_rxdesc(struct wm_softc *sc, int x)
772{
773  wiseman_rxdesc_t *__rxd = &(sc)->sc_rxdescs[(x)];
774  struct mbuf *m;
775
776  m = sc->rxs_mbuf[x];
777
778  __rxd->wrx_addr.wa_low=htole32(mtod(m, void*));
779  __rxd->wrx_addr.wa_high = 0;
780  __rxd->wrx_len = 0;
781  __rxd->wrx_cksum = 0;
782  __rxd->wrx_status = 0;
783  __rxd->wrx_errors = 0;
784  __rxd->wrx_special = 0;
785  /* Receive Descriptor Tail: add Rx desc. to H/W free list */
786  CSR_WRITE(sc,WMREG_RDT, (x));
787}
788
789static void i82544EI_rx(struct wm_softc *sc)
790{
791  struct ifnet *ifp = &sc->arpcom.ac_if;
792  struct mbuf *m;
793  int i, len;
794  uint8_t status, errors;
795  struct ether_header *eh;
796
797#ifdef WM_DEBUG
798  printk("i82544EI_rx()\n");
799#endif
800
801  for (i = sc->sc_rxptr;; i = WM_NEXTRX(i)) {
802    DPRINTF(WM_DEBUG_RX, ("%s: RX: checking descriptor %d\n",
803                    sc->dv_xname, i));
804
805    status = sc->sc_rxdescs[i].wrx_status;
806    if ((status & WRX_ST_DD) == 0)  break; /* descriptor not done */
807
808    errors = sc->sc_rxdescs[i].wrx_errors;
809    len = le16toh(sc->sc_rxdescs[i].wrx_len);
810    m = sc->rxs_mbuf[i];
811    if (sc->sc_rxdiscard) {
812       printk("RX: discarding contents of descriptor %d\n", i);
813       wm_init_rxdesc(sc, i);
814       if (status & WRX_ST_EOP) {
815          /* Reset our state. */
816          printk("RX: resetting rxdiscard -> 0\n");
817          sc->sc_rxdiscard = 0;
818       }
819       continue;
820    }
821
822    /*
823     * If an error occurred, update stats and drop the packet.
824     */
825    if (errors &(WRX_ER_CE|WRX_ER_SE|WRX_ER_SEQ|WRX_ER_CXE|WRX_ER_RXE)) {
826       ifp->if_ierrors++;
827       if (errors & WRX_ER_SE)
828          printk("%s: symbol error\n",sc->dv_xname);
829       else if (errors & WRX_ER_SEQ)
830          printk("%s: receive sequence error\n",sc->dv_xname);
831            else if (errors & WRX_ER_CE)
832                 printk("%s: CRC error\n",sc->dv_xname);
833       m_freem(m);
834       goto give_it_back;
835    }
836
837    /*
838     * No errors.  Receive the packet.
839     *
840     * Note, we have configured the chip to include the
841     * CRC with every packet.
842     */
843    m->m_len = m->m_pkthdr.len = len - sizeof(struct ether_header);
844
845    DPRINTF(WM_DEBUG_RX,("%s: RX: buffer at %p len %d\n",
846                    sc->dv_xname, m->m_data, len));
847
848
849    eh = mtod (m, struct ether_header *);
850    m->m_data += sizeof(struct ether_header);
851    ether_input (ifp, eh, m);
852    /* Pass it on. */
853    ifp->if_ipackets++;
854
855    give_it_back:
856    /* Add a new receive buffer to the ring.*/
857    if (wm_add_rxbuf(sc, i) != 0) {
858       /*
859        * Failed, throw away what we've done so
860        * far, and discard the rest of the packet.
861        */
862       printk("Failed in wm_add_rxbuf(), drop packet\n");
863       ifp->if_ierrors++;
864       wm_init_rxdesc(sc, i);
865       if ((status & WRX_ST_EOP) == 0)
866          sc->sc_rxdiscard = 1;
867       m_freem(m);
868    }
869  } /* end for */
870
871  /* Update the receive pointer. */
872  sc->sc_rxptr = i;
873  DPRINTF(WM_DEBUG_RX, ("%s: RX: rxptr -> %d\n", sc->dv_xname, i));
874}
875
876static int i82544EI_init_hw(struct wm_softc *sc)
877{
878  struct ifnet *ifp = &sc->arpcom.ac_if;
879  int i,error;
880  uint8_t cksumfields;
881
882#if 0
883  /* KATETODO : sc_align_tweak */
884        /*
885         * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set.
886         * There is a small but measurable benefit to avoiding the adjusment
887         * of the descriptor so that the headers are aligned, for normal mtu,
888         * on such platforms.  One possibility is that the DMA itself is
889         * slightly more efficient if the front of the entire packet (instead
890         * of the front of the headers) is aligned.
891         *
892         * Note we must always set align_tweak to 0 if we are using
893         * jumbo frames.
894         */
895#ifdef __NO_STRICT_ALIGNMENT
896        sc->sc_align_tweak = 0;
897#else
898        if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2))
899                sc->sc_align_tweak = 0;
900        else
901                sc->sc_align_tweak = 2;
902#endif /* __NO_STRICT_ALIGNMENT */
903#endif
904
905  /* Cancel any pending I/O. */
906  wm_stop(ifp, 0);
907
908  /* update statistics before reset */
909  ifp->if_collisions += CSR_READ(sc, WMREG_COLC);
910  ifp->if_ierrors += CSR_READ(sc, WMREG_RXERRC);
911
912  /* Reset the chip to a known state. */
913  wm_reset(sc);
914
915  /* Initialize the error buffer ring */
916  sc->if_err_ptr1=0;
917  sc->if_err_ptr2=0;
918  for (i=0; i< IF_ERR_BUFSZE; i++) sc->if_errsts[i]=0;
919
920  /* Initialize the transmit descriptor ring. */
921  memset( (void *) sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
922  sc->txq_free = NTXDESC;
923  sc->txq_next = 0;
924  sc->txs_lastdesc = 0;
925  sc->txq_next = 0;
926  sc->txq_free = NTXDESC;
927  sc->txq_nactive = 0;
928
929  sc->sc_txctx_ipcs = 0xffffffff;
930  sc->sc_txctx_tucs = 0xffffffff;
931
932  CSR_WRITE(sc,WMREG_TBDAH, 0);
933  CSR_WRITE(sc,WMREG_TBDAL, WM_CDTXADDR(sc));
934#ifdef WM_DEBUG
935  printk("TBDAL 0x%x, TDLEN %d\n", WM_CDTXADDR(sc), sizeof(sc->sc_txdescs));
936#endif
937  CSR_WRITE(sc,WMREG_TDLEN, sizeof(sc->sc_txdescs));
938  CSR_WRITE(sc,WMREG_TDH, 0);
939  CSR_WRITE(sc,WMREG_TDT, 0);
940  CSR_WRITE(sc,WMREG_TIDV, 0 );
941  /* CSR_WRITE(sc,WMREG_TADV, 128);  not for 82544 */
942
943  CSR_WRITE(sc,WMREG_TXDCTL, TXDCTL_PTHRESH(0) |
944                    TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0));
945  CSR_WRITE(sc,WMREG_RXDCTL, RXDCTL_PTHRESH(0) |
946                    RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1) | RXDCTL_GRAN );
947
948  CSR_WRITE(sc,WMREG_TQSA_LO, 0);
949  CSR_WRITE(sc,WMREG_TQSA_HI, 0);
950
951  /*
952   * Set up checksum offload parameters for
953   * this packet.
954   */
955#ifdef RTEMS_CKSUM_OFFLOAD
956  if (m0->m_pkthdr.csum_flags & (M_CSUM_TSOv4|M_CSUM_TSOv6|
957                    M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4|
958                                 M_CSUM_TCPv6|M_CSUM_UDPv6)) {
959     if (wm_tx_offload(sc, txs, &TxDescCmd,&cksumfields) != 0) {
960         /* Error message already displayed. */
961         continue;
962     }
963  } else {
964#endif
965     TxDescCmd = 0;
966     cksumfields = 0;
967#ifdef RTEMS_CKSUM_OFFLOAD
968  }
969#endif
970
971  TxDescCmd |= WTX_CMD_EOP|WTX_CMD_IFCS|WTX_CMD_RS;
972
973  /* Initialize the transmit job descriptors. */
974  for (i = 0; i < NTXDESC; i++) {
975      sc->txs_mbuf[i] = 0;
976      sc->sc_txdescs[i].wtx_fields.wtxu_options=cksumfields;
977      sc->sc_txdescs[i].wtx_addr.wa_high = 0;
978      sc->sc_txdescs[i].wtx_addr.wa_low = 0;
979      sc->sc_txdescs[i].wtx_cmdlen = htole32(TxDescCmd);
980  }
981
982  /*
983   * Initialize the receive descriptor and receive job
984   * descriptor rings.
985   */
986  memset( (void *) sc->sc_rxdescs, 0, sizeof(sc->sc_rxdescs));
987  CSR_WRITE(sc,WMREG_RDBAH, 0);
988  CSR_WRITE(sc,WMREG_RDBAL, WM_CDRXADDR(sc));
989  CSR_WRITE(sc,WMREG_RDLEN, sizeof(sc->sc_rxdescs));
990  CSR_WRITE(sc,WMREG_RDH, 0);
991  CSR_WRITE(sc,WMREG_RDT, 0);
992  CSR_WRITE(sc,WMREG_RDTR, 0 |RDTR_FPD);
993  /* CSR_WRITE(sc, WMREG_RADV, 256);  not for 82544.  */
994
995  for (i = 0; i < NRXDESC; i++) {
996      if (sc->rxs_mbuf[i] == NULL) {
997         if ((error = wm_add_rxbuf(sc, i)) != 0) {
998            printk("%s%d: unable to allocate or map rx buffer"
999            "%d, error = %d\n",ifp->if_name,ifp->if_unit, i, error);
1000            /*
1001             * XXX Should attempt to run with fewer receive
1002             * XXX buffers instead of just failing.
1003             */
1004            wm_rxdrain(sc);
1005            return(error);
1006          }
1007      } else {
1008        printk("sc->rxs_mbuf[%d] not NULL.\n", i);
1009        wm_init_rxdesc(sc, i);
1010      }
1011  }
1012  sc->sc_rxptr = 0;
1013  sc->sc_rxdiscard = 0;
1014
1015  /*
1016   * Clear out the VLAN table -- we don't use it (yet).
1017   */
1018  CSR_WRITE(sc,WMREG_VET, 0);
1019  for (i = 0; i < WM_VLAN_TABSIZE; i++)
1020       CSR_WRITE(sc,WMREG_VFTA + (i << 2), 0);
1021
1022#if 0
1023  /* Use MOTLoad default
1024   *
1025   * Set up flow-control parameters.
1026   */
1027  CSR_WRITE(sc,WMREG_FCAL, FCAL_CONST);/* same as MOTLOAD 0x00c28001 */
1028  CSR_WRITE(sc,WMREG_FCAH, FCAH_CONST);/* same as MOTLOAD 0x00000100 */
1029  CSR_WRITE(sc,WMREG_FCT, ETHERTYPE_FLOWCONTROL);/* same as MOTLoad 0x8808 */
1030
1031
1032  /* safe,even though MOTLoad default all 0 */
1033  sc->sc_fcrtl = FCRTL_DFLT;
1034
1035  CSR_WRITE(sc,WMREG_FCRTH, FCRTH_DFLT);
1036  CSR_WRITE(sc,WMREG_FCRTL, sc->sc_fcrtl);
1037  /*KATETO   CSR_WRITE(sc,WMREG_FCTTV, FCTTV_DFLT);*/
1038  CSR_WRITE(sc,WMREG_FCTTV, 0x100);
1039#endif
1040
1041  sc->sc_ctrl &= ~CTRL_VME;
1042  /* TODO : not here.
1043     Configures flow control settings after link is established
1044     sc->sc_ctrl |= CTRL_TFCE | CTRL_RFCE; */
1045
1046  /* Write the control registers. */
1047  CSR_WRITE(sc,WMREG_CTRL, sc->sc_ctrl);
1048#if 0
1049  CSR_WRITE(sc,WMREG_CTRL_EXT, sc->sc_ctrl_ext);
1050#endif
1051
1052  /* MOTLoad : WMREG_RXCSUM (0x5000)= 0, no Rx checksum offloading */
1053#ifdef RTEMS_CKSUM_OFFLOAD
1054  /*
1055   * Set up checksum offload parameters.
1056   */
1057   reg = CSR_READ(sc, WMREG_RXCSUM);
1058   reg &= ~(RXCSUM_IPOFL | RXCSUM_IPV6OFL | RXCSUM_TUOFL);
1059   if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx)
1060            reg |= RXCSUM_IPOFL;
1061   if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx))
1062            reg |= RXCSUM_IPOFL | RXCSUM_TUOFL;
1063   if (ifp->if_capenable & (IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx))
1064            reg |= RXCSUM_IPV6OFL | RXCSUM_TUOFL;
1065   CSR_WRITE(sc, WMREG_RXCSUM, reg);
1066#endif
1067
1068  /*
1069   * Set up the interrupt registers.
1070   */
1071  CSR_WRITE(sc,WMREG_IMC, 0xffffffffU);
1072
1073  /* Reading the WMREG_ICR clears the interrupt bits */
1074  CSR_READ(sc,WMREG_ICR);
1075
1076  /*  printf("WMREG_IMS 0x%x\n", CSR_READ(sc,WMREG_IMS));*/
1077
1078  sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXCFG | ICR_RXDMT0 | ICR_RXO | ICR_RXT0;
1079
1080  CSR_WRITE(sc,WMREG_IMS, sc->sc_icr);
1081
1082  /* Set up the inter-packet gap. */
1083  CSR_WRITE(sc,WMREG_TIPG, sc->sc_tipg);
1084
1085#if 0 /* XXXJRT */
1086  /* Set the VLAN ethernetype. */
1087  CSR_WRITE(sc,WMREG_VET, ETHERTYPE_VLAN);
1088#endif
1089
1090  /*
1091   * Set up the transmit control register; we start out with
1092   * a collision distance suitable for FDX, but update it when
1093   * we resolve the media type.
1094   */
1095  sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_CT(TX_COLLISION_THRESHOLD) |
1096            TCTL_COLD(TX_COLLISION_DISTANCE_FDX) |
1097            TCTL_RTLC /* retransmit on late collision */;
1098
1099  /*
1100   * Set up the receive control register; we actually program
1101   * the register when we set the receive filter.  Use multicast
1102   * address offset type 0.
1103   *
1104   * Only the i82544 has the ability to strip the incoming
1105   * CRC (RCTL_SECRC).
1106   */
1107  sc->sc_mchash_type = 0;
1108  sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_LPE |
1109    RCTL_DPF | RCTL_MO(sc->sc_mchash_type)|RCTL_SECRC;
1110
1111  if (MCLBYTES == 2048) {
1112     sc->sc_rctl |= RCTL_2k;
1113  } else {
1114        switch(MCLBYTES) {
1115        case 4096:
1116             sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k;
1117             break;
1118        case 8192:
1119             sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k;
1120             break;
1121        case 16384:
1122             sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k;
1123             break;
1124        default:
1125             rtems_panic("wm_init: MCLBYTES %d unsupported",
1126                    MCLBYTES);
1127             break;
1128        }
1129  }
1130
1131#ifdef WM_DEBUG
1132  printk("RDBAL 0x%x,RDLEN %d, RDT %d\n",CSR_READ(sc,WMREG_RDBAL),CSR_READ(sc,WMREG_RDLEN), CSR_READ(sc,WMREG_RDT));
1133#endif
1134
1135  /* Set the receive filter. */
1136  wm_set_filter(sc);
1137
1138  CSR_WRITE(sc,WMREG_TCTL, sc->sc_tctl);
1139
1140  /* Map and establish our interrupt. */
1141  if (!BSP_install_rtems_irq_handler(&i82544IrqData))
1142     rtems_panic("1GHZ ethernet: unable to install ISR");
1143
1144  return(0);
1145}
1146
1147void BSP_rdTIDV(void)
1148{
1149  printf("Reg TIDV: 0x%" PRIx32 "\n", in_le32((volatile uint32_t *) (BSP_1GHz_membase+WMREG_TIDV)));
1150}
1151void BSP_rdRDTR(void)
1152{
1153  printf("Reg RDTR: 0x%" PRIx32 "\n", in_le32((volatile uint32_t *) (BSP_1GHz_membase+WMREG_RDTR)));
1154}
1155
1156void BSP_setTIDV(int val)
1157{
1158  out_le32((volatile uint32_t *) (BSP_1GHz_membase+WMREG_TIDV), val);
1159}
1160
1161void BSP_setRDTR(int val)
1162{
1163  out_le32((volatile uint32_t *) (BSP_1GHz_membase+WMREG_RDTR), val);
1164}
1165/*
1166 * i82544EI_ifinit:             [ifnet interface function]
1167 *
1168 *      Initialize the interface.
1169 */
1170static void i82544EI_ifinit(void *arg)
1171{
1172  struct wm_softc *sc = (struct wm_softc*)arg;
1173
1174#ifdef WM_DEBUG
1175  printk("i82544EI_ifinit(): daemon ID: 0x%08x)\n", sc->daemonTid);
1176#endif
1177  if (sc->daemonTid) {
1178#ifdef WM_DEBUG
1179     printk("i82544EI: daemon already up, doing nothing\n");
1180#endif
1181     return;
1182  }
1183  i82544EI_init_hw(sc);
1184
1185  sc->daemonTid = rtems_bsdnet_newproc(i82544EI_TASK_NAME,4096,i82544EI_daemon,arg);
1186
1187  /* ...all done! */
1188  sc->arpcom.ac_if.if_flags |= IFF_RUNNING;
1189
1190#ifdef WM_DEBUG
1191  printk(")");
1192#endif
1193}
1194
1195/*
1196 * wm_txdrain:
1197 *
1198 *      Drain the transmit queue.
1199 */
1200static void wm_txdrain(struct wm_softc *sc)
1201{
1202  int i;
1203
1204  /* Release any queued transmit buffers. */
1205  for (i = 0; i <  NTXDESC; i++) {
1206      if (sc->txs_mbuf[i] != NULL) {
1207          m_freem(sc->txs_mbuf[i]);
1208          sc->txs_mbuf[i] = NULL;
1209      }
1210  }
1211}
1212
1213/*
1214 * wm_rxdrain:
1215 *
1216 *      Drain the receive queue.
1217 */
1218static void wm_rxdrain(struct wm_softc *sc)
1219{
1220  int i;
1221
1222  for (i = 0; i < NRXDESC; i++) {
1223      if (sc->rxs_mbuf[i] != NULL) {
1224          m_freem(sc->rxs_mbuf[i]);
1225          sc->rxs_mbuf[i] = NULL;
1226      }
1227  }
1228}
1229
1230static void i82544EI_tx_stop(struct wm_softc *sc)
1231{
1232  wm_txdrain(sc);
1233}
1234
1235static void i82544EI_rx_stop(struct wm_softc *sc)
1236{
1237  wm_rxdrain(sc);
1238}
1239
1240static void i82544EI_stop_hw(struct wm_softc *sc)
1241{
1242#ifdef WM_DEBUG
1243  printk("i82544EI_stop_hw(");
1244#endif
1245
1246  /* remove our interrupt handler which will also
1247  * disable interrupts at the MPIC and the device
1248  * itself
1249  */
1250  if (!BSP_remove_rtems_irq_handler(&i82544IrqData))
1251     rtems_panic("i82544EI: unable to remove IRQ handler!");
1252
1253  CSR_WRITE(sc,WMREG_IMS, 0);
1254
1255  sc->arpcom.ac_if.if_flags &= ~IFF_RUNNING;
1256  i82544EI_tx_stop(sc);
1257  i82544EI_rx_stop(sc);
1258#ifdef WM_DEBUG
1259  printk(")");
1260#endif
1261}
1262
1263/*
1264 * wm_stop:             [ifnet interface function]
1265 *
1266 *      Stop transmission on the interface.
1267 */
1268static void wm_stop(struct ifnet *ifp, int disable)
1269{
1270  struct wm_softc *sc = ifp->if_softc;
1271
1272#ifdef WM_DEBUG
1273  printk("wm_stop(");
1274#endif
1275  /* Stop the transmit and receive processes. */
1276  CSR_WRITE(sc,WMREG_TCTL, 0);
1277  CSR_WRITE(sc,WMREG_RCTL, 0);
1278
1279  wm_txdrain(sc);
1280  wm_rxdrain(sc);
1281
1282  /* Mark the interface as down  */
1283  ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1284#ifdef WM_DEBUG
1285  printk(")\n");
1286#endif
1287}
1288
1289/*
1290 * wm_eeprom_sendbits:
1291 *
1292 *      Send a series of bits to the EEPROM.
1293 */
1294static void wm_eeprom_sendbits(struct wm_softc *sc, uint32_t bits, int nbits)
1295{
1296  uint32_t reg;
1297  int x;
1298
1299  reg = CSR_READ(sc,WMREG_EECD);
1300
1301  for (x = nbits; x > 0; x--) {
1302      if (bits & (1U << (x - 1)))
1303         reg |= EECD_DI;
1304      else
1305         reg &= ~EECD_DI;
1306      CSR_WRITE(sc,WMREG_EECD, reg);
1307      rtems_bsp_delay(2);
1308      CSR_WRITE(sc,WMREG_EECD, reg | EECD_SK);
1309      rtems_bsp_delay(2);
1310      CSR_WRITE(sc,WMREG_EECD, reg);
1311      rtems_bsp_delay(2);
1312  }
1313}
1314
1315/*
1316 * wm_eeprom_recvbits:
1317 *
1318 *      Receive a series of bits from the EEPROM.
1319 */
1320static void wm_eeprom_recvbits(struct wm_softc *sc, uint32_t *valp, int nbits)
1321{
1322  uint32_t reg, val;
1323  int x;
1324
1325  reg = CSR_READ(sc,WMREG_EECD) & ~EECD_DI;
1326
1327  val = 0;
1328  for (x = nbits; x > 0; x--) {
1329      CSR_WRITE(sc,WMREG_EECD, reg | EECD_SK);
1330      rtems_bsp_delay(2);
1331      if (CSR_READ(sc,WMREG_EECD) & EECD_DO)
1332         val |= (1U << (x - 1));
1333      CSR_WRITE(sc,WMREG_EECD, reg);
1334      rtems_bsp_delay(2);
1335  }
1336  *valp = val;
1337}
1338
1339/*
1340 * wm_read_eeprom_uwire:
1341 *
1342 * Read a word from the EEPROM using the MicroWire protocol.
1343 *
1344 * (The 82544EI Gigabit Ethernet Controller is compatible with
1345 * most MicroWire interface, serial EEPROM devices.)
1346 */
1347static int wm_read_eeprom_uwire(struct wm_softc *sc, int word, int wordcnt, uint16_t *data)
1348{
1349  uint32_t reg, val;
1350  int i;
1351
1352  for (i = 0; i < wordcnt; i++) {
1353      /* Clear SK and DI. */
1354      reg = CSR_READ(sc,WMREG_EECD) & ~(EECD_SK | EECD_DI);
1355      CSR_WRITE(sc,WMREG_EECD, reg);
1356
1357      /* Set CHIP SELECT. */
1358      reg |= EECD_CS;
1359      CSR_WRITE(sc,WMREG_EECD, reg);
1360      rtems_bsp_delay(2);
1361
1362      /* Shift in the READ command. */
1363      wm_eeprom_sendbits(sc, UWIRE_OPC_READ, 3);
1364
1365      /* Shift in address. */
1366      wm_eeprom_sendbits(sc, word + i, sc->sc_ee_addrbits);
1367
1368      /* Shift out the data. */
1369      wm_eeprom_recvbits(sc, &val, 16);
1370      data[i] = val & 0xffff;
1371
1372      /* Clear CHIP SELECT. */
1373      reg = CSR_READ(sc,WMREG_EECD) & ~EECD_CS;
1374      CSR_WRITE(sc,WMREG_EECD, reg);
1375      rtems_bsp_delay(2);
1376  }
1377  return (0);
1378}
1379
1380#if 0
1381/*
1382 * wm_acquire_eeprom:
1383 *
1384 *      Perform the EEPROM handshake required on some chips.
1385 */
1386static int wm_acquire_eeprom(struct wm_softc *sc)
1387{
1388  uint32_t reg;
1389  int x;
1390
1391  reg = CSR_READ(sc,WMREG_EECD);
1392
1393  /* Request EEPROM access. */
1394  reg |= EECD_EE_REQ;
1395  CSR_WRITE(sc,WMREG_EECD, reg);
1396
1397  /* ..and wait for it to be granted. */
1398  for (x = 0; x < 100; x++) {
1399      reg = CSR_READ(sc,WMREG_EECD);
1400      if (reg & EECD_EE_GNT) break;
1401      rtems_bsp_delay(500);
1402  }
1403  if ((reg & EECD_EE_GNT) == 0) {
1404      printk("Could not acquire EEPROM GNT x= %d\n", x);
1405      reg &= ~EECD_EE_REQ;
1406      CSR_WRITE(sc,WMREG_EECD, reg);
1407      return (1);
1408  }
1409
1410  return (0);
1411}
1412#endif
1413
1414/*
1415 * wm_read_eeprom:
1416 *
1417 * Read data from the serial EEPROM.
1418 * 82544EI does not Perform the EEPROM handshake
1419 */
1420static int wm_read_eeprom(struct wm_softc *sc, int word, int wordcnt, uint16_t *data)
1421{
1422#if 0
1423  /* base on the datasheet, this does not seem to be applicable */
1424  if (wm_acquire_eeprom(sc))
1425     return(1);
1426#endif
1427  return(wm_read_eeprom_uwire(sc, word, wordcnt, data));
1428}
1429
1430/*
1431 * wm_add_rxbuf:
1432 *
1433 *      Add a receive buffer to the indiciated descriptor.
1434 */
1435static int wm_add_rxbuf(struct wm_softc *sc, int idx)
1436{
1437  struct mbuf *m;
1438
1439  MGETHDR(m, M_WAIT, MT_DATA);
1440  if (m == NULL) return (ENOBUFS);
1441  MCLGET(m, M_WAIT);
1442  if ((m->m_flags & M_EXT) == 0) {
1443     m_freem(m);
1444     return (ENOBUFS);
1445  }
1446  m->m_pkthdr.rcvif =  &sc->arpcom.ac_if;
1447  sc->rxs_mbuf[idx] = m;
1448  /*  m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;*/
1449  wm_init_rxdesc(sc, idx);
1450#if 0
1451  printk("sc->rxs_mbuf[%d]= 0x%x, mbuf @ 0x%x\n",
1452    idx, sc->rxs_mbuf[idx], le32toh(sc->sc_rxdescs[idx].wrx_addr.wa_low));
1453#endif
1454  return(0);
1455}
1456
1457/*
1458 * wm_set_ral:
1459 *
1460 *      Set an entery in the receive address list.
1461 */
1462static void
1463wm_set_ral(struct wm_softc *sc, const uint8_t *enaddr, int idx)
1464{
1465  uint32_t ral_lo, ral_hi;
1466
1467  if (enaddr != NULL) {
1468     ral_lo = enaddr[0]|(enaddr[1] << 8)|(enaddr[2] << 16)|(enaddr[3] << 24);
1469     ral_hi = enaddr[4] | (enaddr[5] << 8);
1470     ral_hi |= RAL_AV;
1471  } else {
1472     ral_lo = 0;
1473     ral_hi = 0;
1474  }
1475
1476  CSR_WRITE(sc,WMREG_RAL_LO(WMREG_CORDOVA_RAL_BASE, idx),ral_lo);
1477  CSR_WRITE(sc,WMREG_RAL_HI(WMREG_CORDOVA_RAL_BASE, idx),ral_hi);
1478}
1479
1480/*
1481 * wm_mchash:
1482 *
1483 *      Compute the hash of the multicast address for the 4096-bit
1484 *      multicast filter.
1485 */
1486static uint32_t
1487wm_mchash(struct wm_softc *sc, const uint8_t *enaddr)
1488{
1489  static const int lo_shift[4] = { 4, 3, 2, 0 };
1490  static const int hi_shift[4] = { 4, 5, 6, 8 };
1491  uint32_t hash;
1492
1493  hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) |
1494            (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]);
1495
1496  return (hash & 0xfff);
1497}
1498
1499/*
1500 * wm_set_filter: Set up the receive filter.
1501 */
1502static void wm_set_filter(struct wm_softc *sc)
1503{
1504  struct ifnet *ifp = &sc->arpcom.ac_if;
1505  struct ether_multi *enm;
1506  struct ether_multistep step;
1507  uint32_t mta_reg;
1508  uint32_t hash, reg, bit;
1509  int i;
1510
1511#ifdef WM_DEBUG
1512  printk("wm_set_filter(");
1513#endif
1514  mta_reg = WMREG_CORDOVA_MTA;
1515  sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE);
1516
1517  if (ifp->if_flags & IFF_BROADCAST)
1518     sc->sc_rctl |= RCTL_BAM;
1519  if (ifp->if_flags & IFF_PROMISC) {
1520     sc->sc_rctl |= RCTL_UPE;
1521     goto allmulti;
1522  }
1523
1524  /*
1525   * Set the station address in the first RAL slot, and
1526   * clear the remaining slots.
1527   */
1528  wm_set_ral(sc, sc->arpcom.ac_enaddr, 0);
1529  for (i = 1; i < WM_RAL_TABSIZE; i++)
1530      wm_set_ral(sc, NULL, i);
1531
1532  /* Clear out the multicast table. */
1533  for (i = 0; i < WM_MC_TABSIZE; i++)
1534      CSR_WRITE(sc,mta_reg + (i << 2), 0);
1535
1536  ETHER_FIRST_MULTI(step, &sc->arpcom, enm);
1537  while (enm != NULL) {
1538        if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
1539            /*
1540             * We must listen to a range of multicast addresses.
1541             * For now, just accept all multicasts, rather than
1542             * trying to set only those filter bits needed to match
1543             * the range.  (At this time, the only use of address
1544             * ranges is for IP multicast routing, for which the
1545             * range is big enough to require all bits set.)
1546             */
1547            goto allmulti;
1548         }
1549
1550         hash = wm_mchash(sc, enm->enm_addrlo);
1551
1552         reg = (hash >> 5) & 0x7f;
1553         bit = hash & 0x1f;
1554
1555         hash = CSR_READ(sc,mta_reg + (reg << 2));
1556         hash |= 1U << bit;
1557
1558         /* XXX Hardware bug?? */
1559         if ((reg & 0xe) == 1) {
1560            bit = CSR_READ(sc,mta_reg + ((reg - 1) << 2));
1561            CSR_WRITE(sc,mta_reg + (reg << 2), hash);
1562            CSR_WRITE(sc,mta_reg + ((reg - 1) << 2), bit);
1563         } else
1564            CSR_WRITE(sc,mta_reg + (reg << 2), hash);
1565
1566         ETHER_NEXT_MULTI(step, enm);
1567  }
1568
1569  ifp->if_flags &= ~IFF_ALLMULTI;
1570  goto setit;
1571
1572 allmulti:
1573  ifp->if_flags |= IFF_ALLMULTI;
1574  sc->sc_rctl |= RCTL_MPE;
1575
1576 setit:
1577  CSR_WRITE(sc,WMREG_RCTL, sc->sc_rctl);
1578
1579#ifdef WM_DEBUG
1580  printk("RCTL 0x%x)\n", CSR_READ(sc,WMREG_RCTL));
1581#endif
1582}
1583
1584static void i82544EI_error(struct wm_softc *sc)
1585{
1586  struct ifnet          *ifp = &sc->arpcom.ac_if;
1587  unsigned long         intr_status= sc->if_errsts[sc->if_err_ptr1];
1588
1589  /* read and reset the status; because this is written
1590   * by the ISR, we must disable interrupts here
1591   */
1592  if (intr_status) {
1593    printk("Error %s%d:", ifp->if_name, ifp->if_unit);
1594    if (intr_status & ICR_RXSEQ) {
1595       printk("Rxq framing error (ICR= %x), if_ierrors %d\n",
1596              intr_status, ifp->if_ierrors);
1597    }
1598  }
1599  else
1600    printk("%s%d: Ghost interrupt ?\n",ifp->if_name,ifp->if_unit);
1601  sc->if_errsts[sc->if_err_ptr1]=0;
1602  if ((++sc->if_err_ptr1)==IF_ERR_BUFSZE) sc->if_err_ptr1=0; /* Till Straumann */
1603}
1604
1605void i82544EI_printStats(void)
1606{
1607  i82544EI_stats(root_i82544EI_dev);
1608}
1609
1610/* The daemon does all of the work; RX, TX and cleaning up buffers/descriptors */
1611static void i82544EI_daemon(void *arg)
1612{
1613  struct wm_softc *sc = (struct wm_softc*)arg;
1614  rtems_event_set       events;
1615  struct mbuf   *m=0;
1616  struct ifnet  *ifp=&sc->arpcom.ac_if;
1617
1618#ifdef WM_DEBUG
1619  printk("i82544EI_daemon()\n");
1620#endif
1621
1622  /* NOTE: our creator possibly holds the bsdnet_semaphore.
1623   *       since that has PRIORITY_INVERSION enabled, our
1624   *       subsequent call to bsdnet_event_receive() will
1625   *       _not_ release it. It's still in posession of our
1626   *       owner.
1627   *       This is different from how killing this task
1628   *       is handled.
1629   */
1630
1631  for (;;) {
1632     /* sleep until there's work to be done */
1633     /* Note: bsdnet_event_receive() acquires
1634      *       the global bsdnet semaphore for
1635      *       mutual exclusion.
1636      */
1637     rtems_bsdnet_event_receive(ALL_EVENTS,
1638                                RTEMS_WAIT | RTEMS_EVENT_ANY,
1639                                RTEMS_NO_TIMEOUT,
1640                                &events);
1641     if (KILL_EVENT & events)  break;
1642
1643     if (events & RX_EVENT)  i82544EI_rx(sc); /* in ISR instead */
1644
1645     /* clean up and try sending packets */
1646     do {
1647        i82544EI_txq_done(sc);
1648
1649        while (sc->txq_free>0) {
1650           if (sc->txq_free>TXQ_HiLmt_OFF) {
1651              m=0;
1652              IF_DEQUEUE(&ifp->if_snd,m);
1653              if (m==0) break;
1654              i82544EI_sendpacket(sc, m);
1655           }
1656           else {
1657              i82544EI_txq_done(sc);
1658              break;
1659           }
1660        }
1661         /* we leave this loop
1662          *  - either because there's no free buffer
1663          *    (m=0 initializer && !sc->txq_free)
1664          *  - or there's nothing to send (IF_DEQUEUE
1665          *    returned 0
1666          */
1667     } while (m);
1668
1669     ifp->if_flags &= ~IFF_OACTIVE;
1670
1671     /* Log errors and other uncommon events. */
1672     if (events & ERR_EVENT) i82544EI_error(sc);
1673     /* Rx overrun */
1674     if ( events & INIT_EVENT) {
1675        printk("Warnning, Rx overrun.  Make sure the old mbuf was free\n");
1676        i82544EI_ifinit(arg);
1677     }
1678
1679  } /* end for(;;) { rtems_bsdnet_event_receive() .....*/
1680
1681  printf("out of daemon\n");
1682  ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
1683
1684  /* shut down the hardware */
1685  i82544EI_stop_hw(sc);
1686  /* flush the output queue */
1687  for (;;) {
1688      IF_DEQUEUE(&ifp->if_snd,m);
1689      if (!m) break;
1690      m_freem(m);
1691  }
1692  /* as of 'rtems_bsdnet_event_receive()' we own the
1693   * networking semaphore
1694   */
1695  rtems_bsdnet_semaphore_release();
1696  rtems_semaphore_release(sc->daemonSync);
1697
1698  /* Note that I dont use sc->daemonTid here -
1699   * theoretically, that variable could already
1700   * hold a newly created TID
1701   */
1702  rtems_task_delete(RTEMS_SELF);
1703}
1704
1705/*
1706 * wm_gmii_reset:
1707 *
1708 *      Reset the PHY.
1709 */
1710static void wm_gmii_reset(struct wm_softc *sc)
1711{
1712
1713  CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET);
1714  rtems_bsp_delay(20000);
1715
1716  CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
1717  rtems_bsp_delay(20000);
1718
1719}
1720
1721/*
1722 * wm_gmii_mediainit:
1723 *
1724 *      Initialize media for use on 1000BASE-T devices.
1725 */
1726static void wm_gmii_mediainit(struct wm_softc *sc)
1727{
1728  /*  struct ifnet *ifp = &sc->arpcom.ac_if;*/
1729
1730  /* We have MII. */
1731  sc->sc_flags |= WM_F_HAS_MII;
1732
1733#if 0
1734  /* <skf> May 2009 : The value that should be programmed into IPGT is 10 */
1735  sc->sc_tipg = TIPG_IPGT(10)+TIPG_IPGR1(8)+TIPG_IPGR2(6);
1736#else
1737  sc->sc_tipg = TIPG_1000T_DFLT; /* 0x602008 */
1738#endif
1739
1740  /*
1741   * Let the chip set speed/duplex on its own based on
1742   * signals from the PHY.
1743   * XXXbouyer - I'm not sure this is right for the 80003,
1744   * the em driver only sets CTRL_SLU here - but it seems to work.
1745   */
1746  sc->sc_ctrl |= CTRL_SLU;
1747  CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
1748
1749  wm_gmii_reset(sc);
1750
1751#if 0
1752  /* Initialize our media structures and probe the GMII. */
1753  sc->sc_mii.mii_ifp = ifp;
1754
1755  sc->sc_mii.mii_readreg = wm_gmii_i82544_readreg;
1756  sc->sc_mii.mii_writereg = wm_gmii_i82544_writereg;
1757  sc->sc_mii.mii_statchg = wm_gmii_statchg;
1758
1759  ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_gmii_mediachange,
1760            wm_gmii_mediastatus);
1761
1762  mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
1763            MII_OFFSET_ANY, MIIF_DOPAUSE);
1764  if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
1765     ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
1766     ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE);
1767  } else
1768      ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
1769#endif
1770}
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