source: rtems/c/src/lib/libbsp/powerpc/mvme5500/network/if_1GHz/if_wm.c @ 6771a9e7

4.104.114.95
Last change on this file since 6771a9e7 was 6771a9e7, checked in by Ralf Corsepius <ralf.corsepius@…>, on 08/20/08 at 09:00:11

Add missing prototypes.

  • Property mode set to 100644
File size: 42.8 KB
Line 
1/*
2 * Copyright (c) 2004,2005 RTEMS/Mvme5500 port by S. Kate Feng <feng1@bnl.gov>
3 *      Brookhaven National Laboratory, All rights reserved
4 *
5 * Acknowledgements:
6 * netBSD : Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
7 *          Jason R. Thorpe for Wasabi Systems, Inc.
8 * Intel : NDA document
9 *
10 * Some notes from the author, S. Kate Feng :
11 *
12 * 1) The error reporting routine i82544EI_error() employs two pointers
13 *    for the error report buffer. One for the ISR and another one for
14 *    the error report.
15 * 2) Enable the hardware Auto-Negotiation state machine.
16 * 3) Set Big Endian mode in the WMREG_CTRL so that we do not need htole32
17 *    because PPC is big endian mode.
18 *    However, the data packet structure defined in if_wmreg.h
19 *    should be redefined for the big endian mode.
20 * 4) To ensure the cache coherence, the MOTLoad had the PCI
21 *    snoop control registers (0x1f00) set to "snoop to WB region" for
22 *    the entire 512MB of memory.
23 * 5) MOTLoad default :
24 *    little endian mode, cache line size is 32 bytes, no checksum control,
25 *    hardware auto-neg. state machine disabled. PCI control "snoop
26 *    to WB region", MII mode (PHY) instead of TBI mode.
27 * 6) We currently only use 32-bit (instead of 64-bit) DMA addressing.
28 * 7) Support for checksum offloading and TCP segmentation offload will
29 *    be available for releasing in 2008, upon request, if I still believe.
30 *   
31 */
32
33#define BYTE_ORDER BIG_ENDIAN
34
35#define INET
36
37#include <rtems.h>
38#include <rtems/bspIo.h>      /* printk */
39#include <stdio.h>            /* printf for statistics */
40#include <string.h>
41
42#include <libcpu/io.h>        /* inp & friends */
43#include <libcpu/spr.h>       /* registers.h is included here */
44#include <bsp.h>
45
46#include <sys/param.h>
47#include <sys/systm.h>
48#include <sys/mbuf.h>
49
50#include <rtems/rtems_bsdnet.h>
51#include <rtems/rtems_bsdnet_internal.h>
52#include <rtems/error.h>           
53#include <errno.h>
54
55#include <rtems/rtems/types.h>
56#include <rtems/score/cpu.h>
57
58#include <sys/queue.h>
59
60#include <sys/ioctl.h>
61#include <sys/socket.h>
62#include <sys/sockio.h>             /* SIOCADDMULTI, SIOC...     */
63#include <net/if.h>
64#include <net/if_dl.h>
65#include <netinet/in.h>
66#include <netinet/if_ether.h>
67
68#ifdef INET
69#include <netinet/in_var.h>
70#endif
71
72#include <bsp/irq.h>
73#include <bsp/pci.h>
74#include <bsp/pcireg.h>
75#include <bsp/if_wmreg.h>
76#define WMREG_RADV      0x282c  /* Receive Interrupt Absolute Delay Timer */
77
78/*#define CKSUM_OFFLOAD*/
79
80#define ETHERTYPE_FLOWCONTROL   0x8808  /* 802.3x flow control packet */
81
82#define i82544EI_TASK_NAME "IGHZ"
83#define SOFTC_ALIGN        4095
84
85#define INTR_ERR_SIZE        16
86
87/*#define WM_DEBUG*/
88#ifdef WM_DEBUG
89#define WM_DEBUG_LINK           0x01
90#define WM_DEBUG_TX             0x02
91#define WM_DEBUG_RX             0x04
92#define WM_DEBUG_GMII           0x08
93int     wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK;
94
95#define DPRINTF(x, y)   if (wm_debug & (x)) printk y
96#else
97#define DPRINTF(x, y)   /* nothing */
98#endif /* WM_DEBUG */
99
100/* RTEMS event to kill the daemon */
101#define KILL_EVENT              RTEMS_EVENT_1
102/* RTEMS event to (re)start the transmitter */
103#define START_TRANSMIT_EVENT    RTEMS_EVENT_2
104/* RTEMS events used by the ISR */
105#define RX_EVENT                RTEMS_EVENT_3
106#define TX_EVENT                RTEMS_EVENT_4
107#define ERR_EVENT               RTEMS_EVENT_5
108#define INIT_EVENT              RTEMS_EVENT_6
109 
110#define ALL_EVENTS (KILL_EVENT|START_TRANSMIT_EVENT|RX_EVENT|TX_EVENT|ERR_EVENT|INIT_EVENT)
111
112
113#define NTXDESC                 128
114#define NTXDESC_MASK            (NTXDESC - 1)
115#define WM_NEXTTX(x)            (((x) + 1) & NTXDESC_MASK)
116
117#define NRXDESC                 64
118#define NRXDESC_MASK            (NRXDESC - 1)
119#define WM_NEXTRX(x)            (((x) + 1) & NRXDESC_MASK)
120#define WM_PREVRX(x)            (((x) - 1) & NRXDESC_MASK)
121
122#define WM_CDOFF(x)     offsetof(struct wm_control_data, x)
123#define WM_CDTXOFF(x)   WM_CDOFF(sc_txdescs[(x)])
124#define WM_CDRXOFF(x)   WM_CDOFF(sc_rxdescs[(x)])
125
126#define TXQ_HiLmt_OFF 64
127
128static uint32_t TxDescCmd;
129
130/*
131 * Software state per device.
132 */
133struct wm_softc {
134        wiseman_txdesc_t sc_txdescs[NTXDESC]; /* transmit descriptor memory */
135        wiseman_rxdesc_t sc_rxdescs[NRXDESC]; /* receive descriptor memory */
136        struct mbuf *txs_mbuf[NTXDESC];        /* transmit buffer memory */
137        struct mbuf *rxs_mbuf[NRXDESC];        /* receive buffer memory */
138        struct wm_softc *next_module;
139        volatile unsigned int intr_errsts[INTR_ERR_SIZE]; /* intr_status */
140        unsigned int intr_err_ptr1;     /* ptr used in i82544EI_error() */
141        unsigned int intr_err_ptr2;     /* ptr used in ISR */
142        int txs_firstdesc;              /* first descriptor in packet */
143        int txs_lastdesc;               /* last descriptor in packet */
144        int txs_ndesc;                  /* # of descriptors used */
145        unsigned sc_membase;            /* Memory space base address */
146        unsigned sc_memsize;            /* Memory space size */
147
148        char    dv_xname[16];           /* external name (name + unit) */
149        void *sc_sdhook;                /* shutdown hook */
150        struct arpcom arpcom;           /* rtems if structure, contains ifnet */
151        int sc_flags;                   /* flags; see below */
152        int sc_bus_speed;               /* PCI/PCIX bus speed */
153        int sc_flowflags;               /* 802.3x flow control flags */
154
155        void *sc_ih;                    /* interrupt cookie */
156
157        int sc_ee_addrbits;             /* EEPROM address bits */
158        rtems_id        daemonTid;
159        rtems_id        daemonSync;     /* synchronization with the daemon */
160
161        int      txq_next;              /* next Tx descriptor ready for transmitting */
162        uint32_t txq_nactive;           /* number of active TX descriptors */
163        uint32_t txq_fi;                /* next free Tx descriptor */
164        uint32_t txq_free;              /* number of free Tx jobs */
165        uint32_t sc_txctx_ipcs;         /* cached Tx IP cksum ctx */
166        uint32_t sc_txctx_tucs;         /* cached Tx TCP/UDP cksum ctx */
167
168        int     sc_rxptr;               /* next ready Rx descriptor/queue ent */
169        int     sc_rxdiscard;
170        int     sc_rxlen;
171        uint32_t sc_ctrl;               /* prototype CTRL register */
172#if 0
173        uint32_t sc_ctrl_ext;           /* prototype CTRL_EXT register */
174#endif
175        uint32_t sc_icr;                /* prototype interrupt bits */
176        uint32_t sc_tctl;               /* prototype TCTL register */
177        uint32_t sc_rctl;               /* prototype RCTL register */
178        uint32_t sc_tipg;               /* prototype TIPG register */
179        uint32_t sc_fcrtl;              /* prototype FCRTL register */
180
181        int sc_mchash_type;             /* multicast filter offset */
182
183        /* statistics */
184        struct {
185          volatile unsigned long     rxInterrupts;
186          volatile unsigned long     txInterrupts;
187          unsigned long     txMultiBuffPacket;
188          unsigned long     txMultiMaxLen;
189          unsigned long     txSinglMaxLen;
190          unsigned long     txMultiMaxLoop;
191          unsigned long     txBuffMaxLen;
192          unsigned long     linkInterrupts;
193          unsigned long     length_errors;
194          unsigned long     frame_errors;
195          unsigned long     crc_errors;
196          unsigned long     rxOvrRunInterrupts; /* Rx overrun interrupt */
197          unsigned long     rxSeqErr;
198          unsigned long     rxC_ordered;
199          unsigned long     ghostInterrupts;
200          unsigned long     linkStatusChng;
201        } stats;
202};
203
204/* <skf> our memory address seen from the PCI bus should be 1:1 */
205#define htole32(x)  le32toh(x)
206#define le32toh(x)  CPU_swap_u32((unsigned int) x)
207#define le16toh(x)  CPU_swap_u16(x)
208
209/* sc_flags */
210#define WM_F_HAS_MII            0x01    /* has MII */
211/* 82544 EI does not perform EEPROM handshake, EEPROM interface is not SPI */
212#define WM_F_EEPROM_HANDSHAKE   0x02    /* requires EEPROM handshake */
213#define WM_F_EEPROM_SPI         0x04    /* EEPROM is SPI */
214#define WM_F_IOH_VALID          0x10    /* I/O handle is valid */
215#define WM_F_BUS64              0x20    /* bus is 64-bit */
216#define WM_F_PCIX               0x40    /* bus is PCI-X */
217
218#define CSR_READ(sc,reg) in_le32((volatile unsigned *)(sc->sc_membase+reg))
219#define CSR_WRITE(sc,reg,val) out_le32((volatile unsigned *)(sc->sc_membase+reg), val)
220
221#define WM_CDTXADDR(sc) ( (uint32_t) &sc->sc_txdescs[0] )
222#define WM_CDRXADDR(sc) ( (uint32_t) &sc->sc_rxdescs[0] )
223
224static struct wm_softc *root_i82544EI_dev = NULL;
225
226static void i82544EI_ifstart(struct ifnet *ifp);
227static int  wm_ioctl(struct ifnet *ifp, u_long cmd,uint32_t data);
228static void i82544EI_ifinit(void *arg);
229static void wm_stop(struct ifnet *ifp, int disable);
230
231static void wm_rxdrain(struct wm_softc *sc);
232static int  wm_add_rxbuf(struct wm_softc *sc, int idx);
233static int  wm_read_eeprom(struct wm_softc *sc,int word,int wordcnt, uint16_t *data);
234static void i82544EI_daemon(void *arg);
235static void wm_set_filter(struct wm_softc *sc);
236
237static void i82544EI_isr(void);
238static void i82544EI_sendpacket(struct wm_softc *sc, struct mbuf *m);
239extern int  pci_mem_find(), pci_io_find(), pci_get_capability(void);
240extern char * ether_sprintf1(void);
241
242static void i82544EI_irq_on(const rtems_irq_connect_data *irq)
243{
244  struct wm_softc *sc;
245  unsigned int irqMask=  ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | ICR_RXO | ICR_RXT0 | ICR_RXCFG;
246 
247  for (sc= root_i82544EI_dev; sc; sc= sc-> next_module) {
248    CSR_WRITE(sc,WMREG_IMS,(CSR_READ(sc,WMREG_IMS)| irqMask) );
249    return;
250  }
251}
252
253static void i82544EI_irq_off(const rtems_irq_connect_data *irq)
254{
255  struct wm_softc *sc;
256  unsigned int irqMask=  ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | ICR_RXO | ICR_RXT0 |ICR_RXCFG ;
257
258  for (sc= root_i82544EI_dev; sc; sc= sc-> next_module) {
259    CSR_WRITE(sc,WMREG_IMS, (CSR_READ(sc,WMREG_IMS) & ~irqMask) );
260    return;
261  }
262}
263
264static int i82544EI_irq_is_on(const rtems_irq_connect_data *irq)
265{
266  return(CSR_READ(root_i82544EI_dev,WMREG_ICR) & root_i82544EI_dev->sc_icr);
267}
268
269static rtems_irq_connect_data i82544IrqData={
270        BSP_GPP_82544_IRQ,
271        (rtems_irq_hdl) i82544EI_isr,
272        (rtems_irq_enable) i82544EI_irq_on,
273        (rtems_irq_disable) i82544EI_irq_off,
274        (rtems_irq_is_enabled) i82544EI_irq_is_on,
275};
276
277int rtems_i82544EI_driver_attach(struct rtems_bsdnet_ifconfig *config, int attach)
278{
279  struct wm_softc *sc;
280  struct ifnet *ifp;
281  uint8_t enaddr[ETHER_ADDR_LEN];
282  uint16_t myea[ETHER_ADDR_LEN / 2], cfg1, cfg2, swdpin;
283  unsigned reg;
284  int b,d,f; /* PCI bus/device/function */
285  int unit;
286  void     *softc_mem;
287  char     *name;
288
289  unit = rtems_bsdnet_parse_driver_name(config, &name);
290  if (unit < 0) return 0;
291 
292  printk("\nEthernet driver name %s unit %d \n",name, unit);
293  printk("Copyright (c) 2004,2005 S. Kate Feng <feng1@bnl.gov> (RTEMS/mvme5500 port)\n");
294
295  /* Make sure certain elements e.g. descriptor lists are aligned.*/
296  softc_mem = rtems_bsdnet_malloc(sizeof(*sc) + SOFTC_ALIGN, M_FREE, M_NOWAIT);
297
298  /* Check for the very unlikely case of no memory. */
299  if (softc_mem == NULL)
300     rtems_panic("i82544EI: OUT OF MEMORY");
301
302  sc = (void *)(((long)softc_mem + SOFTC_ALIGN) & ~SOFTC_ALIGN);
303  memset(sc, 0, sizeof(*sc));
304
305  sprintf(sc->dv_xname, "%s%d", name, unit);
306
307  if (pci_find_device(PCI_VENDOR_ID_INTEL,PCI_DEVICE_INTEL_82544EI_COPPER,
308                        unit-1,&b, &d, &f))
309    rtems_panic("i82544EI device ID not found\n");
310
311#if WM_DEBUG
312  printk("82544EI:b%d, d%d, f%d\n", b, d,f);
313#endif
314
315  /* Memory-mapped acccess is required for normal operation.*/
316  if ( pci_mem_find(b,d,f,PCI_MAPREG_START, &sc->sc_membase, &sc->sc_memsize))
317     rtems_panic("i82544EI: unable to map memory space\n");
318
319#ifdef WM_DEBUG
320  printk("Memory base addr 0x%x\n", sc->sc_membase);
321  printk("txdesc[0] addr:0x%x, rxdesc[0] addr:0x%x, sizeof sc %d\n",&sc->sc_txdescs[0], &sc->sc_rxdescs[0], sizeof(*sc));     
322#endif
323
324
325  sc->sc_ctrl |=CSR_READ(sc,WMREG_CTRL); 
326  /*
327   * Determine a few things about the bus we're connected to.
328   */
329  reg = CSR_READ(sc,WMREG_STATUS);
330  if (reg & STATUS_BUS64) sc->sc_flags |= WM_F_BUS64;
331  sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33;
332#ifdef WM_DEBUG
333  printk("%s%d: %d-bit %dMHz PCI bus\n",name, unit,
334         (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed);
335#endif
336
337  /*
338   * Setup some information about the EEPROM.
339   */
340
341  sc->sc_ee_addrbits = 6;
342
343#ifdef WM_DEBUG
344  printk("%s%d: %u word (%d address bits) MicroWire EEPROM\n",
345            name, unit, 1U << sc->sc_ee_addrbits,
346            sc->sc_ee_addrbits);
347#endif
348
349  /*
350   * Read the Ethernet address from the EEPROM.
351   */
352  if (wm_read_eeprom(sc, EEPROM_OFF_MACADDR,
353            sizeof(myea) / sizeof(myea[0]), myea))
354     rtems_panic("i82544ei 1GHZ ethernet: unable to read Ethernet address");
355
356  enaddr[0] = myea[0] & 0xff;
357  enaddr[1] = myea[0] >> 8;
358  enaddr[2] = myea[1] & 0xff;
359  enaddr[3] = myea[1] >> 8;
360  enaddr[4] = myea[2] & 0xff;
361  enaddr[5] = myea[2] >> 8;
362
363
364  memcpy(sc->arpcom.ac_enaddr, enaddr, ETHER_ADDR_LEN);
365#ifdef WM_DEBUG
366  printk("%s: Ethernet address %s\n", sc->dv_xname,
367            ether_sprintf1(enaddr));
368#endif
369
370  /*
371   * Read the config info from the EEPROM, and set up various
372   * bits in the control registers based on their contents.
373   */
374  if (wm_read_eeprom(sc, EEPROM_OFF_CFG1, 1, &cfg1)) {
375     printk("%s: unable to read CFG1 from EEPROM\n",sc->dv_xname);
376     return(0);
377  }
378  if (wm_read_eeprom(sc, EEPROM_OFF_CFG2, 1, &cfg2)) {
379     printk("%s: unable to read CFG2 from EEPROM\n",sc->dv_xname);
380     return(0);
381  }
382  if (wm_read_eeprom(sc, EEPROM_OFF_SWDPIN, 1, &swdpin)) {
383     printk("%s: unable to read SWDPIN from EEPROM\n",sc->dv_xname);
384     return(0);
385  }
386
387  if (cfg1 & EEPROM_CFG1_ILOS) sc->sc_ctrl |= CTRL_ILOS;
388  sc->sc_ctrl|=((swdpin >> EEPROM_SWDPIN_SWDPIO_SHIFT) & 0xf) <<
389                CTRL_SWDPIO_SHIFT;
390  sc->sc_ctrl |= ((swdpin >> EEPROM_SWDPIN_SWDPIN_SHIFT) & 0xf) <<
391                CTRL_SWDPINS_SHIFT;
392
393  CSR_WRITE(sc,WMREG_CTRL, sc->sc_ctrl);
394#if 0
395  CSR_WRITE(sc,WMREG_CTRL_EXT, sc->sc_ctrl_ext);
396#endif
397
398  ifp = &sc->arpcom.ac_if;
399  /* set this interface's name and unit */
400  ifp->if_unit = unit;
401  ifp->if_name = name;
402  ifp->if_softc = sc;
403  ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
404  ifp->if_mtu = config->mtu ? config->mtu : ETHERMTU;
405  ifp->if_ioctl = wm_ioctl;
406  ifp->if_start = i82544EI_ifstart;
407  /*  ifp->if_watchdog = wm_watchdog;*/
408  ifp->if_init = i82544EI_ifinit;
409  if (ifp->if_snd.ifq_maxlen == 0)
410      ifp->if_snd.ifq_maxlen = ifqmaxlen;
411
412  ifp->if_output = ether_output;
413
414  /* create the synchronization semaphore */
415  if (RTEMS_SUCCESSFUL != rtems_semaphore_create(
416     rtems_build_name('I','G','H','Z'),0,0,0,&sc->daemonSync))
417     rtems_panic("i82544EI: semaphore creation failed");
418
419  sc->next_module = root_i82544EI_dev;
420  root_i82544EI_dev = sc;
421
422  /* Attach the interface. */
423  if_attach(ifp);
424  ether_ifattach(ifp);
425#ifdef WM_DEBUG
426  printk("82544EI: Ethernet driver has been attached (handle 0x%08x,ifp 0x%08x)\n",sc, ifp);
427#endif
428
429  return(1);
430}
431
432/*
433 * i82544EI_ifstart:            [ifnet interface function]
434 *
435 *      Start packet transmission on the interface.
436 */
437static void
438i82544EI_ifstart(struct ifnet *ifp)
439{
440  struct wm_softc *sc = ifp->if_softc;
441
442#ifdef WM_DEBUG
443  printk("i82544EI_ifstart(");
444#endif
445
446  if ((ifp->if_flags & IFF_RUNNING) == 0) {
447#ifdef WM_DEBUG
448     printk("IFF_RUNNING==0\n");
449#endif         
450     return;
451  }
452
453  ifp->if_flags |= IFF_OACTIVE;
454  rtems_event_send (sc->daemonTid, START_TRANSMIT_EVENT);
455#ifdef WM_DEBUG
456  printk(")\n");
457#endif
458}
459
460static void i82544EI_stats(struct wm_softc *sc)
461{
462  struct ifnet *ifp = &sc->arpcom.ac_if;
463
464  printf("       Rx Interrupts:%-8u\n", sc->stats.rxInterrupts);
465  printf("     Receive Packets:%-8u\n", CSR_READ(sc,WMREG_GPRC));
466  printf("     Receive Overrun:%-8u\n", sc->stats.rxOvrRunInterrupts);
467  printf("     Receive  errors:%-8u\n", CSR_READ(sc,WMREG_RXERRC));
468  printf("   Rx sequence error:%-8u\n", sc->stats.rxSeqErr);
469  printf("      Rx /C/ ordered:%-8u\n", sc->stats.rxC_ordered);
470  printf("    Rx Length Errors:%-8u\n", CSR_READ(sc,WMREG_RLEC));
471  printf("       Tx Interrupts:%-8u\n", sc->stats.txInterrupts);
472#if 0
473  printf("Multi-BuffTx Packets:%-8u\n", sc->stats.txMultiBuffPacket);
474  printf("Multi-BuffTx max len:%-8u\n", sc->stats.txMultiMaxLen);
475  printf("SingleBuffTx max len:%-8u\n", sc->stats.txSinglMaxLen);
476  printf("Multi-BuffTx maxloop:%-8u\n", sc->stats.txMultiMaxLoop);
477  printf("Tx buffer max len   :%-8u\n", sc->stats.txBuffMaxLen);
478#endif
479  printf("   Transmitt Packets:%-8u\n", CSR_READ(sc,WMREG_GPTC));
480  printf("   Transmitt  errors:%-8u\n", ifp->if_oerrors);
481  printf("         Active Txqs:%-8u\n", sc->txq_nactive);
482  printf("          collisions:%-8u\n", CSR_READ(sc,WMREG_COLC));
483  printf("          Crc Errors:%-8u\n", CSR_READ(sc,WMREG_CRCERRS));
484  printf("  Link Status Change:%-8u\n", sc->stats.linkStatusChng);
485}
486
487/*
488 * wm_ioctl:            [ifnet interface function]
489 *
490 *      Handle control requests from the operator.
491 */
492static int wm_ioctl(struct ifnet *ifp, u_long cmd,uint32_t data)
493{
494  struct wm_softc *sc = ifp->if_softc;
495  int error=0;
496
497  switch (cmd) {
498    default:
499      error = ether_ioctl(ifp, cmd, data);
500      if (error == ENETRESET) {
501          /*
502           * Multicast list has changed; set the hardware filter
503           * accordingly.
504           */
505          wm_set_filter(sc);
506          error = 0;
507      }
508      break;
509    case SIO_RTEMS_SHOW_STATS:
510      i82544EI_stats(sc);
511      break;
512  }
513
514  /* Try to get more packets going.*/
515  i82544EI_ifstart(ifp);
516  return (error);
517}
518
519/*
520 * wm_isr:
521 *
522 *      Interrupt service routine.
523 */
524static void i82544EI_isr()
525{
526  volatile struct wm_softc *sc = root_i82544EI_dev;
527  uint32_t icr;
528  rtems_event_set  events=0;
529
530  /* Reading the WMREG_ICR clears the interrupt bits */
531  icr = CSR_READ(sc,WMREG_ICR);
532
533  if ( icr & (ICR_RXDMT0|ICR_RXT0)) {
534     sc->stats.rxInterrupts++;
535     events |= RX_EVENT;
536  }
537
538  if (icr & ICR_TXDW) {
539     sc->stats.txInterrupts++;
540     events |= TX_EVENT;
541  }
542  /* <SKF> Rx overrun : no available receive buffer
543   * or PCI receive bandwidth inadequate.
544   */
545  if (icr & ICR_RXO) {
546     sc->stats.rxOvrRunInterrupts++;
547     events |= INIT_EVENT;
548  }
549  if (icr & ICR_RXSEQ) /* framing error */ {
550     sc->intr_errsts[sc->intr_err_ptr2++]=icr;
551     sc->intr_err_ptr2 %=INTR_ERR_SIZE; /* Till Straumann */
552     events |= ERR_EVENT;
553     sc->stats.rxSeqErr++;
554  }
555  if ( !icr) sc->stats.ghostInterrupts++;
556
557  if (icr & ICR_LSC) sc->stats.linkStatusChng++;
558  if (icr & ICR_RXCFG) sc->stats.rxC_ordered++;
559
560  rtems_event_send(sc->daemonTid, events);
561}
562
563/*
564 * i82544EI_sendpacket:
565 *
566 *      Helper; handle transmit interrupts.
567 */
568static void i82544EI_sendpacket(struct wm_softc *sc, struct mbuf *m)
569{
570
571#ifdef WM_DEBUG_TX
572  printk("sendpacket(");
573#endif
574
575  if ( !(m->m_next)) { /* single buffer packet */
576    sc->txs_mbuf[sc->txq_next]= m;
577    /* Note: we currently only use 32-bit DMA addresses. */
578    sc->sc_txdescs[sc->txq_next].wtx_addr.wa_low = htole32(mtod(m, void*));
579    sc->sc_txdescs[sc->txq_next].wtx_cmdlen =htole32(TxDescCmd | m->m_len);
580    sc->txs_lastdesc= sc->txq_next;
581    sc->txq_next = WM_NEXTTX(sc->txq_next);
582    sc->txq_nactive++;
583    sc->txq_free--;
584  }
585  else /* multiple mbufs in this packet */
586  {
587    struct mbuf *mtp, *mdest;
588    volatile unsigned char *pt;
589    int len, y, loop=0;
590
591#ifdef WM_DEBUG_TX
592    printk("multi mbufs ");
593#endif
594    mtp = m;
595    while ( mtp) {
596      MGETHDR(mdest, M_WAIT, MT_DATA);
597      MCLGET(mdest, M_WAIT);
598      pt = (volatile unsigned char *)mdest->m_data;
599      for ( len=0;mtp;mtp=mtp->m_next) {
600        loop++;
601        /* Each descriptor gets a 2k (MCLBYTES) buffer, although
602         * the length of each descriptor can be up to 16288 bytes.
603         * For packets which fill more than one buffer ( >2k), we
604         * chain them together.
605         * <Kate Feng> : This effective for packets > 2K
606         * The other way is effective for packets < 2K
607         */
608        if ( ((y=(len+mtp->m_len)) > sizeof(union mcluster))) {
609          printk(">2048, use next descriptor\n");
610          break;
611        }
612        memcpy((void *)pt,(char *)mtp->m_data, mtp->m_len);
613        pt += mtp->m_len;
614        len += mtp->m_len;
615#if 0
616        sc->stats.txSinglMaxLen= MAX(mtp->m_len, sc->stats.txSinglMaxLen);
617#endif
618      } /* end for loop */
619      mdest->m_len=len;
620      sc->txs_mbuf[sc->txq_next] = mdest;
621      /* Note: we currently only use 32-bit DMA addresses. */
622      sc->sc_txdescs[sc->txq_next].wtx_addr.wa_low = htole32(mtod(mdest, void*));
623      sc->sc_txdescs[sc->txq_next].wtx_cmdlen = htole32(TxDescCmd|mdest->m_len);
624      sc->txs_lastdesc = sc->txq_next;
625      sc->txq_next = WM_NEXTTX(sc->txq_next);
626      sc->txq_nactive ++;
627      if (sc->txq_free)
628         sc->txq_free--;
629      else
630         rtems_panic("i8254EI : no more free descriptors");
631#if 0
632      sc->stats.txMultiMaxLen= MAX(mdest->m_len, sc->stats.txMultiMaxLen);
633      sc->stats.txMultiBuffPacket++;
634#endif
635    } /* end for while */
636    /* free old mbuf chain */
637#if 0
638    sc->stats.txMultiMaxLoop=MAX(loop, sc->stats.txMultiMaxLoop);
639#endif
640    m_freem(m);
641    m=0;
642  }  /* end  multiple mbufs */
643   
644  DPRINTF(WM_DEBUG_TX,("%s: TX: desc %d: cmdlen 0x%08x\n", sc->dv_xname,
645         sc->txs_lastdesc, le32toh(sc->sc_txdescs[sc->txs_lastdesc].wtx_cmdlen)));
646  DPRINTF(WM_DEBUG_TX,("status 0x%08x\n",sc->sc_txdescs[sc->txq_fi].wtx_fields.wtxu_status));
647
648  memBar();
649
650  /* This is the location where software writes the first NEW descriptor */
651  CSR_WRITE(sc,WMREG_TDT, sc->txq_next);
652
653  DPRINTF(WM_DEBUG_TX,("%s: addr 0x%08x, TX: TDH %d, TDT %d\n",sc->dv_xname,
654  le32toh(sc->sc_txdescs[sc->txs_lastdesc].wtx_addr.wa_low), CSR_READ(sc,WMREG_TDH),
655          CSR_READ(sc,WMREG_TDT)));
656
657  DPRINTF(WM_DEBUG_TX,("%s: TX: finished transmitting packet, job %d\n",
658                    sc->dv_xname, sc->txq_next));
659
660}
661
662static void i82544EI_txq_free(struct wm_softc *sc, uint8_t status)
663{
664  struct ifnet *ifp = &sc->arpcom.ac_if;
665
666  /* We might use the statistics registers instead of variables
667   * to keep tack of the network statistics
668   */
669
670  /* statistics */
671  ifp->if_opackets++;
672
673  if (status & (WTX_ST_EC|WTX_ST_LC)) {
674       ifp->if_oerrors++;
675
676     if (status & WTX_ST_LC) 
677        printf("%s: late collision\n", sc->dv_xname);
678     else if (status & WTX_ST_EC) {
679        ifp->if_collisions += 16;
680         printf("%s: excessive collisions\n", sc->dv_xname);
681     }
682  }
683  /* Free the original mbuf chain */
684  m_freem(sc->txs_mbuf[sc->txq_fi]);
685  sc->txs_mbuf[sc->txq_fi] = 0;
686  sc->sc_txdescs[sc->txq_fi].wtx_fields.wtxu_status=0;
687
688  sc->txq_free ++;
689  sc->txq_fi = WM_NEXTTX(sc->txq_fi);
690  --sc->txq_nactive;
691}
692
693static void i82544EI_txq_done(struct wm_softc *sc)
694{
695  uint8_t status;
696
697  /*
698   * Go through the Tx list and free mbufs for those
699   * frames which have been transmitted.
700   */
701  while ( sc->txq_nactive > 0) {
702    status = sc->sc_txdescs[sc->txq_fi].wtx_fields.wtxu_status;
703    if ((status & WTX_ST_DD) == 0) break;
704    i82544EI_txq_free(sc, status);
705    DPRINTF(WM_DEBUG_TX,("%s: TX: job %d done\n",
706                    sc->dv_xname, sc->txq_fi));
707  }
708}
709
710static void wm_init_rxdesc(struct wm_softc *sc, int x) 
711{                       
712  wiseman_rxdesc_t *__rxd = &(sc)->sc_rxdescs[(x)];             
713  struct mbuf *m;
714
715  m = sc->rxs_mbuf[x];
716               
717  __rxd->wrx_addr.wa_low=htole32(mtod(m, void*)); 
718  __rxd->wrx_addr.wa_high = 0;                                 
719  __rxd->wrx_len = 0;                                             
720  __rxd->wrx_cksum = 0;                                           
721  __rxd->wrx_status = 0;                                               
722  __rxd->wrx_errors = 0;                                         
723  __rxd->wrx_special = 0;                                         
724  /* Receive Descriptor Tail: add Rx desc. to H/W free list */   
725  CSR_WRITE(sc,WMREG_RDT, (x));                                         
726}
727
728static void i82544EI_rx(struct wm_softc *sc)
729{
730  struct ifnet *ifp = &sc->arpcom.ac_if;
731  struct mbuf *m;
732  int i, len;
733  uint8_t status, errors;
734  struct ether_header *eh;
735
736#ifdef WM_DEBUG
737  printk("i82544EI_rx()\n");
738#endif
739
740  for (i = sc->sc_rxptr;; i = WM_NEXTRX(i)) {
741    DPRINTF(WM_DEBUG_RX, ("%s: RX: checking descriptor %d\n",
742                    sc->dv_xname, i));
743
744    status = sc->sc_rxdescs[i].wrx_status;
745    errors = sc->sc_rxdescs[i].wrx_errors;
746    len = le16toh(sc->sc_rxdescs[i].wrx_len);
747    m = sc->rxs_mbuf[i];
748
749    if ((status & WRX_ST_DD) == 0)  break; /* descriptor not done */
750
751    if (sc->sc_rxdiscard) {
752       printk("RX: discarding contents of descriptor %d\n", i);
753       wm_init_rxdesc(sc, i);
754       if (status & WRX_ST_EOP) {
755          /* Reset our state. */
756          printk("RX: resetting rxdiscard -> 0\n");
757          sc->sc_rxdiscard = 0;
758       }
759       continue;
760    }
761
762    /*
763     * If an error occurred, update stats and drop the packet.
764     */
765    if (errors &(WRX_ER_CE|WRX_ER_SE|WRX_ER_SEQ|WRX_ER_CXE|WRX_ER_RXE)) {
766       ifp->if_ierrors++;
767       if (errors & WRX_ER_SE)
768          printk("%s: symbol error\n",sc->dv_xname);
769       else if (errors & WRX_ER_SEQ)
770          printk("%s: receive sequence error\n",sc->dv_xname);
771            else if (errors & WRX_ER_CE)
772                 printk("%s: CRC error\n",sc->dv_xname);
773       m_freem(m);
774       goto give_it_back;
775    }
776
777    /*
778     * No errors.  Receive the packet.
779     *
780     * Note, we have configured the chip to include the
781     * CRC with every packet.
782     */
783    m->m_len = m->m_pkthdr.len = len - sizeof(struct ether_header);
784
785    DPRINTF(WM_DEBUG_RX,("%s: RX: buffer at %p len %d\n",
786                    sc->dv_xname, m->m_data, len));
787
788
789    eh = mtod (m, struct ether_header *);
790    m->m_data += sizeof(struct ether_header);
791    ether_input (ifp, eh, m);
792    /* Pass it on. */
793    ifp->if_ipackets++;
794   
795    give_it_back:
796    /* Add a new receive buffer to the ring.*/
797    if (wm_add_rxbuf(sc, i) != 0) {
798       /*
799        * Failed, throw away what we've done so
800        * far, and discard the rest of the packet.
801        */
802       printk("Failed in wm_add_rxbuf(), drop packet\n");
803       ifp->if_ierrors++;
804       wm_init_rxdesc(sc, i);
805       if ((status & WRX_ST_EOP) == 0)
806          sc->sc_rxdiscard = 1;
807       m_freem(m);
808    }
809  } /* end for */
810
811  /* Update the receive pointer. */
812  sc->sc_rxptr = i;
813  DPRINTF(WM_DEBUG_RX, ("%s: RX: rxptr -> %d\n", sc->dv_xname, i));
814}
815
816static int i82544EI_init_hw(struct wm_softc *sc)
817{
818  struct ifnet *ifp = &sc->arpcom.ac_if;
819  int i,error;
820  uint8_t cksumfields;
821
822  /* Cancel any pending I/O. */
823  wm_stop(ifp, 0);
824
825  /* Initialize the error buffer ring */
826  sc->intr_err_ptr1=0;
827  sc->intr_err_ptr2=0;
828  for (i=0; i< INTR_ERR_SIZE; i++) sc->intr_errsts[i]=0;
829
830  /* Initialize the transmit descriptor ring. */
831  memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
832  sc->txq_free = NTXDESC;
833  sc->txq_next = 0;
834  sc->txs_lastdesc = 0;
835  sc->txq_next = 0;
836  sc->txq_free = NTXDESC;
837  sc->txq_nactive = 0;
838
839  sc->sc_txctx_ipcs = 0xffffffff;
840  sc->sc_txctx_tucs = 0xffffffff;
841
842  CSR_WRITE(sc,WMREG_TBDAH, 0);
843  CSR_WRITE(sc,WMREG_TBDAL, WM_CDTXADDR(sc));
844#ifdef WM_DEBUG
845  printk("TBDAL 0x%x, TDLEN %d\n", WM_CDTXADDR(sc), sizeof(sc->sc_txdescs));
846#endif
847  CSR_WRITE(sc,WMREG_TDLEN, sizeof(sc->sc_txdescs));
848  CSR_WRITE(sc,WMREG_TDH, 0);
849  CSR_WRITE(sc,WMREG_TDT, 0);
850  CSR_WRITE(sc,WMREG_TIDV, 64 );
851  CSR_WRITE(sc,WMREG_TADV, 128);
852
853  CSR_WRITE(sc,WMREG_TXDCTL, TXDCTL_PTHRESH(0) |
854                    TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0));
855  CSR_WRITE(sc,WMREG_RXDCTL, RXDCTL_PTHRESH(0) |
856                    RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1) | RXDCTL_GRAN );
857
858  CSR_WRITE(sc,WMREG_TQSA_LO, 0);
859  CSR_WRITE(sc,WMREG_TQSA_HI, 0);
860
861  /*
862   * Set up checksum offload parameters for
863   * this packet.
864   */
865#ifdef CKSUM_OFFLOAD
866  if (m0->m_pkthdr.csum_flags &
867     (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) {
868     if (wm_tx_cksum(sc, txs, &TxDescCmd,&cksumfields) != 0) {
869         /* Error message already displayed. */
870         continue;
871     }
872  } else {
873#endif
874     TxDescCmd = 0;
875     cksumfields = 0;
876#ifdef CKSUM_OFFLOAD
877  }
878#endif
879
880  TxDescCmd |= WTX_CMD_EOP|WTX_CMD_IFCS|WTX_CMD_RS;
881
882  /* Initialize the transmit job descriptors. */
883  for (i = 0; i < NTXDESC; i++) {
884      sc->txs_mbuf[i] = 0;
885      sc->sc_txdescs[i].wtx_fields.wtxu_options=cksumfields;
886      sc->sc_txdescs[i].wtx_addr.wa_high = 0;
887      sc->sc_txdescs[i].wtx_addr.wa_low = 0;
888      sc->sc_txdescs[i].wtx_cmdlen = htole32(TxDescCmd);
889  }
890
891  /*
892   * Initialize the receive descriptor and receive job
893   * descriptor rings.
894   */
895  memset(sc->sc_rxdescs, 0, sizeof(sc->sc_rxdescs));
896  CSR_WRITE(sc,WMREG_RDBAH, 0);
897  CSR_WRITE(sc,WMREG_RDBAL, WM_CDRXADDR(sc));
898  CSR_WRITE(sc,WMREG_RDLEN, sizeof(sc->sc_rxdescs));
899  CSR_WRITE(sc,WMREG_RDH, 0);
900  CSR_WRITE(sc,WMREG_RDT, 0);
901  CSR_WRITE(sc,WMREG_RDTR, 0 |RDTR_FPD);
902  CSR_WRITE(sc, WMREG_RADV, 256);
903
904  for (i = 0; i < NRXDESC; i++) {
905      if (sc->rxs_mbuf[i] == NULL) {
906         if ((error = wm_add_rxbuf(sc, i)) != 0) {
907            printk("%s%d: unable to allocate or map rx buffer"
908            "%d, error = %d\n",ifp->if_name,ifp->if_unit, i, error);
909            /*
910             * XXX Should attempt to run with fewer receive
911             * XXX buffers instead of just failing.
912             */
913            wm_rxdrain(sc);
914            return(error);
915          }
916      } else {
917        printk("sc->rxs_mbuf[%d] not NULL.\n", i);
918        wm_init_rxdesc(sc, i);
919      }
920  }
921  sc->sc_rxptr = 0;
922  sc->sc_rxdiscard = 0;
923
924  /*
925   * Clear out the VLAN table -- we don't use it (yet).
926   */
927  CSR_WRITE(sc,WMREG_VET, 0);
928  for (i = 0; i < WM_VLAN_TABSIZE; i++)
929       CSR_WRITE(sc,WMREG_VFTA + (i << 2), 0);
930
931  /*
932   * Set up flow-control parameters.
933   *
934   * XXX Values could probably stand some tuning.
935   */
936  CSR_WRITE(sc,WMREG_FCAL, FCAL_CONST);/*safe,even though MOTLOAD 0x00c28001 */
937  CSR_WRITE(sc,WMREG_FCAH, FCAH_CONST);/*safe,even though MOTLOAD 0x00000100 */
938  CSR_WRITE(sc,WMREG_FCT, ETHERTYPE_FLOWCONTROL);/*safe,even though MOTLoad 0x8808 */
939
940
941  /* safe,even though MOTLoad default all 0 */
942  sc->sc_fcrtl = FCRTL_DFLT;
943
944  CSR_WRITE(sc,WMREG_FCRTH, FCRTH_DFLT);
945  CSR_WRITE(sc,WMREG_FCRTL, sc->sc_fcrtl);
946  CSR_WRITE(sc,WMREG_FCTTV, FCTTV_DFLT);
947
948  sc->sc_ctrl &= ~CTRL_VME;
949  /*sc->sc_ctrl |= CTRL_TFCE | CTRL_RFCE;*/
950  /* enable Big Endian Mode for the powerPC
951  sc->sc_ctrl |= CTRL_BEM;*/
952
953  /* Write the control registers. */
954  CSR_WRITE(sc,WMREG_CTRL, sc->sc_ctrl);
955#if 0
956  CSR_WRITE(sc,WMREG_CTRL_EXT, sc->sc_ctrl_ext);
957#endif
958
959  /* MOTLoad : WMREG_RXCSUM (0x5000)= 0, no Rx checksum offloading */ 
960
961  /*
962   * Set up the interrupt registers.
963   */
964  CSR_WRITE(sc,WMREG_IMC, 0xffffffffU);
965  /* Reading the WMREG_ICR clears the interrupt bits */
966  CSR_READ(sc,WMREG_ICR);
967
968  /*  printf("WMREG_IMS 0x%x\n", CSR_READ(sc,WMREG_IMS));*/
969
970  sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXCFG | ICR_RXDMT0 | ICR_RXO | ICR_RXT0;
971
972  CSR_WRITE(sc,WMREG_IMS, sc->sc_icr);
973
974  /* Set up the inter-packet gap. */
975  CSR_WRITE(sc,WMREG_TIPG, sc->sc_tipg);
976
977#if 0 /* XXXJRT */
978  /* Set the VLAN ethernetype. */
979  CSR_WRITE(sc,WMREG_VET, ETHERTYPE_VLAN);
980#endif
981
982  /*
983   * Set up the transmit control register; we start out with
984   * a collision distance suitable for FDX, but update it when
985   * we resolve the media type.
986   */
987  sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_CT(TX_COLLISION_THRESHOLD) |
988            TCTL_COLD(TX_COLLISION_DISTANCE_FDX) | TCTL_RTLC; /*transmitter enable*/
989
990  /*
991   * Set up the receive control register; we actually program
992   * the register when we set the receive filter.  Use multicast
993   * address offset type 0.
994   *
995   * Only the i82544 has the ability to strip the incoming
996   * CRC, so we don't enable that feature. (TODO)
997   */
998  sc->sc_mchash_type = 0;
999  sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_LPE |
1000            RCTL_DPF | RCTL_MO(sc->sc_mchash_type);
1001
1002  /* (MCLBYTES == 2048) */
1003  sc->sc_rctl |= RCTL_2k;
1004
1005#ifdef WM_DEBUG
1006  printk("RDBAL 0x%x,RDLEN %d, RDT %d\n",CSR_READ(sc,WMREG_RDBAL),CSR_READ(sc,WMREG_RDLEN), CSR_READ(sc,WMREG_RDT));
1007#endif
1008
1009  /* Set the receive filter. */
1010  wm_set_filter(sc);
1011
1012  CSR_WRITE(sc,WMREG_TCTL, sc->sc_tctl);
1013
1014  /* Map and establish our interrupt. */
1015  if (!BSP_install_rtems_irq_handler(&i82544IrqData))
1016     rtems_panic("1GHZ ethernet: unable to install ISR");
1017
1018  return(0);
1019}
1020
1021/*
1022 * i82544EI_ifinit:             [ifnet interface function]
1023 *
1024 *      Initialize the interface.
1025 */
1026static void i82544EI_ifinit(void *arg)
1027{
1028  struct wm_softc *sc = (struct wm_softc*)arg;
1029
1030#ifdef WM_DEBUG
1031  printk("i82544EI_ifinit(): daemon ID: 0x%08x)\n", sc->daemonTid);
1032#endif
1033  if (sc->daemonTid) {
1034#ifdef WM_DEBUG
1035     printk("i82544EI: daemon already up, doing nothing\n");
1036#endif
1037     return;
1038  }
1039  i82544EI_init_hw(sc);
1040
1041  sc->daemonTid = rtems_bsdnet_newproc(i82544EI_TASK_NAME,4096,i82544EI_daemon,arg);
1042
1043  /* ...all done! */
1044  sc->arpcom.ac_if.if_flags |= IFF_RUNNING;
1045
1046#ifdef WM_DEBUG
1047  printk(")");
1048#endif
1049}
1050
1051/*
1052 * wm_txdrain:
1053 *
1054 *      Drain the transmit queue.
1055 */
1056static void wm_txdrain(struct wm_softc *sc)
1057{
1058  int i;
1059
1060  /* Release any queued transmit buffers. */
1061  for (i = 0; i <  NTXDESC; i++) {
1062      if (sc->txs_mbuf[i] != NULL) {
1063          m_freem(sc->txs_mbuf[i]);
1064          sc->txs_mbuf[i] = NULL;
1065      }
1066  }
1067}
1068
1069/*
1070 * wm_rxdrain:
1071 *
1072 *      Drain the receive queue.
1073 */
1074static void wm_rxdrain(struct wm_softc *sc)
1075{
1076  int i;
1077
1078  for (i = 0; i < NRXDESC; i++) {
1079      if (sc->rxs_mbuf[i] != NULL) {
1080          m_freem(sc->rxs_mbuf[i]);
1081          sc->rxs_mbuf[i] = NULL;
1082      }
1083  }
1084}
1085
1086static void i82544EI_tx_stop(struct wm_softc *sc)
1087{
1088  wm_txdrain(sc);
1089}
1090
1091static void i82544EI_rx_stop(struct wm_softc *sc)
1092{
1093  wm_rxdrain(sc);
1094}
1095
1096static void i82544EI_stop_hw(struct wm_softc *sc)
1097{
1098#ifdef WM_DEBUG
1099  printk("i82544EI_stop_hw(");
1100#endif
1101
1102  /* remove our interrupt handler which will also
1103  * disable interrupts at the MPIC and the device
1104  * itself
1105  */
1106  if (!BSP_remove_rtems_irq_handler(&i82544IrqData))
1107     rtems_panic("i82544EI: unable to remove IRQ handler!");
1108
1109  CSR_WRITE(sc,WMREG_IMS, 0);
1110
1111  sc->arpcom.ac_if.if_flags &= ~IFF_RUNNING;
1112  i82544EI_tx_stop(sc);
1113  i82544EI_rx_stop(sc);
1114#ifdef WM_DEBUG
1115  printk(")");
1116#endif
1117}
1118
1119/*
1120 * wm_stop:             [ifnet interface function]
1121 *
1122 *      Stop transmission on the interface.
1123 */
1124static void wm_stop(struct ifnet *ifp, int disable)
1125{
1126  struct wm_softc *sc = ifp->if_softc;
1127
1128#ifdef WM_DEBUG
1129  printk("wm_stop(");
1130#endif 
1131  /* Stop the transmit and receive processes. */
1132  CSR_WRITE(sc,WMREG_TCTL, 0);
1133  CSR_WRITE(sc,WMREG_RCTL, 0);
1134
1135  wm_txdrain(sc);
1136  wm_rxdrain(sc);
1137
1138  /* Mark the interface as down  */
1139  ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1140#ifdef WM_DEBUG
1141  printk(")\n");
1142#endif 
1143}
1144
1145/*
1146 * wm_eeprom_sendbits:
1147 *
1148 *      Send a series of bits to the EEPROM.
1149 */
1150static void wm_eeprom_sendbits(struct wm_softc *sc, uint32_t bits, int nbits)
1151{
1152  uint32_t reg;
1153  int x;
1154
1155  reg = CSR_READ(sc,WMREG_EECD);
1156
1157  for (x = nbits; x > 0; x--) {
1158      if (bits & (1U << (x - 1)))
1159         reg |= EECD_DI;
1160      else
1161         reg &= ~EECD_DI;
1162      CSR_WRITE(sc,WMREG_EECD, reg);
1163      rtems_bsp_delay(2);
1164      CSR_WRITE(sc,WMREG_EECD, reg | EECD_SK);
1165      rtems_bsp_delay(2);
1166      CSR_WRITE(sc,WMREG_EECD, reg);
1167      rtems_bsp_delay(2);
1168  }
1169}
1170
1171/*
1172 * wm_eeprom_recvbits:
1173 *
1174 *      Receive a series of bits from the EEPROM.
1175 */
1176static void wm_eeprom_recvbits(struct wm_softc *sc, uint32_t *valp, int nbits)
1177{
1178  uint32_t reg, val;
1179  int x;
1180
1181  reg = CSR_READ(sc,WMREG_EECD) & ~EECD_DI;
1182
1183  val = 0;
1184  for (x = nbits; x > 0; x--) {
1185      CSR_WRITE(sc,WMREG_EECD, reg | EECD_SK);
1186      rtems_bsp_delay(2);
1187      if (CSR_READ(sc,WMREG_EECD) & EECD_DO)
1188         val |= (1U << (x - 1));
1189      CSR_WRITE(sc,WMREG_EECD, reg);
1190      rtems_bsp_delay(2);
1191  }
1192  *valp = val;
1193}
1194
1195/*
1196 * wm_read_eeprom_uwire:
1197 *
1198 * Read a word from the EEPROM using the MicroWire protocol.
1199 *
1200 * (The 82544EI Gigabit Ethernet Controller is compatible with
1201 * most MicroWire interface, serial EEPROM devices.)
1202 */
1203static int wm_read_eeprom_uwire(struct wm_softc *sc, int word, int wordcnt, uint16_t *data)
1204{
1205  uint32_t reg, val;
1206  int i;
1207
1208  for (i = 0; i < wordcnt; i++) {
1209      /* Clear SK and DI. */
1210      reg = CSR_READ(sc,WMREG_EECD) & ~(EECD_SK | EECD_DI);
1211      CSR_WRITE(sc,WMREG_EECD, reg);
1212
1213      /* Set CHIP SELECT. */
1214      reg |= EECD_CS;
1215      CSR_WRITE(sc,WMREG_EECD, reg);
1216      rtems_bsp_delay(2);
1217
1218      /* Shift in the READ command. */
1219      wm_eeprom_sendbits(sc, UWIRE_OPC_READ, 3);
1220
1221      /* Shift in address. */
1222      wm_eeprom_sendbits(sc, word + i, sc->sc_ee_addrbits);
1223
1224      /* Shift out the data. */
1225      wm_eeprom_recvbits(sc, &val, 16);
1226      data[i] = val & 0xffff;
1227
1228      /* Clear CHIP SELECT. */
1229      reg = CSR_READ(sc,WMREG_EECD) & ~EECD_CS;
1230      CSR_WRITE(sc,WMREG_EECD, reg);
1231      rtems_bsp_delay(2);
1232  }
1233  return (0);
1234}
1235
1236/*
1237 * wm_acquire_eeprom:
1238 *
1239 *      Perform the EEPROM handshake required on some chips.
1240 */
1241static int wm_acquire_eeprom(struct wm_softc *sc)
1242{
1243  uint32_t reg;
1244  int x;
1245
1246  reg = CSR_READ(sc,WMREG_EECD);
1247
1248  /* Request EEPROM access. */
1249  reg |= EECD_EE_REQ;
1250  CSR_WRITE(sc,WMREG_EECD, reg);
1251
1252  /* ..and wait for it to be granted. */
1253  for (x = 0; x < 100; x++) {
1254      reg = CSR_READ(sc,WMREG_EECD);
1255      if (reg & EECD_EE_GNT) break;
1256      rtems_bsp_delay(500);
1257  }
1258  if ((reg & EECD_EE_GNT) == 0) {
1259      printk("Could not acquire EEPROM GNT x= %d\n", x);
1260      reg &= ~EECD_EE_REQ;
1261      CSR_WRITE(sc,WMREG_EECD, reg);
1262      return (1);
1263  }
1264
1265  return (0);
1266}
1267
1268/*
1269 * wm_read_eeprom:
1270 *
1271 * Read data from the serial EEPROM.
1272 * 82544EI does not Perform the EEPROM handshake
1273 */
1274static int wm_read_eeprom(struct wm_softc *sc, int word, int wordcnt, uint16_t *data)
1275{
1276#if 0
1277  /* base on the datasheet, this does not seem to be applicable */
1278  if (wm_acquire_eeprom(sc))
1279     return(1);
1280#endif
1281  return(wm_read_eeprom_uwire(sc, word, wordcnt, data));
1282}
1283
1284/*
1285 * wm_add_rxbuf:
1286 *
1287 *      Add a receive buffer to the indiciated descriptor.
1288 */
1289static int wm_add_rxbuf(struct wm_softc *sc, int idx)
1290{
1291  struct mbuf *m;
1292
1293  MGETHDR(m, M_WAIT, MT_DATA);
1294  if (m == NULL) return (ENOBUFS);
1295  MCLGET(m, M_WAIT);
1296  if ((m->m_flags & M_EXT) == 0) {
1297     m_freem(m);
1298     return (ENOBUFS);
1299  }
1300  m->m_pkthdr.rcvif =  &sc->arpcom.ac_if;
1301  sc->rxs_mbuf[idx] = m;
1302  /*  m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;*/
1303  wm_init_rxdesc(sc, idx);
1304#if 0
1305  printk("sc->rxs_mbuf[%d]= 0x%x, mbuf @ 0x%x\n",
1306    idx, sc->rxs_mbuf[idx], le32toh(sc->sc_rxdescs[idx].wrx_addr.wa_low));
1307#endif
1308  return(0);
1309}
1310
1311/*
1312 * wm_set_ral:
1313 *
1314 *      Set an entery in the receive address list.
1315 */
1316static void
1317wm_set_ral(struct wm_softc *sc, const uint8_t *enaddr, int idx)
1318{
1319  uint32_t ral_lo, ral_hi;
1320
1321  if (enaddr != NULL) {
1322     ral_lo = enaddr[0]|(enaddr[1] << 8)|(enaddr[2] << 16)|(enaddr[3] << 24);
1323     ral_hi = enaddr[4] | (enaddr[5] << 8);
1324     ral_hi |= RAL_AV;
1325  } else {
1326     ral_lo = 0;
1327     ral_hi = 0;
1328  }
1329
1330  CSR_WRITE(sc,WMREG_RAL_LO(WMREG_CORDOVA_RAL_BASE, idx),ral_lo);
1331  CSR_WRITE(sc,WMREG_RAL_HI(WMREG_CORDOVA_RAL_BASE, idx),ral_hi);
1332}
1333
1334/*
1335 * wm_mchash:
1336 *
1337 *      Compute the hash of the multicast address for the 4096-bit
1338 *      multicast filter.
1339 */
1340static uint32_t
1341wm_mchash(struct wm_softc *sc, const uint8_t *enaddr)
1342{
1343  static const int lo_shift[4] = { 4, 3, 2, 0 };
1344  static const int hi_shift[4] = { 4, 5, 6, 8 };
1345  uint32_t hash;
1346
1347  hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) |
1348            (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]);
1349
1350  return (hash & 0xfff);
1351}
1352
1353/*
1354 * wm_set_filter: Set up the receive filter.
1355 */
1356static void wm_set_filter(struct wm_softc *sc)
1357{
1358  struct ifnet *ifp = &sc->arpcom.ac_if;
1359  struct ether_multi *enm;
1360  struct ether_multistep step;
1361  uint32_t mta_reg;
1362  uint32_t hash, reg, bit;
1363  int i;
1364
1365#ifdef WM_DEBUG
1366  printk("wm_set_filter(");
1367#endif 
1368  mta_reg = WMREG_CORDOVA_MTA;
1369  sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE);
1370
1371  /*  if (ifp->if_flags & IFF_BROADCAST)*/
1372     sc->sc_rctl |= RCTL_BAM;
1373  if (ifp->if_flags & IFF_PROMISC) {
1374     sc->sc_rctl |= RCTL_UPE;
1375     goto allmulti;
1376  }
1377
1378  /*
1379   * Set the station address in the first RAL slot, and
1380   * clear the remaining slots.
1381   */
1382  wm_set_ral(sc, sc->arpcom.ac_enaddr, 0);
1383  for (i = 1; i < WM_RAL_TABSIZE; i++)
1384      wm_set_ral(sc, NULL, i);
1385
1386  /* Clear out the multicast table. */
1387  for (i = 0; i < WM_MC_TABSIZE; i++)
1388      CSR_WRITE(sc,mta_reg + (i << 2), 0);
1389
1390  ETHER_FIRST_MULTI(step, &sc->arpcom, enm);
1391  while (enm != NULL) {
1392        if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
1393            /*
1394             * We must listen to a range of multicast addresses.
1395             * For now, just accept all multicasts, rather than
1396             * trying to set only those filter bits needed to match
1397             * the range.  (At this time, the only use of address
1398             * ranges is for IP multicast routing, for which the
1399             * range is big enough to require all bits set.)
1400             */
1401            goto allmulti;
1402         }
1403
1404         hash = wm_mchash(sc, enm->enm_addrlo);
1405
1406         reg = (hash >> 5) & 0x7f;
1407         bit = hash & 0x1f;
1408
1409         hash = CSR_READ(sc,mta_reg + (reg << 2));
1410         hash |= 1U << bit;
1411
1412         /* XXX Hardware bug?? */
1413         if ((reg & 0xe) == 1) {
1414            bit = CSR_READ(sc,mta_reg + ((reg - 1) << 2));
1415            CSR_WRITE(sc,mta_reg + (reg << 2), hash);
1416            CSR_WRITE(sc,mta_reg + ((reg - 1) << 2), bit);
1417         } else
1418            CSR_WRITE(sc,mta_reg + (reg << 2), hash);
1419
1420         ETHER_NEXT_MULTI(step, enm);
1421  }
1422
1423  ifp->if_flags &= ~IFF_ALLMULTI;
1424  goto setit;
1425
1426 allmulti:
1427  ifp->if_flags |= IFF_ALLMULTI;
1428  sc->sc_rctl |= RCTL_MPE;
1429
1430 setit:
1431  CSR_WRITE(sc,WMREG_RCTL, sc->sc_rctl);
1432
1433#ifdef WM_DEBUG
1434  printk("RCTL 0x%x)\n", CSR_READ(sc,WMREG_RCTL));
1435#endif 
1436}
1437
1438static void i82544EI_error(struct wm_softc *sc)
1439{
1440  struct ifnet          *ifp = &sc->arpcom.ac_if;
1441  unsigned long         intr_status= sc->intr_errsts[sc->intr_err_ptr1++];
1442
1443  /* read and reset the status; because this is written
1444   * by the ISR, we must disable interrupts here
1445   */
1446  sc->intr_err_ptr1 %=INTR_ERR_SIZE; /* Till Straumann */
1447  if (intr_status) {
1448    printk("Error %s%d:", ifp->if_name, ifp->if_unit);
1449    if (intr_status & ICR_RXSEQ) {
1450       printk("Rxq framing error (ICR= %x), if_ierrors %d\n",
1451              intr_status, ifp->if_ierrors);
1452    }
1453  }
1454  else
1455    printk("%s%d: Ghost interrupt ?\n",ifp->if_name,ifp->if_unit);
1456}
1457
1458void i82544EI_printStats()
1459{
1460  i82544EI_stats(root_i82544EI_dev);
1461}
1462
1463/* The daemon does all of the work; RX, TX and cleaning up buffers/descriptors */
1464static void i82544EI_daemon(void *arg)
1465{
1466  struct wm_softc *sc = (struct wm_softc*)arg;
1467  rtems_event_set       events;
1468  struct mbuf   *m=0;
1469  struct ifnet  *ifp=&sc->arpcom.ac_if;
1470
1471#ifdef WM_DEBUG
1472  printk("i82544EI_daemon()\n");
1473#endif
1474
1475  /* NOTE: our creator possibly holds the bsdnet_semaphore.
1476   *       since that has PRIORITY_INVERSION enabled, our
1477   *       subsequent call to bsdnet_event_receive() will
1478   *       _not_ release it. It's still in posession of our
1479   *       owner.
1480   *       This is different from how killing this task
1481   *       is handled.
1482   */
1483
1484  for (;;) {
1485     /* sleep until there's work to be done */
1486     /* Note: bsdnet_event_receive() acquires
1487      *       the global bsdnet semaphore for
1488      *       mutual exclusion.
1489      */
1490     rtems_bsdnet_event_receive(ALL_EVENTS,
1491                                RTEMS_WAIT | RTEMS_EVENT_ANY,
1492                                RTEMS_NO_TIMEOUT,
1493                                &events);
1494     if (KILL_EVENT & events)  break;
1495
1496     if (events & RX_EVENT)  i82544EI_rx(sc);
1497
1498     /* clean up and try sending packets */
1499     do {
1500        i82544EI_txq_done(sc);
1501
1502        while (sc->txq_free>0) {
1503           if (sc->txq_free>TXQ_HiLmt_OFF) {
1504              IF_DEQUEUE(&ifp->if_snd,m);
1505              if (m==0) break;
1506              i82544EI_sendpacket(sc, m);
1507           }
1508           else {
1509              i82544EI_txq_done(sc);
1510              break;
1511           }
1512           if (events & RX_EVENT)  i82544EI_rx(sc);
1513        }
1514         /* we leave this loop
1515          *  - either because there's no free buffer
1516          *    (m=0 initializer && !sc->txq_free)
1517          *  - or there's nothing to send (IF_DEQUEUE
1518          *    returned 0
1519          */
1520     } while (m && sc->txq_free);
1521
1522     ifp->if_flags &= ~IFF_OACTIVE;
1523
1524     /* Log errors and other uncommon events. */
1525     if (events & ERR_EVENT) i82544EI_error(sc);
1526     /* Rx overrun */
1527     if ( events & INIT_EVENT) {
1528        printk("Warnning, Rx overrun.  Make sure the old mbuf was free\n");
1529        i82544EI_ifinit(arg);
1530     }
1531
1532  } /* end for(;;) { rtems_bsdnet_event_receive() .....*/
1533
1534  printf("out of daemon\n");
1535  ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
1536
1537  /* shut down the hardware */
1538  i82544EI_stop_hw(sc);
1539  /* flush the output queue */
1540  for (;;) {
1541      IF_DEQUEUE(&ifp->if_snd,m);
1542      if (!m) break;
1543      m_freem(m);
1544  }
1545  /* as of 'rtems_bsdnet_event_receive()' we own the
1546   * networking semaphore
1547   */
1548  rtems_bsdnet_semaphore_release();
1549  rtems_semaphore_release(sc->daemonSync);
1550
1551  /* Note that I dont use sc->daemonTid here -
1552   * theoretically, that variable could already
1553   * hold a newly created TID
1554   */
1555  rtems_task_delete(RTEMS_SELF);
1556}
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