source: rtems/c/src/lib/libbsp/powerpc/mvme5500/network/if_1GHz/if_wm.c @ 5d2f5196

4.104.114.9
Last change on this file since 5d2f5196 was 5d2f5196, checked in by Ralf Corsepius <ralf.corsepius@…>, on Aug 20, 2008 at 11:32:46 AM

Add missing prototypes.

  • Property mode set to 100644
File size: 43.0 KB
Line 
1/*
2 * Copyright (c) 2004,2005 RTEMS/Mvme5500 port by S. Kate Feng <feng1@bnl.gov>
3 *      Brookhaven National Laboratory, All rights reserved
4 *
5 * Acknowledgements:
6 * netBSD : Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
7 *          Jason R. Thorpe for Wasabi Systems, Inc.
8 * Intel : NDA document
9 *
10 * Some notes from the author, S. Kate Feng :
11 *
12 * 1) The error reporting routine i82544EI_error() employs two pointers
13 *    for the error report buffer. One for the ISR and another one for
14 *    the error report.
15 * 2) Enable the hardware Auto-Negotiation state machine.
16 * 3) Set Big Endian mode in the WMREG_CTRL so that we do not need htole32
17 *    because PPC is big endian mode.
18 *    However, the data packet structure defined in if_wmreg.h
19 *    should be redefined for the big endian mode.
20 * 4) To ensure the cache coherence, the MOTLoad had the PCI
21 *    snoop control registers (0x1f00) set to "snoop to WB region" for
22 *    the entire 512MB of memory.
23 * 5) MOTLoad default :
24 *    little endian mode, cache line size is 32 bytes, no checksum control,
25 *    hardware auto-neg. state machine disabled. PCI control "snoop
26 *    to WB region", MII mode (PHY) instead of TBI mode.
27 * 6) We currently only use 32-bit (instead of 64-bit) DMA addressing.
28 * 7) Support for checksum offloading and TCP segmentation offload will
29 *    be available for releasing in 2008, upon request, if I still believe.
30 *   
31 */
32
33#define BYTE_ORDER BIG_ENDIAN
34
35#define INET
36
37#include <rtems.h>
38#include <rtems/bspIo.h>      /* printk */
39#include <stdio.h>            /* printf for statistics */
40#include <string.h>
41
42#include <libcpu/io.h>        /* inp & friends */
43#include <libcpu/spr.h>       /* registers.h is included here */
44#include <bsp.h>
45
46#include <sys/param.h>
47#include <sys/systm.h>
48#include <sys/mbuf.h>
49
50#include <rtems/rtems_bsdnet.h>
51#include <rtems/rtems_bsdnet_internal.h>
52#include <rtems/error.h>          
53#include <errno.h>
54
55#include <rtems/rtems/types.h>
56#include <rtems/score/cpu.h>
57
58#include <sys/queue.h>
59
60#include <sys/ioctl.h>
61#include <sys/socket.h>
62#include <sys/sockio.h>             /* SIOCADDMULTI, SIOC...     */
63#include <net/if.h>
64#include <net/if_dl.h>
65#include <netinet/in.h>
66#include <netinet/if_ether.h>
67
68#ifdef INET
69#include <netinet/in_var.h>
70#endif
71
72#include <bsp/irq.h>
73#include <bsp/pci.h>
74#include <bsp/pcireg.h>
75#include <bsp/if_wmreg.h>
76#define WMREG_RADV      0x282c  /* Receive Interrupt Absolute Delay Timer */
77
78/*#define CKSUM_OFFLOAD*/
79
80#define ETHERTYPE_FLOWCONTROL   0x8808  /* 802.3x flow control packet */
81
82#define i82544EI_TASK_NAME "IGHZ"
83#define SOFTC_ALIGN        4095
84
85#define INTR_ERR_SIZE        16
86
87/*#define WM_DEBUG*/
88#ifdef WM_DEBUG
89#define WM_DEBUG_LINK           0x01
90#define WM_DEBUG_TX             0x02
91#define WM_DEBUG_RX             0x04
92#define WM_DEBUG_GMII           0x08
93int     wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK;
94
95#define DPRINTF(x, y)   if (wm_debug & (x)) printk y
96#else
97#define DPRINTF(x, y)   /* nothing */
98#endif /* WM_DEBUG */
99
100/* RTEMS event to kill the daemon */
101#define KILL_EVENT              RTEMS_EVENT_1
102/* RTEMS event to (re)start the transmitter */
103#define START_TRANSMIT_EVENT    RTEMS_EVENT_2
104/* RTEMS events used by the ISR */
105#define RX_EVENT                RTEMS_EVENT_3
106#define TX_EVENT                RTEMS_EVENT_4
107#define ERR_EVENT               RTEMS_EVENT_5
108#define INIT_EVENT              RTEMS_EVENT_6
109 
110#define ALL_EVENTS (KILL_EVENT|START_TRANSMIT_EVENT|RX_EVENT|TX_EVENT|ERR_EVENT|INIT_EVENT)
111
112
113#define NTXDESC                 128
114#define NTXDESC_MASK            (NTXDESC - 1)
115#define WM_NEXTTX(x)            (((x) + 1) & NTXDESC_MASK)
116
117#define NRXDESC                 64
118#define NRXDESC_MASK            (NRXDESC - 1)
119#define WM_NEXTRX(x)            (((x) + 1) & NRXDESC_MASK)
120#define WM_PREVRX(x)            (((x) - 1) & NRXDESC_MASK)
121
122#define WM_CDOFF(x)     offsetof(struct wm_control_data, x)
123#define WM_CDTXOFF(x)   WM_CDOFF(sc_txdescs[(x)])
124#define WM_CDRXOFF(x)   WM_CDOFF(sc_rxdescs[(x)])
125
126#define TXQ_HiLmt_OFF 64
127
128static uint32_t TxDescCmd;
129
130/*
131 * Software state per device.
132 */
133struct wm_softc {
134        wiseman_txdesc_t sc_txdescs[NTXDESC]; /* transmit descriptor memory */
135        wiseman_rxdesc_t sc_rxdescs[NRXDESC]; /* receive descriptor memory */
136        struct mbuf *txs_mbuf[NTXDESC];        /* transmit buffer memory */
137        struct mbuf *rxs_mbuf[NRXDESC];        /* receive buffer memory */
138        struct wm_softc *next_module;
139        volatile unsigned int intr_errsts[INTR_ERR_SIZE]; /* intr_status */
140        unsigned int intr_err_ptr1;     /* ptr used in i82544EI_error() */
141        unsigned int intr_err_ptr2;     /* ptr used in ISR */
142        int txs_firstdesc;              /* first descriptor in packet */
143        int txs_lastdesc;               /* last descriptor in packet */
144        int txs_ndesc;                  /* # of descriptors used */
145        unsigned sc_membase;            /* Memory space base address */
146        unsigned sc_memsize;            /* Memory space size */
147
148        char    dv_xname[16];           /* external name (name + unit) */
149        void *sc_sdhook;                /* shutdown hook */
150        struct arpcom arpcom;           /* rtems if structure, contains ifnet */
151        int sc_flags;                   /* flags; see below */
152        int sc_bus_speed;               /* PCI/PCIX bus speed */
153        int sc_flowflags;               /* 802.3x flow control flags */
154
155        void *sc_ih;                    /* interrupt cookie */
156
157        int sc_ee_addrbits;             /* EEPROM address bits */
158        rtems_id        daemonTid;
159        rtems_id        daemonSync;     /* synchronization with the daemon */
160
161        int      txq_next;              /* next Tx descriptor ready for transmitting */
162        uint32_t txq_nactive;           /* number of active TX descriptors */
163        uint32_t txq_fi;                /* next free Tx descriptor */
164        uint32_t txq_free;              /* number of free Tx jobs */
165        uint32_t sc_txctx_ipcs;         /* cached Tx IP cksum ctx */
166        uint32_t sc_txctx_tucs;         /* cached Tx TCP/UDP cksum ctx */
167
168        int     sc_rxptr;               /* next ready Rx descriptor/queue ent */
169        int     sc_rxdiscard;
170        int     sc_rxlen;
171        uint32_t sc_ctrl;               /* prototype CTRL register */
172#if 0
173        uint32_t sc_ctrl_ext;           /* prototype CTRL_EXT register */
174#endif
175        uint32_t sc_icr;                /* prototype interrupt bits */
176        uint32_t sc_tctl;               /* prototype TCTL register */
177        uint32_t sc_rctl;               /* prototype RCTL register */
178        uint32_t sc_tipg;               /* prototype TIPG register */
179        uint32_t sc_fcrtl;              /* prototype FCRTL register */
180
181        int sc_mchash_type;             /* multicast filter offset */
182
183        /* statistics */
184        struct {
185          volatile unsigned long     rxInterrupts;
186          volatile unsigned long     txInterrupts;
187          unsigned long     txMultiBuffPacket;
188          unsigned long     txMultiMaxLen;
189          unsigned long     txSinglMaxLen;
190          unsigned long     txMultiMaxLoop;
191          unsigned long     txBuffMaxLen;
192          unsigned long     linkInterrupts;
193          unsigned long     length_errors;
194          unsigned long     frame_errors;
195          unsigned long     crc_errors;
196          unsigned long     rxOvrRunInterrupts; /* Rx overrun interrupt */
197          unsigned long     rxSeqErr;
198          unsigned long     rxC_ordered;
199          unsigned long     ghostInterrupts;
200          unsigned long     linkStatusChng;
201        } stats;
202};
203
204/* <skf> our memory address seen from the PCI bus should be 1:1 */
205#define htole32(x)  le32toh(x)
206#define le32toh(x)  CPU_swap_u32((unsigned int) x)
207#define le16toh(x)  CPU_swap_u16(x)
208
209/* sc_flags */
210#define WM_F_HAS_MII            0x01    /* has MII */
211/* 82544 EI does not perform EEPROM handshake, EEPROM interface is not SPI */
212#define WM_F_EEPROM_HANDSHAKE   0x02    /* requires EEPROM handshake */
213#define WM_F_EEPROM_SPI         0x04    /* EEPROM is SPI */
214#define WM_F_IOH_VALID          0x10    /* I/O handle is valid */
215#define WM_F_BUS64              0x20    /* bus is 64-bit */
216#define WM_F_PCIX               0x40    /* bus is PCI-X */
217
218#define CSR_READ(sc,reg) in_le32((volatile unsigned *)(sc->sc_membase+reg))
219#define CSR_WRITE(sc,reg,val) out_le32((volatile unsigned *)(sc->sc_membase+reg), val)
220
221#define WM_CDTXADDR(sc) ( (uint32_t) &sc->sc_txdescs[0] )
222#define WM_CDRXADDR(sc) ( (uint32_t) &sc->sc_rxdescs[0] )
223
224static struct wm_softc *root_i82544EI_dev = NULL;
225
226static void i82544EI_ifstart(struct ifnet *ifp);
227static int  wm_ioctl(struct ifnet *ifp, u_long cmd,uint32_t data);
228static void i82544EI_ifinit(void *arg);
229static void wm_stop(struct ifnet *ifp, int disable);
230
231static void wm_rxdrain(struct wm_softc *sc);
232static int  wm_add_rxbuf(struct wm_softc *sc, int idx);
233static int  wm_read_eeprom(struct wm_softc *sc,int word,int wordcnt, uint16_t *data);
234static void i82544EI_daemon(void *arg);
235static void wm_set_filter(struct wm_softc *sc);
236
237static void i82544EI_isr(void);
238static void i82544EI_sendpacket(struct wm_softc *sc, struct mbuf *m);
239extern int pci_mem_find(int b, int d, int f, int reg, unsigned *basep,unsigned *sizep);
240extern int pci_io_find(int b, int d, int f, int reg,unsigned *basep,unsigned *sizep);
241extern int pci_get_capability(int b, int d, int f, int capid,int *offset,uint32_t *value);
242extern char * ether_sprintf1(void);
243
244static void i82544EI_irq_on(const rtems_irq_connect_data *irq)
245{
246  struct wm_softc *sc;
247  unsigned int irqMask=  ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | ICR_RXO | ICR_RXT0 | ICR_RXCFG;
248 
249  for (sc= root_i82544EI_dev; sc; sc= sc-> next_module) {
250    CSR_WRITE(sc,WMREG_IMS,(CSR_READ(sc,WMREG_IMS)| irqMask) );
251    return;
252  }
253}
254
255static void i82544EI_irq_off(const rtems_irq_connect_data *irq)
256{
257  struct wm_softc *sc;
258  unsigned int irqMask=  ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | ICR_RXO | ICR_RXT0 |ICR_RXCFG ;
259
260  for (sc= root_i82544EI_dev; sc; sc= sc-> next_module) {
261    CSR_WRITE(sc,WMREG_IMS, (CSR_READ(sc,WMREG_IMS) & ~irqMask) );
262    return;
263  }
264}
265
266static int i82544EI_irq_is_on(const rtems_irq_connect_data *irq)
267{
268  return(CSR_READ(root_i82544EI_dev,WMREG_ICR) & root_i82544EI_dev->sc_icr);
269}
270
271static rtems_irq_connect_data i82544IrqData={
272        BSP_GPP_82544_IRQ,
273        (rtems_irq_hdl) i82544EI_isr,
274        (rtems_irq_enable) i82544EI_irq_on,
275        (rtems_irq_disable) i82544EI_irq_off,
276        (rtems_irq_is_enabled) i82544EI_irq_is_on, 
277};
278
279int rtems_i82544EI_driver_attach(struct rtems_bsdnet_ifconfig *config, int attach)
280{
281  struct wm_softc *sc;
282  struct ifnet *ifp;
283  uint8_t enaddr[ETHER_ADDR_LEN];
284  uint16_t myea[ETHER_ADDR_LEN / 2], cfg1, cfg2, swdpin;
285  unsigned reg;
286  int b,d,f; /* PCI bus/device/function */
287  int unit;
288  void     *softc_mem;
289  char     *name;
290
291  unit = rtems_bsdnet_parse_driver_name(config, &name);
292  if (unit < 0) return 0;
293 
294  printk("\nEthernet driver name %s unit %d \n",name, unit);
295  printk("Copyright (c) 2004,2005 S. Kate Feng <feng1@bnl.gov> (RTEMS/mvme5500 port)\n");
296
297  /* Make sure certain elements e.g. descriptor lists are aligned.*/ 
298  softc_mem = rtems_bsdnet_malloc(sizeof(*sc) + SOFTC_ALIGN, M_FREE, M_NOWAIT);
299
300  /* Check for the very unlikely case of no memory. */
301  if (softc_mem == NULL)
302     rtems_panic("i82544EI: OUT OF MEMORY");
303
304  sc = (void *)(((long)softc_mem + SOFTC_ALIGN) & ~SOFTC_ALIGN);
305  memset(sc, 0, sizeof(*sc));
306
307  sprintf(sc->dv_xname, "%s%d", name, unit);
308
309  if (pci_find_device(PCI_VENDOR_ID_INTEL,PCI_DEVICE_INTEL_82544EI_COPPER,
310                        unit-1,&b, &d, &f))
311    rtems_panic("i82544EI device ID not found\n");
312
313#if WM_DEBUG
314  printk("82544EI:b%d, d%d, f%d\n", b, d,f);
315#endif
316
317  /* Memory-mapped acccess is required for normal operation.*/
318  if ( pci_mem_find(b,d,f,PCI_MAPREG_START, &sc->sc_membase, &sc->sc_memsize))
319     rtems_panic("i82544EI: unable to map memory space\n");
320
321#ifdef WM_DEBUG
322  printk("Memory base addr 0x%x\n", sc->sc_membase);
323  printk("txdesc[0] addr:0x%x, rxdesc[0] addr:0x%x, sizeof sc %d\n",&sc->sc_txdescs[0], &sc->sc_rxdescs[0], sizeof(*sc));     
324#endif
325
326
327  sc->sc_ctrl |=CSR_READ(sc,WMREG_CTRL); 
328  /*
329   * Determine a few things about the bus we're connected to.
330   */
331  reg = CSR_READ(sc,WMREG_STATUS); 
332  if (reg & STATUS_BUS64) sc->sc_flags |= WM_F_BUS64;
333  sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33;
334#ifdef WM_DEBUG
335  printk("%s%d: %d-bit %dMHz PCI bus\n",name, unit,
336         (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed);
337#endif
338
339  /*
340   * Setup some information about the EEPROM.
341   */
342
343  sc->sc_ee_addrbits = 6;
344
345#ifdef WM_DEBUG
346  printk("%s%d: %u word (%d address bits) MicroWire EEPROM\n",
347            name, unit, 1U << sc->sc_ee_addrbits,
348            sc->sc_ee_addrbits);
349#endif
350
351  /*
352   * Read the Ethernet address from the EEPROM.
353   */
354  if (wm_read_eeprom(sc, EEPROM_OFF_MACADDR,
355            sizeof(myea) / sizeof(myea[0]), myea)) 
356     rtems_panic("i82544ei 1GHZ ethernet: unable to read Ethernet address");
357
358  enaddr[0] = myea[0] & 0xff;
359  enaddr[1] = myea[0] >> 8;
360  enaddr[2] = myea[1] & 0xff;
361  enaddr[3] = myea[1] >> 8;
362  enaddr[4] = myea[2] & 0xff;
363  enaddr[5] = myea[2] >> 8;
364
365
366  memcpy(sc->arpcom.ac_enaddr, enaddr, ETHER_ADDR_LEN);
367#ifdef WM_DEBUG
368  printk("%s: Ethernet address %s\n", sc->dv_xname,
369            ether_sprintf1(enaddr));
370#endif
371
372  /*
373   * Read the config info from the EEPROM, and set up various
374   * bits in the control registers based on their contents.
375   */
376  if (wm_read_eeprom(sc, EEPROM_OFF_CFG1, 1, &cfg1)) {
377     printk("%s: unable to read CFG1 from EEPROM\n",sc->dv_xname);
378     return(0);
379  }
380  if (wm_read_eeprom(sc, EEPROM_OFF_CFG2, 1, &cfg2)) {
381     printk("%s: unable to read CFG2 from EEPROM\n",sc->dv_xname);
382     return(0);
383  }
384  if (wm_read_eeprom(sc, EEPROM_OFF_SWDPIN, 1, &swdpin)) {
385     printk("%s: unable to read SWDPIN from EEPROM\n",sc->dv_xname);
386     return(0);
387  }
388
389  if (cfg1 & EEPROM_CFG1_ILOS) sc->sc_ctrl |= CTRL_ILOS;
390  sc->sc_ctrl|=((swdpin >> EEPROM_SWDPIN_SWDPIO_SHIFT) & 0xf) <<
391                CTRL_SWDPIO_SHIFT;
392  sc->sc_ctrl |= ((swdpin >> EEPROM_SWDPIN_SWDPIN_SHIFT) & 0xf) <<
393                CTRL_SWDPINS_SHIFT;
394
395  CSR_WRITE(sc,WMREG_CTRL, sc->sc_ctrl);
396#if 0
397  CSR_WRITE(sc,WMREG_CTRL_EXT, sc->sc_ctrl_ext);
398#endif
399
400  ifp = &sc->arpcom.ac_if;
401  /* set this interface's name and unit */
402  ifp->if_unit = unit;
403  ifp->if_name = name;
404  ifp->if_softc = sc;
405  ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
406  ifp->if_mtu = config->mtu ? config->mtu : ETHERMTU;
407  ifp->if_ioctl = wm_ioctl;
408  ifp->if_start = i82544EI_ifstart;
409  /*  ifp->if_watchdog = wm_watchdog;*/
410  ifp->if_init = i82544EI_ifinit;
411  if (ifp->if_snd.ifq_maxlen == 0)
412      ifp->if_snd.ifq_maxlen = ifqmaxlen;
413
414  ifp->if_output = ether_output;
415
416  /* create the synchronization semaphore */
417  if (RTEMS_SUCCESSFUL != rtems_semaphore_create(
418     rtems_build_name('I','G','H','Z'),0,0,0,&sc->daemonSync))
419     rtems_panic("i82544EI: semaphore creation failed");
420
421  sc->next_module = root_i82544EI_dev;
422  root_i82544EI_dev = sc;
423
424  /* Attach the interface. */
425  if_attach(ifp);
426  ether_ifattach(ifp);
427#ifdef WM_DEBUG
428  printk("82544EI: Ethernet driver has been attached (handle 0x%08x,ifp 0x%08x)\n",sc, ifp);
429#endif
430
431  return(1);
432}
433
434/*
435 * i82544EI_ifstart:            [ifnet interface function]
436 *
437 *      Start packet transmission on the interface.
438 */
439static void
440i82544EI_ifstart(struct ifnet *ifp)
441{
442  struct wm_softc *sc = ifp->if_softc;
443
444#ifdef WM_DEBUG
445  printk("i82544EI_ifstart(");
446#endif
447
448  if ((ifp->if_flags & IFF_RUNNING) == 0) {
449#ifdef WM_DEBUG
450     printk("IFF_RUNNING==0\n");
451#endif         
452     return;
453  }
454
455  ifp->if_flags |= IFF_OACTIVE;
456  rtems_event_send (sc->daemonTid, START_TRANSMIT_EVENT);
457#ifdef WM_DEBUG
458  printk(")\n");
459#endif
460}
461
462static void i82544EI_stats(struct wm_softc *sc)
463{
464  struct ifnet *ifp = &sc->arpcom.ac_if;
465
466  printf("       Rx Interrupts:%-8u\n", sc->stats.rxInterrupts);
467  printf("     Receive Packets:%-8u\n", CSR_READ(sc,WMREG_GPRC));
468  printf("     Receive Overrun:%-8u\n", sc->stats.rxOvrRunInterrupts);
469  printf("     Receive  errors:%-8u\n", CSR_READ(sc,WMREG_RXERRC));
470  printf("   Rx sequence error:%-8u\n", sc->stats.rxSeqErr);
471  printf("      Rx /C/ ordered:%-8u\n", sc->stats.rxC_ordered);
472  printf("    Rx Length Errors:%-8u\n", CSR_READ(sc,WMREG_RLEC));
473  printf("       Tx Interrupts:%-8u\n", sc->stats.txInterrupts);
474#if 0
475  printf("Multi-BuffTx Packets:%-8u\n", sc->stats.txMultiBuffPacket);
476  printf("Multi-BuffTx max len:%-8u\n", sc->stats.txMultiMaxLen);
477  printf("SingleBuffTx max len:%-8u\n", sc->stats.txSinglMaxLen);
478  printf("Multi-BuffTx maxloop:%-8u\n", sc->stats.txMultiMaxLoop);
479  printf("Tx buffer max len   :%-8u\n", sc->stats.txBuffMaxLen);
480#endif
481  printf("   Transmitt Packets:%-8u\n", CSR_READ(sc,WMREG_GPTC));
482  printf("   Transmitt  errors:%-8u\n", ifp->if_oerrors);
483  printf("         Active Txqs:%-8u\n", sc->txq_nactive); 
484  printf("          collisions:%-8u\n", CSR_READ(sc,WMREG_COLC));
485  printf("          Crc Errors:%-8u\n", CSR_READ(sc,WMREG_CRCERRS));
486  printf("  Link Status Change:%-8u\n", sc->stats.linkStatusChng);
487}
488
489/*
490 * wm_ioctl:            [ifnet interface function]
491 *
492 *      Handle control requests from the operator.
493 */
494static int wm_ioctl(struct ifnet *ifp, u_long cmd,uint32_t data)
495{
496  struct wm_softc *sc = ifp->if_softc;
497  int error=0;
498
499  switch (cmd) {
500    default:
501      error = ether_ioctl(ifp, cmd, data);
502      if (error == ENETRESET) {
503          /*
504           * Multicast list has changed; set the hardware filter
505           * accordingly.
506           */
507          wm_set_filter(sc);
508          error = 0;
509      }
510      break;
511    case SIO_RTEMS_SHOW_STATS:
512      i82544EI_stats(sc);
513      break;
514  }
515
516  /* Try to get more packets going.*/
517  i82544EI_ifstart(ifp);
518  return (error);
519}
520
521/*
522 * wm_isr:
523 *
524 *      Interrupt service routine.
525 */
526static void i82544EI_isr()
527{
528  volatile struct wm_softc *sc = root_i82544EI_dev;
529  uint32_t icr;
530  rtems_event_set  events=0;
531
532  /* Reading the WMREG_ICR clears the interrupt bits */
533  icr = CSR_READ(sc,WMREG_ICR);
534
535  if ( icr & (ICR_RXDMT0|ICR_RXT0)) {
536     sc->stats.rxInterrupts++;
537     events |= RX_EVENT;
538  }
539
540  if (icr & ICR_TXDW) {
541     sc->stats.txInterrupts++;
542     events |= TX_EVENT;
543  }
544  /* <SKF> Rx overrun : no available receive buffer
545   * or PCI receive bandwidth inadequate.
546   */
547  if (icr & ICR_RXO) {
548     sc->stats.rxOvrRunInterrupts++;
549     events |= INIT_EVENT;
550  }
551  if (icr & ICR_RXSEQ) /* framing error */ {
552     sc->intr_errsts[sc->intr_err_ptr2++]=icr;
553     sc->intr_err_ptr2 %=INTR_ERR_SIZE; /* Till Straumann */
554     events |= ERR_EVENT;
555     sc->stats.rxSeqErr++;
556  }
557  if ( !icr) sc->stats.ghostInterrupts++;
558
559  if (icr & ICR_LSC) sc->stats.linkStatusChng++;
560  if (icr & ICR_RXCFG) sc->stats.rxC_ordered++;
561
562  rtems_event_send(sc->daemonTid, events);
563}
564
565/*
566 * i82544EI_sendpacket:
567 *
568 *      Helper; handle transmit interrupts.
569 */
570static void i82544EI_sendpacket(struct wm_softc *sc, struct mbuf *m)
571{
572
573#ifdef WM_DEBUG_TX
574  printk("sendpacket(");
575#endif
576
577  if ( !(m->m_next)) { /* single buffer packet */
578    sc->txs_mbuf[sc->txq_next]= m;
579    /* Note: we currently only use 32-bit DMA addresses. */
580    sc->sc_txdescs[sc->txq_next].wtx_addr.wa_low = htole32(mtod(m, void*));
581    sc->sc_txdescs[sc->txq_next].wtx_cmdlen =htole32(TxDescCmd | m->m_len);
582    sc->txs_lastdesc= sc->txq_next;
583    sc->txq_next = WM_NEXTTX(sc->txq_next);
584    sc->txq_nactive++;
585    sc->txq_free--;
586  }
587  else /* multiple mbufs in this packet */
588  { 
589    struct mbuf *mtp, *mdest;
590    volatile unsigned char *pt;
591    int len, y, loop=0;
592
593#ifdef WM_DEBUG_TX
594    printk("multi mbufs ");
595#endif
596    mtp = m;
597    while ( mtp) { 
598      MGETHDR(mdest, M_WAIT, MT_DATA);
599      MCLGET(mdest, M_WAIT);
600      pt = (volatile unsigned char *)mdest->m_data;
601      for ( len=0;mtp;mtp=mtp->m_next) {
602        loop++;
603        /* Each descriptor gets a 2k (MCLBYTES) buffer, although
604         * the length of each descriptor can be up to 16288 bytes.
605         * For packets which fill more than one buffer ( >2k), we
606         * chain them together.
607         * <Kate Feng> : This effective for packets > 2K
608         * The other way is effective for packets < 2K
609         */
610        if ( ((y=(len+mtp->m_len)) > sizeof(union mcluster))) {
611          printk(">2048, use next descriptor\n");
612          break; 
613        }
614        memcpy((void *)pt,(char *)mtp->m_data, mtp->m_len);
615        pt += mtp->m_len;
616        len += mtp->m_len;
617#if 0
618        sc->stats.txSinglMaxLen= MAX(mtp->m_len, sc->stats.txSinglMaxLen);
619#endif
620      } /* end for loop */
621      mdest->m_len=len;
622      sc->txs_mbuf[sc->txq_next] = mdest;
623      /* Note: we currently only use 32-bit DMA addresses. */
624      sc->sc_txdescs[sc->txq_next].wtx_addr.wa_low = htole32(mtod(mdest, void*));
625      sc->sc_txdescs[sc->txq_next].wtx_cmdlen = htole32(TxDescCmd|mdest->m_len);
626      sc->txs_lastdesc = sc->txq_next;
627      sc->txq_next = WM_NEXTTX(sc->txq_next);
628      sc->txq_nactive ++;
629      if (sc->txq_free) 
630         sc->txq_free--;
631      else
632         rtems_panic("i8254EI : no more free descriptors");
633#if 0
634      sc->stats.txMultiMaxLen= MAX(mdest->m_len, sc->stats.txMultiMaxLen);
635      sc->stats.txMultiBuffPacket++;
636#endif
637    } /* end for while */
638    /* free old mbuf chain */
639#if 0
640    sc->stats.txMultiMaxLoop=MAX(loop, sc->stats.txMultiMaxLoop);
641#endif
642    m_freem(m); 
643    m=0;
644  }  /* end  multiple mbufs */
645   
646  DPRINTF(WM_DEBUG_TX,("%s: TX: desc %d: cmdlen 0x%08x\n", sc->dv_xname,
647         sc->txs_lastdesc, le32toh(sc->sc_txdescs[sc->txs_lastdesc].wtx_cmdlen)));
648  DPRINTF(WM_DEBUG_TX,("status 0x%08x\n",sc->sc_txdescs[sc->txq_fi].wtx_fields.wtxu_status));
649
650  memBar();
651
652  /* This is the location where software writes the first NEW descriptor */
653  CSR_WRITE(sc,WMREG_TDT, sc->txq_next);
654
655  DPRINTF(WM_DEBUG_TX,("%s: addr 0x%08x, TX: TDH %d, TDT %d\n",sc->dv_xname,
656  le32toh(sc->sc_txdescs[sc->txs_lastdesc].wtx_addr.wa_low), CSR_READ(sc,WMREG_TDH),
657          CSR_READ(sc,WMREG_TDT)));
658
659  DPRINTF(WM_DEBUG_TX,("%s: TX: finished transmitting packet, job %d\n",
660                    sc->dv_xname, sc->txq_next));
661
662}
663
664static void i82544EI_txq_free(struct wm_softc *sc, uint8_t status)
665{
666  struct ifnet *ifp = &sc->arpcom.ac_if;
667
668  /* We might use the statistics registers instead of variables
669   * to keep tack of the network statistics
670   */ 
671
672  /* statistics */
673  ifp->if_opackets++;
674
675  if (status & (WTX_ST_EC|WTX_ST_LC)) {
676       ifp->if_oerrors++;
677
678     if (status & WTX_ST_LC) 
679        printf("%s: late collision\n", sc->dv_xname);
680     else if (status & WTX_ST_EC) {
681        ifp->if_collisions += 16;
682         printf("%s: excessive collisions\n", sc->dv_xname);
683     }
684  }
685  /* Free the original mbuf chain */
686  m_freem(sc->txs_mbuf[sc->txq_fi]);
687  sc->txs_mbuf[sc->txq_fi] = 0;
688  sc->sc_txdescs[sc->txq_fi].wtx_fields.wtxu_status=0;
689
690  sc->txq_free ++;
691  sc->txq_fi = WM_NEXTTX(sc->txq_fi);
692  --sc->txq_nactive;
693}
694
695static void i82544EI_txq_done(struct wm_softc *sc)
696{
697  uint8_t status;
698
699  /*
700   * Go through the Tx list and free mbufs for those
701   * frames which have been transmitted.
702   */
703  while ( sc->txq_nactive > 0) {
704    status = sc->sc_txdescs[sc->txq_fi].wtx_fields.wtxu_status;
705    if ((status & WTX_ST_DD) == 0) break;
706    i82544EI_txq_free(sc, status);
707    DPRINTF(WM_DEBUG_TX,("%s: TX: job %d done\n",
708                    sc->dv_xname, sc->txq_fi));
709  }
710}
711
712static void wm_init_rxdesc(struct wm_softc *sc, int x) 
713{                       
714  wiseman_rxdesc_t *__rxd = &(sc)->sc_rxdescs[(x)];             
715  struct mbuf *m;
716
717  m = sc->rxs_mbuf[x];
718               
719  __rxd->wrx_addr.wa_low=htole32(mtod(m, void*)); 
720  __rxd->wrx_addr.wa_high = 0;                                 
721  __rxd->wrx_len = 0;                                             
722  __rxd->wrx_cksum = 0;                                           
723  __rxd->wrx_status = 0;                                               
724  __rxd->wrx_errors = 0;                                         
725  __rxd->wrx_special = 0;                                         
726  /* Receive Descriptor Tail: add Rx desc. to H/W free list */   
727  CSR_WRITE(sc,WMREG_RDT, (x));                                         
728} 
729
730static void i82544EI_rx(struct wm_softc *sc)
731{
732  struct ifnet *ifp = &sc->arpcom.ac_if;
733  struct mbuf *m;
734  int i, len;
735  uint8_t status, errors;
736  struct ether_header *eh;
737
738#ifdef WM_DEBUG
739  printk("i82544EI_rx()\n");
740#endif
741
742  for (i = sc->sc_rxptr;; i = WM_NEXTRX(i)) {
743    DPRINTF(WM_DEBUG_RX, ("%s: RX: checking descriptor %d\n",
744                    sc->dv_xname, i));
745
746    status = sc->sc_rxdescs[i].wrx_status;
747    errors = sc->sc_rxdescs[i].wrx_errors;
748    len = le16toh(sc->sc_rxdescs[i].wrx_len);
749    m = sc->rxs_mbuf[i];
750
751    if ((status & WRX_ST_DD) == 0)  break; /* descriptor not done */
752
753    if (sc->sc_rxdiscard) {
754       printk("RX: discarding contents of descriptor %d\n", i);
755       wm_init_rxdesc(sc, i);
756       if (status & WRX_ST_EOP) {
757          /* Reset our state. */
758          printk("RX: resetting rxdiscard -> 0\n");
759          sc->sc_rxdiscard = 0;
760       }
761       continue;
762    }
763
764    /*
765     * If an error occurred, update stats and drop the packet.
766     */
767    if (errors &(WRX_ER_CE|WRX_ER_SE|WRX_ER_SEQ|WRX_ER_CXE|WRX_ER_RXE)) {
768       ifp->if_ierrors++;
769       if (errors & WRX_ER_SE)
770          printk("%s: symbol error\n",sc->dv_xname);
771       else if (errors & WRX_ER_SEQ)
772          printk("%s: receive sequence error\n",sc->dv_xname);
773            else if (errors & WRX_ER_CE)
774                 printk("%s: CRC error\n",sc->dv_xname);
775       m_freem(m);
776       goto give_it_back;
777    }
778
779    /*
780     * No errors.  Receive the packet.
781     *
782     * Note, we have configured the chip to include the
783     * CRC with every packet.
784     */
785    m->m_len = m->m_pkthdr.len = len - sizeof(struct ether_header);
786
787    DPRINTF(WM_DEBUG_RX,("%s: RX: buffer at %p len %d\n",
788                    sc->dv_xname, m->m_data, len));
789
790
791    eh = mtod (m, struct ether_header *);
792    m->m_data += sizeof(struct ether_header);
793    ether_input (ifp, eh, m);
794    /* Pass it on. */
795    ifp->if_ipackets++;
796   
797    give_it_back:
798    /* Add a new receive buffer to the ring.*/
799    if (wm_add_rxbuf(sc, i) != 0) {
800       /*
801        * Failed, throw away what we've done so
802        * far, and discard the rest of the packet.
803        */
804       printk("Failed in wm_add_rxbuf(), drop packet\n");
805       ifp->if_ierrors++;
806       wm_init_rxdesc(sc, i);
807       if ((status & WRX_ST_EOP) == 0)
808          sc->sc_rxdiscard = 1;
809       m_freem(m);
810    }
811  } /* end for */
812
813  /* Update the receive pointer. */
814  sc->sc_rxptr = i;
815  DPRINTF(WM_DEBUG_RX, ("%s: RX: rxptr -> %d\n", sc->dv_xname, i));
816}
817
818static int i82544EI_init_hw(struct wm_softc *sc)
819{
820  struct ifnet *ifp = &sc->arpcom.ac_if;
821  int i,error;
822  uint8_t cksumfields;
823
824  /* Cancel any pending I/O. */
825  wm_stop(ifp, 0);
826
827  /* Initialize the error buffer ring */
828  sc->intr_err_ptr1=0;
829  sc->intr_err_ptr2=0;
830  for (i=0; i< INTR_ERR_SIZE; i++) sc->intr_errsts[i]=0;
831
832  /* Initialize the transmit descriptor ring. */
833  memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
834  sc->txq_free = NTXDESC;
835  sc->txq_next = 0;
836  sc->txs_lastdesc = 0;
837  sc->txq_next = 0;
838  sc->txq_free = NTXDESC;
839  sc->txq_nactive = 0;
840
841  sc->sc_txctx_ipcs = 0xffffffff;
842  sc->sc_txctx_tucs = 0xffffffff;
843
844  CSR_WRITE(sc,WMREG_TBDAH, 0);
845  CSR_WRITE(sc,WMREG_TBDAL, WM_CDTXADDR(sc));
846#ifdef WM_DEBUG
847  printk("TBDAL 0x%x, TDLEN %d\n", WM_CDTXADDR(sc), sizeof(sc->sc_txdescs));
848#endif
849  CSR_WRITE(sc,WMREG_TDLEN, sizeof(sc->sc_txdescs));
850  CSR_WRITE(sc,WMREG_TDH, 0);
851  CSR_WRITE(sc,WMREG_TDT, 0);
852  CSR_WRITE(sc,WMREG_TIDV, 64 ); 
853  CSR_WRITE(sc,WMREG_TADV, 128);
854
855  CSR_WRITE(sc,WMREG_TXDCTL, TXDCTL_PTHRESH(0) |
856                    TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0));
857  CSR_WRITE(sc,WMREG_RXDCTL, RXDCTL_PTHRESH(0) |
858                    RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1) | RXDCTL_GRAN );
859
860  CSR_WRITE(sc,WMREG_TQSA_LO, 0);
861  CSR_WRITE(sc,WMREG_TQSA_HI, 0);
862
863  /*
864   * Set up checksum offload parameters for
865   * this packet.
866   */
867#ifdef CKSUM_OFFLOAD
868  if (m0->m_pkthdr.csum_flags &
869     (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) {
870     if (wm_tx_cksum(sc, txs, &TxDescCmd,&cksumfields) != 0) {
871         /* Error message already displayed. */
872         continue;
873     }
874  } else {
875#endif
876     TxDescCmd = 0;
877     cksumfields = 0;
878#ifdef CKSUM_OFFLOAD
879  }
880#endif
881
882  TxDescCmd |= WTX_CMD_EOP|WTX_CMD_IFCS|WTX_CMD_RS; 
883
884  /* Initialize the transmit job descriptors. */
885  for (i = 0; i < NTXDESC; i++) {
886      sc->txs_mbuf[i] = 0;
887      sc->sc_txdescs[i].wtx_fields.wtxu_options=cksumfields;
888      sc->sc_txdescs[i].wtx_addr.wa_high = 0;
889      sc->sc_txdescs[i].wtx_addr.wa_low = 0;
890      sc->sc_txdescs[i].wtx_cmdlen = htole32(TxDescCmd); 
891  }
892
893  /*
894   * Initialize the receive descriptor and receive job
895   * descriptor rings.
896   */
897  memset(sc->sc_rxdescs, 0, sizeof(sc->sc_rxdescs));
898  CSR_WRITE(sc,WMREG_RDBAH, 0);
899  CSR_WRITE(sc,WMREG_RDBAL, WM_CDRXADDR(sc));
900  CSR_WRITE(sc,WMREG_RDLEN, sizeof(sc->sc_rxdescs));
901  CSR_WRITE(sc,WMREG_RDH, 0);
902  CSR_WRITE(sc,WMREG_RDT, 0);
903  CSR_WRITE(sc,WMREG_RDTR, 0 |RDTR_FPD); 
904  CSR_WRITE(sc, WMREG_RADV, 256);
905
906  for (i = 0; i < NRXDESC; i++) {
907      if (sc->rxs_mbuf[i] == NULL) {
908         if ((error = wm_add_rxbuf(sc, i)) != 0) {
909            printk("%s%d: unable to allocate or map rx buffer"
910            "%d, error = %d\n",ifp->if_name,ifp->if_unit, i, error);
911            /*
912             * XXX Should attempt to run with fewer receive
913             * XXX buffers instead of just failing.
914             */
915            wm_rxdrain(sc);
916            return(error);
917          }
918      } else {
919        printk("sc->rxs_mbuf[%d] not NULL.\n", i);
920        wm_init_rxdesc(sc, i);
921      }
922  }
923  sc->sc_rxptr = 0;
924  sc->sc_rxdiscard = 0;
925
926  /*
927   * Clear out the VLAN table -- we don't use it (yet).
928   */
929  CSR_WRITE(sc,WMREG_VET, 0);
930  for (i = 0; i < WM_VLAN_TABSIZE; i++)
931       CSR_WRITE(sc,WMREG_VFTA + (i << 2), 0);
932
933  /*
934   * Set up flow-control parameters.
935   *
936   * XXX Values could probably stand some tuning.
937   */
938  CSR_WRITE(sc,WMREG_FCAL, FCAL_CONST);/*safe,even though MOTLOAD 0x00c28001 */
939  CSR_WRITE(sc,WMREG_FCAH, FCAH_CONST);/*safe,even though MOTLOAD 0x00000100 */
940  CSR_WRITE(sc,WMREG_FCT, ETHERTYPE_FLOWCONTROL);/*safe,even though MOTLoad 0x8808 */
941
942
943  /* safe,even though MOTLoad default all 0 */
944  sc->sc_fcrtl = FCRTL_DFLT;
945
946  CSR_WRITE(sc,WMREG_FCRTH, FCRTH_DFLT);
947  CSR_WRITE(sc,WMREG_FCRTL, sc->sc_fcrtl);
948  CSR_WRITE(sc,WMREG_FCTTV, FCTTV_DFLT);
949
950  sc->sc_ctrl &= ~CTRL_VME;
951  /*sc->sc_ctrl |= CTRL_TFCE | CTRL_RFCE;*/
952  /* enable Big Endian Mode for the powerPC
953  sc->sc_ctrl |= CTRL_BEM;*/
954
955  /* Write the control registers. */
956  CSR_WRITE(sc,WMREG_CTRL, sc->sc_ctrl);
957#if 0
958  CSR_WRITE(sc,WMREG_CTRL_EXT, sc->sc_ctrl_ext);
959#endif
960
961  /* MOTLoad : WMREG_RXCSUM (0x5000)= 0, no Rx checksum offloading */ 
962
963  /*
964   * Set up the interrupt registers.
965   */
966  CSR_WRITE(sc,WMREG_IMC, 0xffffffffU);
967  /* Reading the WMREG_ICR clears the interrupt bits */
968  CSR_READ(sc,WMREG_ICR);
969
970  /*  printf("WMREG_IMS 0x%x\n", CSR_READ(sc,WMREG_IMS));*/
971
972  sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXCFG | ICR_RXDMT0 | ICR_RXO | ICR_RXT0;
973
974  CSR_WRITE(sc,WMREG_IMS, sc->sc_icr);
975
976  /* Set up the inter-packet gap. */
977  CSR_WRITE(sc,WMREG_TIPG, sc->sc_tipg);
978
979#if 0 /* XXXJRT */
980  /* Set the VLAN ethernetype. */
981  CSR_WRITE(sc,WMREG_VET, ETHERTYPE_VLAN);
982#endif
983
984  /*
985   * Set up the transmit control register; we start out with
986   * a collision distance suitable for FDX, but update it when
987   * we resolve the media type.
988   */
989  sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_CT(TX_COLLISION_THRESHOLD) |
990            TCTL_COLD(TX_COLLISION_DISTANCE_FDX) | TCTL_RTLC; /*transmitter enable*/
991
992  /*
993   * Set up the receive control register; we actually program
994   * the register when we set the receive filter.  Use multicast
995   * address offset type 0.
996   *
997   * Only the i82544 has the ability to strip the incoming
998   * CRC, so we don't enable that feature. (TODO)
999   */
1000  sc->sc_mchash_type = 0;
1001  sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_LPE |
1002            RCTL_DPF | RCTL_MO(sc->sc_mchash_type);
1003
1004  /* (MCLBYTES == 2048) */
1005  sc->sc_rctl |= RCTL_2k;
1006
1007#ifdef WM_DEBUG
1008  printk("RDBAL 0x%x,RDLEN %d, RDT %d\n",CSR_READ(sc,WMREG_RDBAL),CSR_READ(sc,WMREG_RDLEN), CSR_READ(sc,WMREG_RDT));
1009#endif
1010
1011  /* Set the receive filter. */
1012  wm_set_filter(sc);
1013
1014  CSR_WRITE(sc,WMREG_TCTL, sc->sc_tctl);
1015
1016  /* Map and establish our interrupt. */
1017  if (!BSP_install_rtems_irq_handler(&i82544IrqData))
1018     rtems_panic("1GHZ ethernet: unable to install ISR");
1019
1020  return(0);
1021}
1022
1023/*
1024 * i82544EI_ifinit:             [ifnet interface function]
1025 *
1026 *      Initialize the interface.
1027 */
1028static void i82544EI_ifinit(void *arg)
1029{
1030  struct wm_softc *sc = (struct wm_softc*)arg;
1031
1032#ifdef WM_DEBUG
1033  printk("i82544EI_ifinit(): daemon ID: 0x%08x)\n", sc->daemonTid);
1034#endif
1035  if (sc->daemonTid) {
1036#ifdef WM_DEBUG
1037     printk("i82544EI: daemon already up, doing nothing\n");
1038#endif
1039     return;
1040  }
1041  i82544EI_init_hw(sc);
1042
1043  sc->daemonTid = rtems_bsdnet_newproc(i82544EI_TASK_NAME,4096,i82544EI_daemon,arg);
1044
1045  /* ...all done! */
1046  sc->arpcom.ac_if.if_flags |= IFF_RUNNING; 
1047
1048#ifdef WM_DEBUG
1049  printk(")");
1050#endif
1051}
1052
1053/*
1054 * wm_txdrain:
1055 *
1056 *      Drain the transmit queue.
1057 */
1058static void wm_txdrain(struct wm_softc *sc)
1059{
1060  int i;
1061
1062  /* Release any queued transmit buffers. */
1063  for (i = 0; i <  NTXDESC; i++) {
1064      if (sc->txs_mbuf[i] != NULL) {
1065          m_freem(sc->txs_mbuf[i]);
1066          sc->txs_mbuf[i] = NULL;
1067      }
1068  }
1069}
1070
1071/*
1072 * wm_rxdrain:
1073 *
1074 *      Drain the receive queue.
1075 */
1076static void wm_rxdrain(struct wm_softc *sc)
1077{
1078  int i;
1079
1080  for (i = 0; i < NRXDESC; i++) {
1081      if (sc->rxs_mbuf[i] != NULL) {
1082          m_freem(sc->rxs_mbuf[i]);
1083          sc->rxs_mbuf[i] = NULL;
1084      }
1085  }
1086}
1087
1088static void i82544EI_tx_stop(struct wm_softc *sc)
1089{
1090  wm_txdrain(sc);
1091}
1092
1093static void i82544EI_rx_stop(struct wm_softc *sc)
1094{
1095  wm_rxdrain(sc);
1096}
1097
1098static void i82544EI_stop_hw(struct wm_softc *sc)
1099{
1100#ifdef WM_DEBUG
1101  printk("i82544EI_stop_hw(");
1102#endif
1103
1104  /* remove our interrupt handler which will also
1105  * disable interrupts at the MPIC and the device
1106  * itself
1107  */
1108  if (!BSP_remove_rtems_irq_handler(&i82544IrqData))
1109     rtems_panic("i82544EI: unable to remove IRQ handler!");
1110
1111  CSR_WRITE(sc,WMREG_IMS, 0);
1112
1113  sc->arpcom.ac_if.if_flags &= ~IFF_RUNNING;
1114  i82544EI_tx_stop(sc);
1115  i82544EI_rx_stop(sc);
1116#ifdef WM_DEBUG
1117  printk(")");
1118#endif
1119}
1120
1121/*
1122 * wm_stop:             [ifnet interface function]
1123 *
1124 *      Stop transmission on the interface.
1125 */
1126static void wm_stop(struct ifnet *ifp, int disable)
1127{
1128  struct wm_softc *sc = ifp->if_softc;
1129
1130#ifdef WM_DEBUG
1131  printk("wm_stop(");
1132#endif 
1133  /* Stop the transmit and receive processes. */
1134  CSR_WRITE(sc,WMREG_TCTL, 0);
1135  CSR_WRITE(sc,WMREG_RCTL, 0);
1136
1137  wm_txdrain(sc);
1138  wm_rxdrain(sc);
1139
1140  /* Mark the interface as down  */
1141  ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1142#ifdef WM_DEBUG
1143  printk(")\n");
1144#endif 
1145}
1146
1147/*
1148 * wm_eeprom_sendbits:
1149 *
1150 *      Send a series of bits to the EEPROM.
1151 */
1152static void wm_eeprom_sendbits(struct wm_softc *sc, uint32_t bits, int nbits)
1153{
1154  uint32_t reg;
1155  int x;
1156
1157  reg = CSR_READ(sc,WMREG_EECD);
1158
1159  for (x = nbits; x > 0; x--) {
1160      if (bits & (1U << (x - 1)))
1161         reg |= EECD_DI;
1162      else
1163         reg &= ~EECD_DI;
1164      CSR_WRITE(sc,WMREG_EECD, reg);
1165      rtems_bsp_delay(2);
1166      CSR_WRITE(sc,WMREG_EECD, reg | EECD_SK);
1167      rtems_bsp_delay(2);
1168      CSR_WRITE(sc,WMREG_EECD, reg);
1169      rtems_bsp_delay(2);
1170  }
1171}
1172
1173/*
1174 * wm_eeprom_recvbits:
1175 *
1176 *      Receive a series of bits from the EEPROM.
1177 */
1178static void wm_eeprom_recvbits(struct wm_softc *sc, uint32_t *valp, int nbits)
1179{
1180  uint32_t reg, val;
1181  int x;
1182
1183  reg = CSR_READ(sc,WMREG_EECD) & ~EECD_DI;
1184
1185  val = 0;
1186  for (x = nbits; x > 0; x--) {
1187      CSR_WRITE(sc,WMREG_EECD, reg | EECD_SK);
1188      rtems_bsp_delay(2);
1189      if (CSR_READ(sc,WMREG_EECD) & EECD_DO)
1190         val |= (1U << (x - 1));
1191      CSR_WRITE(sc,WMREG_EECD, reg);
1192      rtems_bsp_delay(2);
1193  }
1194  *valp = val;
1195}
1196
1197/*
1198 * wm_read_eeprom_uwire:
1199 *
1200 * Read a word from the EEPROM using the MicroWire protocol.
1201 *
1202 * (The 82544EI Gigabit Ethernet Controller is compatible with
1203 * most MicroWire interface, serial EEPROM devices.)
1204 */
1205static int wm_read_eeprom_uwire(struct wm_softc *sc, int word, int wordcnt, uint16_t *data)
1206{
1207  uint32_t reg, val;
1208  int i;
1209
1210  for (i = 0; i < wordcnt; i++) {
1211      /* Clear SK and DI. */
1212      reg = CSR_READ(sc,WMREG_EECD) & ~(EECD_SK | EECD_DI);
1213      CSR_WRITE(sc,WMREG_EECD, reg);
1214
1215      /* Set CHIP SELECT. */
1216      reg |= EECD_CS;
1217      CSR_WRITE(sc,WMREG_EECD, reg);
1218      rtems_bsp_delay(2);
1219
1220      /* Shift in the READ command. */
1221      wm_eeprom_sendbits(sc, UWIRE_OPC_READ, 3);
1222
1223      /* Shift in address. */
1224      wm_eeprom_sendbits(sc, word + i, sc->sc_ee_addrbits);
1225
1226      /* Shift out the data. */
1227      wm_eeprom_recvbits(sc, &val, 16);
1228      data[i] = val & 0xffff;
1229
1230      /* Clear CHIP SELECT. */
1231      reg = CSR_READ(sc,WMREG_EECD) & ~EECD_CS;
1232      CSR_WRITE(sc,WMREG_EECD, reg);
1233      rtems_bsp_delay(2);
1234  }
1235  return (0);
1236}
1237
1238/*
1239 * wm_acquire_eeprom:
1240 *
1241 *      Perform the EEPROM handshake required on some chips.
1242 */
1243static int wm_acquire_eeprom(struct wm_softc *sc)
1244{
1245  uint32_t reg;
1246  int x;
1247
1248  reg = CSR_READ(sc,WMREG_EECD);
1249
1250  /* Request EEPROM access. */
1251  reg |= EECD_EE_REQ;
1252  CSR_WRITE(sc,WMREG_EECD, reg);
1253
1254  /* ..and wait for it to be granted. */
1255  for (x = 0; x < 100; x++) {
1256      reg = CSR_READ(sc,WMREG_EECD);
1257      if (reg & EECD_EE_GNT) break;
1258      rtems_bsp_delay(500);
1259  }
1260  if ((reg & EECD_EE_GNT) == 0) {
1261      printk("Could not acquire EEPROM GNT x= %d\n", x);
1262      reg &= ~EECD_EE_REQ;
1263      CSR_WRITE(sc,WMREG_EECD, reg);
1264      return (1);
1265  }
1266
1267  return (0);
1268}
1269
1270/*
1271 * wm_read_eeprom:
1272 *
1273 * Read data from the serial EEPROM.
1274 * 82544EI does not Perform the EEPROM handshake
1275 */
1276static int wm_read_eeprom(struct wm_softc *sc, int word, int wordcnt, uint16_t *data)
1277{
1278#if 0
1279  /* base on the datasheet, this does not seem to be applicable */
1280  if (wm_acquire_eeprom(sc))
1281     return(1);
1282#endif
1283  return(wm_read_eeprom_uwire(sc, word, wordcnt, data));
1284}
1285
1286/*
1287 * wm_add_rxbuf:
1288 *
1289 *      Add a receive buffer to the indiciated descriptor.
1290 */
1291static int wm_add_rxbuf(struct wm_softc *sc, int idx)
1292{
1293  struct mbuf *m;
1294
1295  MGETHDR(m, M_WAIT, MT_DATA);
1296  if (m == NULL) return (ENOBUFS);
1297  MCLGET(m, M_WAIT);
1298  if ((m->m_flags & M_EXT) == 0) {
1299     m_freem(m);
1300     return (ENOBUFS);
1301  }
1302  m->m_pkthdr.rcvif =  &sc->arpcom.ac_if;
1303  sc->rxs_mbuf[idx] = m;
1304  /*  m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;*/
1305  wm_init_rxdesc(sc, idx);
1306#if 0
1307  printk("sc->rxs_mbuf[%d]= 0x%x, mbuf @ 0x%x\n",
1308    idx, sc->rxs_mbuf[idx], le32toh(sc->sc_rxdescs[idx].wrx_addr.wa_low));
1309#endif
1310  return(0);
1311}
1312
1313/*
1314 * wm_set_ral:
1315 *
1316 *      Set an entery in the receive address list.
1317 */
1318static void
1319wm_set_ral(struct wm_softc *sc, const uint8_t *enaddr, int idx)
1320{
1321  uint32_t ral_lo, ral_hi;
1322
1323  if (enaddr != NULL) {
1324     ral_lo = enaddr[0]|(enaddr[1] << 8)|(enaddr[2] << 16)|(enaddr[3] << 24);
1325     ral_hi = enaddr[4] | (enaddr[5] << 8);
1326     ral_hi |= RAL_AV;
1327  } else {
1328     ral_lo = 0;
1329     ral_hi = 0;
1330  }
1331
1332  CSR_WRITE(sc,WMREG_RAL_LO(WMREG_CORDOVA_RAL_BASE, idx),ral_lo);
1333  CSR_WRITE(sc,WMREG_RAL_HI(WMREG_CORDOVA_RAL_BASE, idx),ral_hi);
1334}
1335
1336/*
1337 * wm_mchash:
1338 *
1339 *      Compute the hash of the multicast address for the 4096-bit
1340 *      multicast filter.
1341 */
1342static uint32_t
1343wm_mchash(struct wm_softc *sc, const uint8_t *enaddr)
1344{
1345  static const int lo_shift[4] = { 4, 3, 2, 0 };
1346  static const int hi_shift[4] = { 4, 5, 6, 8 };
1347  uint32_t hash;
1348
1349  hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) |
1350            (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]);
1351
1352  return (hash & 0xfff);
1353}
1354
1355/*
1356 * wm_set_filter: Set up the receive filter.
1357 */
1358static void wm_set_filter(struct wm_softc *sc)
1359{
1360  struct ifnet *ifp = &sc->arpcom.ac_if;
1361  struct ether_multi *enm;
1362  struct ether_multistep step;
1363  uint32_t mta_reg;
1364  uint32_t hash, reg, bit;
1365  int i;
1366
1367#ifdef WM_DEBUG
1368  printk("wm_set_filter(");
1369#endif 
1370  mta_reg = WMREG_CORDOVA_MTA;
1371  sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE);
1372
1373  /*  if (ifp->if_flags & IFF_BROADCAST)*/
1374     sc->sc_rctl |= RCTL_BAM;
1375  if (ifp->if_flags & IFF_PROMISC) {
1376     sc->sc_rctl |= RCTL_UPE;
1377     goto allmulti;
1378  }
1379
1380  /*
1381   * Set the station address in the first RAL slot, and
1382   * clear the remaining slots.
1383   */
1384  wm_set_ral(sc, sc->arpcom.ac_enaddr, 0);
1385  for (i = 1; i < WM_RAL_TABSIZE; i++)
1386      wm_set_ral(sc, NULL, i);
1387
1388  /* Clear out the multicast table. */
1389  for (i = 0; i < WM_MC_TABSIZE; i++)
1390      CSR_WRITE(sc,mta_reg + (i << 2), 0);
1391
1392  ETHER_FIRST_MULTI(step, &sc->arpcom, enm);
1393  while (enm != NULL) {
1394        if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
1395            /*
1396             * We must listen to a range of multicast addresses.
1397             * For now, just accept all multicasts, rather than
1398             * trying to set only those filter bits needed to match
1399             * the range.  (At this time, the only use of address
1400             * ranges is for IP multicast routing, for which the
1401             * range is big enough to require all bits set.)
1402             */
1403            goto allmulti;
1404         }
1405
1406         hash = wm_mchash(sc, enm->enm_addrlo);
1407
1408         reg = (hash >> 5) & 0x7f;
1409         bit = hash & 0x1f;
1410
1411         hash = CSR_READ(sc,mta_reg + (reg << 2));
1412         hash |= 1U << bit;
1413
1414         /* XXX Hardware bug?? */
1415         if ((reg & 0xe) == 1) {
1416            bit = CSR_READ(sc,mta_reg + ((reg - 1) << 2));
1417            CSR_WRITE(sc,mta_reg + (reg << 2), hash);
1418            CSR_WRITE(sc,mta_reg + ((reg - 1) << 2), bit);
1419         } else
1420            CSR_WRITE(sc,mta_reg + (reg << 2), hash);
1421
1422         ETHER_NEXT_MULTI(step, enm);
1423  }
1424
1425  ifp->if_flags &= ~IFF_ALLMULTI;
1426  goto setit;
1427
1428 allmulti:
1429  ifp->if_flags |= IFF_ALLMULTI;
1430  sc->sc_rctl |= RCTL_MPE;
1431
1432 setit:
1433  CSR_WRITE(sc,WMREG_RCTL, sc->sc_rctl);
1434
1435#ifdef WM_DEBUG
1436  printk("RCTL 0x%x)\n", CSR_READ(sc,WMREG_RCTL));
1437#endif 
1438}
1439
1440static void i82544EI_error(struct wm_softc *sc)
1441{
1442  struct ifnet          *ifp = &sc->arpcom.ac_if;
1443  unsigned long         intr_status= sc->intr_errsts[sc->intr_err_ptr1++];
1444
1445  /* read and reset the status; because this is written
1446   * by the ISR, we must disable interrupts here
1447   */
1448  sc->intr_err_ptr1 %=INTR_ERR_SIZE; /* Till Straumann */
1449  if (intr_status) {
1450    printk("Error %s%d:", ifp->if_name, ifp->if_unit);
1451    if (intr_status & ICR_RXSEQ) {
1452       printk("Rxq framing error (ICR= %x), if_ierrors %d\n",
1453              intr_status, ifp->if_ierrors);
1454    }
1455  }
1456  else 
1457    printk("%s%d: Ghost interrupt ?\n",ifp->if_name,ifp->if_unit);
1458}
1459
1460void i82544EI_printStats()
1461{
1462  i82544EI_stats(root_i82544EI_dev);
1463}
1464
1465/* The daemon does all of the work; RX, TX and cleaning up buffers/descriptors */
1466static void i82544EI_daemon(void *arg)
1467{
1468  struct wm_softc *sc = (struct wm_softc*)arg;
1469  rtems_event_set       events;
1470  struct mbuf   *m=0;
1471  struct ifnet  *ifp=&sc->arpcom.ac_if;
1472
1473#ifdef WM_DEBUG
1474  printk("i82544EI_daemon()\n");
1475#endif
1476
1477  /* NOTE: our creator possibly holds the bsdnet_semaphore.
1478   *       since that has PRIORITY_INVERSION enabled, our
1479   *       subsequent call to bsdnet_event_receive() will
1480   *       _not_ release it. It's still in posession of our
1481   *       owner.
1482   *       This is different from how killing this task
1483   *       is handled.
1484   */
1485
1486  for (;;) {
1487     /* sleep until there's work to be done */
1488     /* Note: bsdnet_event_receive() acquires
1489      *       the global bsdnet semaphore for
1490      *       mutual exclusion.
1491      */
1492     rtems_bsdnet_event_receive(ALL_EVENTS,
1493                                RTEMS_WAIT | RTEMS_EVENT_ANY,
1494                                RTEMS_NO_TIMEOUT,
1495                                &events);
1496     if (KILL_EVENT & events)  break;
1497
1498     if (events & RX_EVENT)  i82544EI_rx(sc);
1499
1500     /* clean up and try sending packets */
1501     do { 
1502        i82544EI_txq_done(sc);
1503
1504        while (sc->txq_free>0) {
1505           if (sc->txq_free>TXQ_HiLmt_OFF) {
1506              IF_DEQUEUE(&ifp->if_snd,m);
1507              if (m==0) break;
1508              i82544EI_sendpacket(sc, m); 
1509           }
1510           else {
1511              i82544EI_txq_done(sc);
1512              break;
1513           }
1514           if (events & RX_EVENT)  i82544EI_rx(sc);
1515        }
1516         /* we leave this loop
1517          *  - either because there's no free buffer
1518          *    (m=0 initializer && !sc->txq_free)
1519          *  - or there's nothing to send (IF_DEQUEUE
1520          *    returned 0
1521          */
1522     } while (m && sc->txq_free);
1523
1524     ifp->if_flags &= ~IFF_OACTIVE;
1525
1526     /* Log errors and other uncommon events. */
1527     if (events & ERR_EVENT) i82544EI_error(sc); 
1528     /* Rx overrun */
1529     if ( events & INIT_EVENT) {
1530        printk("Warnning, Rx overrun.  Make sure the old mbuf was free\n");
1531        i82544EI_ifinit(arg);
1532     }
1533
1534  } /* end for(;;) { rtems_bsdnet_event_receive() .....*/
1535
1536  printf("out of daemon\n");
1537  ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
1538
1539  /* shut down the hardware */
1540  i82544EI_stop_hw(sc);
1541  /* flush the output queue */
1542  for (;;) {
1543      IF_DEQUEUE(&ifp->if_snd,m);
1544      if (!m) break;
1545      m_freem(m);
1546  }
1547  /* as of 'rtems_bsdnet_event_receive()' we own the
1548   * networking semaphore
1549   */
1550  rtems_bsdnet_semaphore_release();
1551  rtems_semaphore_release(sc->daemonSync);
1552
1553  /* Note that I dont use sc->daemonTid here -
1554   * theoretically, that variable could already
1555   * hold a newly created TID
1556   */
1557  rtems_task_delete(RTEMS_SELF);
1558}
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