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GT64260ethreg.h @ 9b4422a2

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Last change on this file since 9b4422a2 was 9b4422a2, checked in by Joel Sherrill <joel.sherrill@…>, on 05/03/12 at 15:09:24

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1	/* $NetBSD: GT64260ethreg.h,v 1.2 2003/03/17 16:41:16 matt Exp $ */
2
3	/*
4	* Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
5	* All rights reserved.
6	*
7	* Redistribution and use in source and binary forms, with or without
8	* modification, are permitted provided that the following conditions
9	* are met:
10	* 1. Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.
12	* 2. Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.
15	* 3. All advertising materials mentioning features or use of this software
16	* must display the following acknowledgement:
17	* This product includes software developed for the NetBSD Project by
18	* Allegro Networks, Inc., and Wasabi Systems, Inc.
19	* 4. The name of Allegro Networks, Inc. may not be used to endorse
20	* or promote products derived from this software without specific prior
21	* written permission.
22	* 5. The name of Wasabi Systems, Inc. may not be used to endorse
23	* or promote products derived from this software without specific prior
24	* written permission.
25	*
26	* THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND
27	* WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
28	* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
29	* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
30	* IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC.
31	* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37	* POSSIBILITY OF SUCH DAMAGE.
38	*/
39
40	#ifndef _DEV_GTETHREG_H_
41	#define _DEV_GTETHREG_H_
42
43	#define ETH__BIT(bit) (1U << (bit))
44	#define ETH__LLBIT(bit) (1ULL << (bit))
45	#define ETH__MASK(bit) (ETH__BIT(bit) - 1)
46	#define ETH__LLMASK(bit) (ETH__LLBIT(bit) - 1)
47	#define ETH__GEN(n, off) (0x2400+((n) << 10)+(ETH__ ## off))
48	#define ETH__EXT(data, bit, len) (((data) >> (bit)) & ETH__MASK(len))
49	#define ETH__LLEXT(data, bit, len) (((data) >> (bit)) & ETH__LLMASK(len))
50	#define ETH__CLR(data, bit, len) ((data) &= ~(ETH__MASK(len) << (bit)))
51	#define ETH__INS(new, bit) ((new) << (bit))
52	#define ETH__LLINS(new, bit) ((unsigned long long)(new) << (bit))
53
54	/*
55	* Descriptors used for both receive & transmit data. Note that the descriptor
56	* must start on a 4LW boundary. Since the GT accesses the descriptor as
57	* two 64-bit quantities, we must present them 32bit quantities in the right
58	* order based on endianess.
59	*/
60
61	struct GTeth_desc {
62	#if defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN /* for mvme5500 */
63	unsigned ed_lencnt; /* Buffer size is hi 16 bits; Byte count (rx) is lo 16 */
64	unsigned ed_cmdsts; /* command (hi16)/status (lo16) bits */
65	unsigned ed_nxtptr; /* next descriptor (must be 4LW aligned) */
66	unsigned ed_bufptr; /* pointer to packet buffer */
67	#endif
68	#if defined(BYTE_ORDER) && BYTE_ORDER == LITTLE_ENDIAN
69	unsigned ed_cmdsts; /* command (hi16)/status (lo16) bits */
70	unsigned ed_lencnt; /* length is hi 16 bits; count (rx) is lo 16 */
71	unsigned ed_bufptr; /* pointer to packet buffer */
72	unsigned ed_nxtptr; /* next descriptor (must be 4LW aligned) */
73	#endif
74	};
75
76	/* Ethernet 0 address control (Low), Offset: 0xf200 */
77	#define RxBSnoopEn ETH__BIT(6) /* Rx buffer snoop enable,1=enable*/
78	#define TxBSnoopEn ETH__BIT(14) /* Tx buffer snoop enable */
79	#define RxDSnoopEn ETH__BIT(22) /* Rx descriptor snoop enable */
80	#define TxDSnoopEn ETH__BIT(30) /* Tx descriptor snoop enable */
81
82	/* Ethernet 0 address control (High), Offset: 0xf204 */
83	#define HashSnoopEn ETH__BIT(6) /* Hash Table snoop enable */
84
85	/* <skf> */
86	#define GT_CUU_Eth0_AddrCtrlLow 0xf200
87	#define GT_CUU_Eth0_AddrCtrlHigh 0xf204
88
89	/* Table 578: Ethernet TX Descriptor - Command/Status word
90	* All bits except F, EI, AM, O are only valid if TX_CMD_L is also set,
91	* otherwise should be 0 (tx).
92	*/
93
94	#define TX_STS_LC ETH__BIT(5) /* Late Collision */
95	#define TX_STS_UR ETH__BIT(6) /* Underrun error */
96	#define TX_STS_RL ETH__BIT(8) /* Retransmit Limit (excession coll) */
97	#define TX_STS_COL ETH__BIT(9) /* Collision Occurred */
98	#define TX_STS_RC(v) ETH__GETBITS(v, 10, 4) /* Retransmit Count */
99	#define TX_STS_ES ETH__BIT(15) /* Error Summary (LC\|UR\|RL) */
100	#define TX_CMD_L ETH__BIT(16) /* Last - End Of Packet */
101	#define TX_CMD_F ETH__BIT(17) /* First - Start Of Packet */
102	#define TX_CMD_P ETH__BIT(18) /* Pad Packet */
103	#define TX_CMD_GC ETH__BIT(22) /* Generate CRC */
104	#define TX_CMD_EI ETH__BIT(23) /* Enable Interrupt */
105	#define TX_CMD_AM ETH__BIT(30) /* Auto Mode */
106	#define TX_CMD_O ETH__BIT(31) /* Ownership (1=GT 0=CPU) */
107
108	#define TX_CMD_FIRST (TX_CMD_F\|TX_CMD_O)
109	#define TX_CMD_LAST (TX_CMD_L\|TX_CMD_GC\|TX_CMD_P\|TX_CMD_O)
110
111	/* Table 608: Ethernet RX Descriptor - Command/Status Word
112	* All bits except F, EI, AM, O are only valid if RX_CMD_L is also set,
113	* otherwise should be ignored (rx).
114	*/
115	#define RX_STS_CE ETH__BIT(0) /* CRC Error */
116	#define RX_STS_COL ETH__BIT(1) /* Collision sensed during reception */
117	#define RX_STS_LC ETH__BIT(5) /* Late Collision (Reserved) */
118	#define RX_STS_OR ETH__BIT(6) /* Overrun Error */
119	#define RX_STS_MFL ETH__BIT(7) /* Max Frame Len Error */
120	#define RX_STS_SF ETH__BIT(8) /* Short Frame Error (< 64 bytes) */
121	#define RX_STS_FT ETH__BIT(11) /* Frame Type (1 = 802.3) */
122	#define RX_STS_M ETH__BIT(12) /* Missed Frame */
123	#define RX_STS_HE ETH__BIT(13) /* Hash Expired (manual match) */
124	#define RX_STS_IGMP ETH__BIT(14) /* IGMP Packet */
125	#define RX_STS_ES ETH__BIT(15) /* Error Summary (CE\|COL\|LC\|OR\|MFL\|SF) */
126	#define RX_CMD_L ETH__BIT(16) /* Last - End Of Packet */
127	#define RX_CMD_F ETH__BIT(17) /* First - Start Of Packet */
128	#define RX_CMD_EI ETH__BIT(23) /* Enable Interrupt */
129	#define RX_CMD_AM ETH__BIT(30) /* Auto Mode */
130	#define RX_CMD_O ETH__BIT(31) /* Ownership (1=GT 0=CPU) */
131
132	/* Table 586: Hash Table Entry Fields
133	*/
134	#define HSH_V ETH__LLBIT(0) /* Entry is valid */
135	#define HSH_S ETH__LLBIT(1) /* Skip this entry */
136	#define HSH_RD ETH__LLBIT(2) /* Receive(1) / Discard (0) */
137	#define HSH_R ETH__LLBIT(2) /* Receive(1) */
138	#define HSH_PRIO_GET(v) ETH__LLEXT(v, 51, 2)
139	#define HSH_PRIO_INS(v) ETH__LLINS(v, 51)
140	#define HSH_ADDR_MASK 0x7fffff8LLU
141	#define HSH_LIMIT 12
142
143
144	#define ETH_EPAR 0x2000 /* PHY Address Register */
145	#define ETH_ESMIR 0x2010 /* SMI Register */
146
147	#define ETH_BASE_ETH0 0x2400 /* Ethernet0 Register Base */
148	#define ETH_BASE_ETH1 0x2800 /* Ethernet1 Register Base */
149	#define ETH_BASE_ETH2 0x2c00 /* Ethernet2 Register Base */
150	#define ETH_SIZE 0x0400 /* Register Space */
151
152	#define ETH__EBASE 0x0000 /* Base of Registers */
153	#define ETH__EPCR 0x0000 /* Port Config. Register */
154	#define ETH__EPCXR 0x0008 /* Port Config. Extend Reg */
155	#define ETH__EPCMR 0x0010 /* Port Command Register */
156	#define ETH__EPSR 0x0018 /* Port Status Register */
157	#define ETH__ESPR 0x0020 /* Port Serial Parameters Reg */
158	#define ETH__EHTPR 0x0028 /* Port Hash Table Pointer Reg*/
159	#define ETH__EFCSAL 0x0030 /* Flow Control Src Addr Low */
160	#define ETH__EFCSAH 0x0038 /* Flow Control Src Addr High */
161	#define ETH__ESDCR 0x0040 /* SDMA Configuration Reg */
162	#define ETH__ESDCMR 0x0048 /* SDMA Command Register */
163	#define ETH__EICR 0x0050 /* Interrupt Cause Register */
164	#define ETH__EIMR 0x0058 /* Interrupt Mask Register */
165	#define ETH__EFRDP0 0x0080 /* First Rx Desc Pointer 0 */
166	#define ETH__EFRDP1 0x0084 /* First Rx Desc Pointer 1 */
167	#define ETH__EFRDP2 0x0088 /* First Rx Desc Pointer 2 */
168	#define ETH__EFRDP3 0x008c /* First Rx Desc Pointer 3 */
169	#define ETH__ECRDP0 0x00a0 /* Current Rx Desc Pointer 0 */
170	#define ETH__ECRDP1 0x00a4 /* Current Rx Desc Pointer 1 */
171	#define ETH__ECRDP2 0x00a8 /* Current Rx Desc Pointer 2 */
172	#define ETH__ECRDP3 0x00ac /* Current Rx Desc Pointer 3 */
173	#define ETH__ECTDP0 0x00e0 /* Current Tx Desc Pointer 0 */
174	#define ETH__ECTDP1 0x00e4 /* Current Tx Desc Pointer 1 */
175	#define ETH__EDSCP2P0L 0x0060 /* IP Differentiated Services
176	CodePoint to Priority0 low */
177	#define ETH__EDSCP2P0H 0x0064 /* IP Differentiated Services
178	CodePoint to Priority0 high*/
179	#define ETH__EDSCP2P1L 0x0068 /* IP Differentiated Services
180	CodePoint to Priority1 low */
181	#define ETH__EDSCP2P1H 0x006c /* IP Differentiated Services
182	CodePoint to Priority1 high*/
183	#define ETH__EVPT2P 0x0068 /* VLAN Prio. Tag to Priority */
184	#define ETH__EMIBCTRS 0x0100 /* MIB Counters */
185
186	/* SKF : we are only concerned with the Ethernet0 for the mvme5500 board */
187	#define ETH0_EBASE 0x2400 /* Base of Registers */
188	#define ETH0_EPCR 0x2400 /* Port Config. Register */
189	#define ETH0_EPCXR 0x2408 /* Port Config. Extend Reg */
190	#define ETH0_EPCMR 0x2410 /* Port Command Register */
191	#define ETH0_EPSR 0x2418 /* Port Status Register */
192	#define ETH0_ESPR 0x2420 /* Port Serial Parameters Reg */
193	#define ETH0_EHTPR 0x2428 /* Port Hash Table Pointer Reg*/
194	#define ETH0_EFCSAL 0x2430 /* Flow Control Src Addr Low */
195	#define ETH0_EFCSAH 0x2438 /* Flow Control Src Addr High */
196	#define ETH0_ESDCR 0x2440 /* SDMA Configuration Reg */
197	#define ETH0_ESDCMR 0x2448 /* SDMA Command Register */
198	#define ETH0_EICR 0x2450 /* Interrupt Cause Register */
199	#define ETH0_EIMR 0x2458 /* Interrupt Mask Register */
200	#define ETH0_EFRDP0 0x2480 /* First Rx Desc Pointer 0 */
201	#define ETH0_EFRDP1 0x2484 /* First Rx Desc Pointer 1 */
202	#define ETH0_EFRDP2 0x2488 /* First Rx Desc Pointer 2 */
203	#define ETH0_EFRDP3 0x248c /* First Rx Desc Pointer 3 */
204	#define ETH0_ECRDP0 0x24a0 /* Current Rx Desc Pointer 0 */
205	#define ETH0_ECRDP1 0x24a4 /* Current Rx Desc Pointer 1 */
206	#define ETH0_ECRDP2 0x24a8 /* Current Rx Desc Pointer 2 */
207	#define ETH0_ECRDP3 0x24ac /* Current Rx Desc Pointer 3 */
208	#define ETH0_ECTDP0 0x24e0 /* Current Tx Desc Pointer 0 */
209	#define ETH0_ECTDP1 0x24e4 /* Current Tx Desc Pointer 1 */
210	#define ETH0_EDSCP2P0L 0x2460 /* IP Differentiated Services
211	CodePoint to Priority0 low */
212	#define ETH0_EDSCP2P0H 0x2464 /* IP Differentiated Services
213	CodePoint to Priority0 high*/
214	#define ETH0_EDSCP2P1L 0x2468 /* IP Differentiated Services
215	CodePoint to Priority1 low */
216	#define ETH0_EDSCP2P1H 0x246c /* IP Differentiated Services
217	CodePoint to Priority1 high*/
218	#define ETH0_EVPT2P 0x2468 /* VLAN Prio. Tag to Priority */
219	#define ETH0_EMIBCTRS 0x2500 /* MIB Counters */
220
221	#define ETH_BASE(n) ETH__GEN(n, EBASE)
222	#define ETH_EPCR(n) ETH__GEN(n, EPCR) /* Port Config. Register */
223	#define ETH_EPCXR(n) ETH__GEN(n, EPCXR) /* Port Config. Extend Reg */
224	#define ETH_EPCMR(n) ETH__GEN(n, EPCMR) /* Port Command Register */
225	#define ETH_EPSR(n) ETH__GEN(n, EPSR) /* Port Status Register */
226	#define ETH_ESPR(n) ETH__GEN(n, ESPR) /* Port Serial Parameters Reg */
227	#define ETH_EHTPR(n) ETH__GEN(n, EHPTR) /* Port Hash Table Pointer Reg*/
228	#define ETH_EFCSAL(n) ETH__GEN(n, EFCSAL) /* Flow Control Src Addr Low */
229	#define ETH_EFCSAH(n) ETH__GEN(n, EFCSAH) /* Flow Control Src Addr High */
230	#define ETH_ESDCR(n) ETH__GEN(n, ESDCR) /* SDMA Configuration Reg */
231	#define ETH_ESDCMR(n) ETH__GEN(n, ESDCMR) /* SDMA Command Register */
232	#define ETH_EICR(n) ETH__GEN(n, EICR) /* Interrupt Cause Register */
233	#define ETH_EIMR(n) ETH__GEN(n, EIMR) /* Interrupt Mask Register */
234	#define ETH_EFRDP0(n) ETH__GEN(n, EFRDP0) /* First Rx Desc Pointer 0 */
235	#define ETH_EFRDP1(n) ETH__GEN(n, EFRDP1) /* First Rx Desc Pointer 1 */
236	#define ETH_EFRDP2(n) ETH__GEN(n, EFRDP2) /* First Rx Desc Pointer 2 */
237	#define ETH_EFRDP3(n) ETH__GEN(n, EFRDP3) /* First Rx Desc Pointer 3 */
238	#define ETH_ECRDP0(n) ETH__GEN(n, ECRDP0) /* Current Rx Desc Pointer 0 */
239	#define ETH_ECRDP1(n) ETH__GEN(n, ECRDP1) /* Current Rx Desc Pointer 1 */
240	#define ETH_ECRDP2(n) ETH__GEN(n, ECRDP2) /* Current Rx Desc Pointer 2 */
241	#define ETH_ECRDP3(n) ETH__GEN(n, ECRDP3) /* Current Rx Desc Pointer 3 */
242	#define ETH_ECTDP0(n) ETH__GEN(n, ECTDP0) /* Current Tx Desc Pointer 0 */
243	#define ETH_ECTDP1(n) ETH__GEN(n, ECTDP1) /* Current Tx Desc Pointer 1 */
244	#define ETH_EDSCP2P0L(n) ETH__GEN(n, EDSCP2P0L) /* IP Differentiated Services
245	CodePoint to Priority0 low */
246	#define ETH_EDSCP2P0H(n) ETH__GEN(n, EDSCP2P0H) /* IP Differentiated Services
247	CodePoint to Priority0 high*/
248	#define ETH_EDSCP2P1L(n) ETH__GEN(n, EDSCP2P1L) /* IP Differentiated Services
249	CodePoint to Priority1 low */
250	#define ETH_EDSCP2P1H(n) ETH__GEN(n, EDSCP1P1H) /* IP Differentiated Services
251	CodePoint to Priority1 high*/
252	#define ETH_EVPT2P(n) ETH__GEN(n, EVPT2P) /* VLAN Prio. Tag to Priority */
253	#define ETH_EMIBCTRS(n) ETH__GEN(n, EMIBCTRS) /* MIB Counters */
254
255	#define ETH_EPAR_PhyAD_GET(v, n) (((v) >> ((n) * 5)) & 0x1f)
256
257	#define ETH_ESMIR_READ(phy, reg) (ETH__INS(phy, 16)\|\
258	ETH__INS(reg, 21)\|\
259	ETH_ESMIR_ReadOpcode)
260	#define ETH_ESMIR_WRITE(phy, reg, val) (ETH__INS(phy, 16)\|\
261	ETH__INS(reg, 21)\|\
262	ETH__INS(val, 0)\|\
263	ETH_ESMIR_WriteOpcode)
264	#define ETH_ESMIR_Value_GET(v) ETH__EXT(v, 0, 16)
265	#define ETH_ESMIR_WriteOpcode 0
266	#define ETH_ESMIR_ReadOpcode ETH__BIT(26)
267	#define ETH_ESMIR_ReadValid ETH__BIT(27)
268	#define ETH_ESMIR_Busy ETH__BIT(28)
269
270	/*
271	* Table 597: Port Configuration Register (PCR)
272	* 00:00 PM Promiscuous mode
273	* 0: Normal mode (Frames are only received if the
274	* destination address is found in the hash
275	* table)
276	* 1: Promiscuous mode (Frames are received
277	* regardless of their destination address.
278	* Errored frames are discarded unless the Port
279	* Configuration register's PBF bit is set)
280	* 01:01 RBM Reject Broadcast Mode
281	* 0: Receive broadcast address
282	* 1: Reject frames with broadcast address
283	* Overridden by the promiscuous mode.
284	* 02:02 PBF Pass Bad Frames
285	* (0: Normal mode, 1: Pass bad Frames)
286	* The Ethernet receiver passes to the CPU errored
287	* frames (like fragments and collided packets)
288	* that are normally rejected.
289	* NOTE: Frames are only passed if they
290	* successfully pass address filtering.
291	* 06:03 Reserved
292	* 07:07 EN Enable (0: Disabled, 1: Enable)
293	* When enabled, the ethernet port is ready to
294	* transmit/receive.
295	* 09:08 LPBK Loop Back Mode
296	* 00: Normal mode
297	* 01: Internal loop back mode (TX data is looped
298	* back to the RX lines. No transition is seen
299	* on the interface pins)
300	* 10: External loop back mode (TX data is looped
301	* back to the RX lines and also transmitted
302	* out to the MII interface pins)
303	* 11: Reserved
304	* 10:10 FC Force Collision
305	* 0: Normal mode.
306	* 1: Force Collision on any TX frame.
307	* For RXM test (in Loopback mode).
308	* 11:11 Reserved.
309	* 12:12 HS Hash Size
310	* 0: 8K address filtering
311	* (256KB of memory space required).
312	* 1: 512 address filtering
313	* ( 16KB of memory space required).
314	* 13:13 HM Hash Mode (0: Hash Func. 0; 1: Hash Func. 1)
315	* 14:14 HDM Hash Default Mode
316	* 0: Discard addresses not found in address table
317	* 1: Pass addresses not found in address table
318	* 15:15 HD Duplex Mode (0: Half Duplex, 1: Full Duplex)
319	* NOTE: Valid only when auto-negotiation for
320	* duplex mode is disabled.
321	* 30:16 Reserved
322	* 31:31 ACCS Accelerate Slot Time
323	* (0: Normal mode, 1: Reserved)
324	*/
325	#define ETH_EPCR_PM ETH__BIT(0)
326	#define ETH_EPCR_RBM ETH__BIT(1)
327	#define ETH_EPCR_PBF ETH__BIT(2)
328	#define ETH_EPCR_EN ETH__BIT(7)
329	#define ETH_EPCR_LPBK_GET(v) ETH__BIT(v, 8, 2)
330	#define ETH_EPCR_LPBK_Normal 0
331	#define ETH_EPCR_LPBK_Internal 1
332	#define ETH_EPCR_LPBK_External 2
333	#define ETH_EPCR_FC ETH__BIT(10)
334
335	#define ETH_EPCR_HS ETH__BIT(12)
336	#define ETH_EPCR_HS_8K 0
337	#define ETH_EPCR_HS_512 ETH_EPCR_HS
338
339	#define ETH_EPCR_HM ETH__BIT(13)
340	#define ETH_EPCR_HM_0 0
341	#define ETH_EPCR_HM_1 ETH_EPCR_HM
342
343	#define ETH_EPCR_HDM ETH__BIT(14)
344	#define ETH_EPCR_HDM_Discard 0
345	#define ETH_EPCR_HDM_Pass ETH_EPCR_HDM
346
347	#define ETH_EPCR_HD_Half 0
348	#define ETH_EPCR_HD_Full ETH_EPCR_HD_Full
349
350	#define ETH_EPCR_ACCS ETH__BIT(31)
351
352
353
354	/*
355	* Table 598: Port Configuration Extend Register (PCXR)
356	* 00:00 IGMP IGMP Packets Capture Enable
357	* 0: IGMP packets are treated as normal Multicast
358	* packets.
359	* 1: IGMP packets on IPv4/Ipv6 over Ethernet/802.3
360	* are trapped and sent to high priority RX
361	* queue.
362	* 01:01 SPAN Spanning Tree Packets Capture Enable
363	* 0: BPDU (Bridge Protocol Data Unit) packets are
364	* treated as normal Multicast packets.
365	* 1: BPDU packets are trapped and sent to high
366	* priority RX queue.
367	* 02:02 PAR Partition Enable (0: Normal, 1: Partition)
368	* When more than 61 collisions occur while
369	* transmitting, the port enters Partition mode.
370	* It waits for the first good packet from the
371	* wire and then goes back to Normal mode. Under
372	* Partition mode it continues transmitting, but
373	* it does not receive.
374	* 05:03 PRIOtx Priority weight in the round-robin between high
375	* and low priority TX queues.
376	* 000: 1 pkt from HIGH, 1 pkt from LOW.
377	* 001: 2 pkt from HIGH, 1 pkt from LOW.
378	* 010: 4 pkt from HIGH, 1 pkt from LOW.
379	* 011: 6 pkt from HIGH, 1 pkt from LOW.
380	* 100: 8 pkt from HIGH, 1 pkt from LOW.
381	* 101: 10 pkt from HIGH, 1 pkt from LOW.
382	* 110: 12 pkt from HIGH, 1 pkt from LOW.
383	* 111: All pkt from HIGH, 0 pkt from LOW. LOW is
384	* served only if HIGH is empty.
385	* NOTE: If the HIGH queue is emptied before
386	* finishing the count, the count is reset
387	* until the next first HIGH comes in.
388	* 07:06 PRIOrx Default Priority for Packets Received on this
389	* Port (00: Lowest priority, 11: Highest priority)
390	* 08:08 PRIOrx_Override Override Priority for Packets Received on this
391	* Port (0: Do not override, 1: Override with
392	* <PRIOrx> field)
393	* 09:09 DPLXen Enable Auto-negotiation for Duplex Mode
394	* (0: Enable, 1: Disable)
395	* 11:10 FCTLen Enable Auto-negotiation for 802.3x Flow-control
396	* 0: Enable; When enabled, 1 is written (through
397	* SMI access) to the PHY's register 4 bit 10
398	* to advertise flow-control capability.
399	* 1: Disable; Only enables flow control after the
400	* PHY address is set by the CPU. When changing
401	* the PHY address the flow control
402	* auto-negotiation must be disabled.
403	* 11:11 FLP Force Link Pass
404	* (0: Force Link Pass, 1: Do NOT Force Link pass)
405	* 12:12 FCTL 802.3x Flow-Control Mode (0: Enable, 1: Disable)
406	* NOTE: Only valid when auto negotiation for flow
407	* control is disabled.
408	* 13:13 Reserved
409	* 15:14 MFL Max Frame Length
410	* Maximum packet allowed for reception (including
411	* CRC): 00: 1518 bytes, 01: 1536 bytes,
412	* 10: 2048 bytes, 11: 64K bytes
413	* 16:16 MIBclrMode MIB Counters Clear Mode (0: Clear, 1: No effect)
414	* 17:17 MIBctrMode Reserved. (MBZ)
415	* 18:18 Speed Port Speed (0: 10Mbit/Sec, 1: 100Mbit/Sec)
416	* NOTE: Only valid if SpeedEn bit is set.
417	* 19:19 SpeedEn Enable Auto-negotiation for Speed
418	* (0: Enable, 1: Disable)
419	* 20:20 RMIIen RMII enable
420	* 0: Port functions as MII port
421	* 1: Port functions as RMII port
422	* 21:21 DSCPen DSCP enable
423	* 0: IP DSCP field decoding is disabled.
424	* 1: IP DSCP field decoding is enabled.
425	* 31:22 Reserved
426	*/
427	#define ETH_EPCXR_IGMP ETH__BIT(0)
428	#define ETH_EPCXR_SPAN ETH__BIT(1)
429	#define ETH_EPCXR_PAR ETH__BIT(2)
430	#define ETH_EPCXR_PRIOtx_GET(v) ETH__EXT(v, 3, 3)
431	#define ETH_EPCXR_PRIOrx_GET(v) ETH__EXT(v, 3, 3)
432	#define ETH_EPCXR_PRIOrx_Override ETH__BIT(8)
433	#define ETH_EPCXR_DLPXen ETH__BIT(9)
434	#define ETH_EPCXR_FCTLen ETH__BIT(10)
435	#define ETH_EPCXR_FLP ETH__BIT(11)
436	#define ETH_EPCXR_FCTL ETH__BIT(12)
437	#define ETH_EPCXR_MFL_GET(v) ETH__EXT(v, 14, 2)
438	#define ETH_EPCXR_MFL_1518 0
439	#define ETH_EPCXR_MFL_1536 1
440	#define ETH_EPCXR_MFL_2048 2
441	#define ETH_EPCXR_MFL_64K 3
442	#define ETH_EPCXR_MIBclrMode ETH__BIT(16)
443	#define ETH_EPCXR_MIBctrMode ETH__BIT(17)
444	#define ETH_EPCXR_Speed ETH__BIT(18)
445	#define ETH_EPCXR_SpeedEn ETH__BIT(19)
446	#define ETH_EPCXR_RMIIEn ETH__BIT(20)
447	#define ETH_EPCXR_DSCPEn ETH__BIT(21)
448
449
450
451	/*
452	* Table 599: Port Command Register (PCMR)
453	* 14:00 Reserved
454	* 15:15 FJ Force Jam / Flow Control
455	* When in half-duplex mode, the CPU uses this bit
456	* to force collisions on the Ethernet segment.
457	* When the CPU recognizes that it is going to run
458	* out of receive buffers, it can force the
459	* transmitter to send jam frames, forcing
460	* collisions on the wire. To allow transmission
461	* on the Ethernet segment, the CPU must clear the
462	* FJ bit when more resources are available. When
463	* in full-duplex and flow-control is enabled, this
464	* bit causes the port's transmitter to send
465	* flow-control PAUSE packets. The CPU must reset
466	* this bit when more resources are available.
467	* 31:16 Reserved
468	*/
469
470	#define ETH_EPCMR_FJ ETH__BIT(15)
471
472
473	/*
474	* Table 600: Port Status Register (PSR) -- Read Only
475	* 00:00 Speed Indicates Port Speed (0: 10Mbs, 1: 100Mbs)
476	* 01:01 Duplex Indicates Port Duplex Mode (0: Half, 1: Full)
477	* 02:02 Fctl Indicates Flow-control Mode
478	* (0: enabled, 1: disabled)
479	* 03:03 Link Indicates Link Status (0: down, 1: up)
480	* 04:04 Pause Indicates that the port is in flow-control
481	* disabled state. This bit is set when an IEEE
482	* 802.3x flow-control PAUSE (XOFF) packet is
483	* received (assuming that flow-control is
484	* enabled and the port is in full-duplex mode).
485	* Reset when XON is received, or when the XOFF
486	* timer has expired.
487	* 05:05 TxLow Tx Low Priority Status
488	* Indicates the status of the low priority
489	* transmit queue: (0: Stopped, 1: Running)
490	* 06:06 TxHigh Tx High Priority Status
491	* Indicates the status of the high priority
492	* transmit queue: (0: Stopped, 1: Running)
493	* 07:07 TXinProg TX in Progress
494	* Indicates that the port's transmitter is in an
495	* active transmission state.
496	* 31:08 Reserved
497	*/
498	#define ETH_EPSR_Speed ETH__BIT(0)
499	#define ETH_EPSR_Duplex ETH__BIT(1)
500	#define ETH_EPSR_Fctl ETH__BIT(2)
501	#define ETH_EPSR_Link ETH__BIT(3)
502	#define ETH_EPSR_Pause ETH__BIT(4)
503	#define ETH_EPSR_TxLow ETH__BIT(5)
504	#define ETH_EPSR_TxHigh ETH__BIT(6)
505	#define ETH_EPSR_TXinProg ETH__BIT(7)
506
507
508	/*
509	* Table 601: Serial Parameters Register (SPR)
510	* 01:00 JAM_LENGTH Two bits to determine the JAM Length
511	* (in Backpressure) as follows:
512	* 00 = 12K bit-times
513	* 01 = 24K bit-times
514	* 10 = 32K bit-times
515	* 11 = 48K bit-times
516	* 06:02 JAM_IPG Five bits to determine the JAM IPG.
517	* The step is four bit-times. The value may vary
518	* between 4 bit time to 124.
519	* 11:07 IPG_JAM_TO_DATA Five bits to determine the IPG JAM to DATA.
520	* The step is four bit-times. The value may vary
521	* between 4 bit time to 124.
522	* 16:12 IPG_DATA Inter-Packet Gap (IPG)
523	* The step is four bit-times. The value may vary
524	* between 12 bit time to 124.
525	* NOTE: These bits may be changed only when the
526	* Ethernet ports is disabled.
527	* 21:17 Data_Blind Data Blinder
528	* The number of nibbles from the beginning of the
529	* IPG, in which the IPG counter is restarted when
530	* detecting a carrier activity. Following this
531	* value, the port enters the Data Blinder zone and
532	* does not reset the IPG counter. This ensures
533	* fair access to the medium.
534	* The default is 10 hex (64 bit times - 2/3 of the
535	* default IPG). The step is 4 bit-times. Valid
536	* range is 3 to 1F hex nibbles.
537	* NOTE: These bits may be only changed when the
538	* Ethernet port is disabled.
539	* 22:22 Limit4 The number of consecutive packet collisions that
540	* occur before the collision counter is reset.
541	* 0: The port resets its collision counter after
542	* 16 consecutive retransmit trials and
543	* restarts the Backoff algorithm.
544	* 1: The port resets its collision counter and
545	* restarts the Backoff algorithm after 4
546	* consecutive transmit trials.
547	* 31:23 Reserved
548	*/
549	#define ETH_ESPR_JAM_LENGTH_GET(v) ETH__EXT(v, 0, 2)
550	#define ETH_ESPR_JAM_IPG_GET(v) ETH__EXT(v, 2, 5)
551	#define ETH_ESPR_IPG_JAM_TO_DATA_GET(v) ETH__EXT(v, 7, 5)
552	#define ETH_ESPR_IPG_DATA_GET(v) ETH__EXT(v, 12, 5)
553	#define ETH_ESPR_Data_Bilnd_GET(v) ETH__EXT(v, 17, 5)
554	#define ETH_ESPR_Limit4(v) ETH__BIT(22)
555
556	/*
557	* Table 602: Hash Table Pointer Register (HTPR)
558	* 31:00 HTP 32-bit pointer to the address table.
559	* Bits [2:0] must be set to zero.
560	*/
561
562	/*
563	* Table 603: Flow Control Source Address Low (FCSAL)
564	* 15:0 SA[15:0] Source Address
565	* The least significant bits of the source
566	* address for the port. This address is used for
567	* Flow Control.
568	* 31:16 Reserved
569	*/
570
571	/*
572	* Table 604: Flow Control Source Address High (FCSAH)
573	* 31:0 SA[47:16] Source Address
574	* The most significant bits of the source address
575	* for the port. This address is used for Flow
576	* Control.
577	*/
578
579
580	/*
581	* Table 605: SDMA Configuration Register (SDCR)
582	* 01:00 Reserved
583	* 05:02 RC Retransmit Count
584	* Sets the maximum number of retransmits per
585	* packet. After executing retransmit for RC
586	* times, the TX SDMA closes the descriptor with a
587	* Retransmit Limit error indication and processes
588	* the next packet. When RC is set to 0, the
589	* number of retransmits is unlimited. In this
590	* case, the retransmit process is only terminated
591	* if CPU issues an Abort command.
592	* 06:06 BLMR Big/Little Endian Receive Mode
593	* The DMA supports Big or Little Endian
594	* configurations on a per channel basis. The BLMR
595	* bit only affects data transfer to memory.
596	* 0: Big Endian
597	* 1: Little Endian
598	* 07:07 BLMT Big/Little Endian Transmit Mode
599	* The DMA supports Big or Little Endian
600	* configurations on a per channel basis. The BLMT
601	* bit only affects data transfer from memory.
602	* 0: Big Endian
603	* 1: Little Endian
604	* 08:08 POVR PCI Override
605	* When set, causes the SDMA to direct all its
606	* accesses in PCI_0 direction and overrides
607	* normal address decoding process.
608	* 09:09 RIFB Receive Interrupt on Frame Boundaries
609	* When set, the SDMA Rx generates interrupts only
610	* on frame boundaries (i.e. after writing the
611	* frame status to the descriptor).
612	* 11:10 Reserved
613	* 13:12 BSZ Burst Size
614	* Sets the maximum burst size for SDMA
615	* transactions:
616	* 00: Burst is limited to 1 64bit words.
617	* 01: Burst is limited to 2 64bit words.
618	* 10: Burst is limited to 4 64bit words.
619	* 11: Burst is limited to 8 64bit words.
620	* 31:14 Reserved
621	*/
622	#define ETH_ESDCR_RC_GET(v) ETH__EXT(v, 2, 4)
623	#define ETH_ESDCR_BLMR ETH__BIT(6)
624	#define ETH_ESDCR_BLMT ETH__BIT(7)
625	#define ETH_ESDCR_POVR ETH__BIT(8)
626	#define ETH_ESDCR_RIFB ETH__BIT(9)
627	#define ETH_ESDCR_BSZ_GET(v) ETH__EXT(v, 12, 2)
628	#define ETH_ESDCR_BSZ_SET(v, n) (ETH__CLR(v, 12, 2),\
629	(v) \|= ETH__INS(n, 12))
630	#define ETH_ESDCR_BSZ_1 0
631	#define ETH_ESDCR_BSZ_2 1
632	#define ETH_ESDCR_BSZ_4 2
633	#define ETH_ESDCR_BSZ_8 3
634
635	#define ETH_ESDCR_BSZ_Strings { "1 64-bit word", "2 64-bit words", \
636	"4 64-bit words", "8 64-bit words" }
637
638	/*
639	* Table 606: SDMA Command Register (SDCMR)
640	* 06:00 Reserved
641	* 07:07 ERD Enable RX DMA.
642	* Set to 1 by the CPU to cause the SDMA to start
643	* a receive process. Cleared when the CPU issues
644	* an Abort Receive command.
645	* 14:08 Reserved
646	* 15:15 AR Abort Receive
647	* Set to 1 by the CPU to abort a receive SDMA
648	* operation. When the AR bit is set, the SDMA
649	* aborts its current operation and moves to IDLE.
650	* No descriptor is closed. The AR bit is cleared
651	* upon entering IDLE. After setting the AR bit,
652	* the CPU must poll the bit to verify that the
653	* abort sequence is completed.
654	* 16:16 STDH Stop TX High
655	* Set to 1 by the CPU to stop the transmission
656	* process from the high priority queue at the end
657	* of the current frame. An interrupt is generated
658	* when the stop command has been executed.
659	* Writing 1 to STDH resets TXDH bit.
660	* Writing 0 to this bit has no effect.
661	* 17:17 STDL Stop TX Low
662	* Set to 1 by the CPU to stop the transmission
663	* process from the low priority queue at the end
664	* of the current frame. An interrupt is generated
665	* when the stop command has been executed.
666	* Writing 1 to STDL resets TXDL bit.
667	* Writing 0 to this bit has no effect.
668	* 22:18 Reserved
669	* 23:23 TXDH Start Tx High
670	* Set to 1 by the CPU to cause the SDMA to fetch
671	* the first descriptor and start a transmit
672	* process from the high priority Tx queue.
673	* Writing 1 to TXDH resets STDH bit.
674	* Writing 0 to this bit has no effect.
675	* 24:24 TXDL Start Tx Low
676	* Set to 1 by the CPU to cause the SDMA to fetch
677	* the first descriptor and start a transmit
678	* process from the low priority Tx queue.
679	* Writing 1 to TXDL resets STDL bit.
680	* Writing 0 to this bit has no effect.
681	* 30:25 Reserved
682	* 31:31 AT Abort Transmit
683	* Set to 1 by the CPU to abort a transmit DMA
684	* operation. When the AT bit is set, the SDMA
685	* aborts its current operation and moves to IDLE.
686	* No descriptor is closed. Cleared upon entering
687	* IDLE. After setting AT bit, the CPU must poll
688	* it in order to verify that the abort sequence
689	* is completed.
690	*/
691	#define ETH_ESDCMR_ERD ETH__BIT(7)
692	#define ETH_ESDCMR_AR ETH__BIT(15)
693	#define ETH_ESDCMR_STDH ETH__BIT(16)
694	#define ETH_ESDCMR_STDL ETH__BIT(17)
695	#define ETH_ESDCMR_TXDH ETH__BIT(23)
696	#define ETH_ESDCMR_TXDL ETH__BIT(24)
697	#define ETH_ESDCMR_AT ETH__BIT(31)
698
699	/*
700	* Table 607: Interrupt Cause Register (ICR)
701	* 00:00 RxBuffer Rx Buffer Return
702	* Indicates an Rx buffer returned to CPU ownership
703	* or that the port finished reception of a Rx
704	* frame in either priority queues.
705	* NOTE: In order to get a Rx Buffer return per
706	* priority queue, use bit 19:16. This bit is
707	* set upon closing any Rx descriptor which
708	* has its EI bit set. To limit the
709	* interrupts to frame (rather than buffer)
710	* boundaries, the user must set SDMA
711	* Configuration register's RIFB bit. When
712	* the RIFB bit is set, an interrupt
713	* generates only upon closing the first
714	* descriptor of a received packet, if this
715	* descriptor has it EI bit set.
716	* 01:01 Reserved
717	* 02:02 TxBufferHigh Tx Buffer for High priority Queue
718	* Indicates a Tx buffer returned to CPU ownership
719	* or that the port finished transmission of a Tx
720	* frame.
721	* NOTE: This bit is set upon closing any Tx
722	* descriptor which has its EI bit set. To
723	* limit the interrupts to frame (rather than
724	* buffer) boundaries, the user must set EI
725	* only in the last descriptor.
726	* 03:03 TxBufferLow Tx Buffer for Low Priority Queue
727	* Indicates a Tx buffer returned to CPU ownership
728	* or that the port finished transmission of a Tx
729	* frame.
730	* NOTE: This bit is set upon closing any Tx
731	* descriptor which has its EI bit set. To
732	* limit the interrupts to frame (rather than
733	* buffer) boundaries, the user must set EI
734	* only in the last descriptor.
735	* 05:04 Reserved
736	* 06:06 TxEndHigh Tx End for High Priority Queue
737	* Indicates that the Tx DMA stopped processing the
738	* high priority queue after stop command, or that
739	* it reached the end of the high priority
740	* descriptor chain.
741	* 07:07 TxEndLow Tx End for Low Priority Queue
742	* Indicates that the Tx DMA stopped processing the
743	* low priority queue after stop command, or that
744	* it reached the end of the low priority
745	* descriptor chain.
746	* 08:08 RxError Rx Resource Error
747	* Indicates a Rx resource error event in one of
748	* the priority queues.
749	* NOTE: To get a Rx Resource Error Indication per
750	* priority queue, use bit 23:20.
751	* 09:09 Reserved
752	* 10:10 TxErrorHigh Tx Resource Error for High Priority Queue
753	* Indicates a Tx resource error event during
754	* packet transmission from the high priority queue
755	* 11:11 TxErrorLow Tx Resource Error for Low Priority Queue
756	* Indicates a Tx resource error event during
757	* packet transmission from the low priority queue
758	* 12:12 RxOVR Rx Overrun
759	* Indicates an overrun event that occurred during
760	* reception of a packet.
761	* 13:13 TxUdr Tx Underrun
762	* Indicates an underrun event that occurred during
763	* transmission of packet from either queue.
764	* 15:14 Reserved
765	* 16:16 RxBuffer-Queue[0] Rx Buffer Return in Priority Queue[0]
766	* Indicates a Rx buffer returned to CPU ownership
767	* or that the port completed reception of a Rx
768	* frame in a receive priority queue[0]
769	* 17:17 RxBuffer-Queue[1] Rx Buffer Return in Priority Queue[1]
770	* Indicates a Rx buffer returned to CPU ownership
771	* or that the port completed reception of a Rx
772	* frame in a receive priority queue[1].
773	* 18:18 RxBuffer-Queue[2] Rx Buffer Return in Priority Queue[2]
774	* Indicates a Rx buffer returned to CPU ownership
775	* or that the port completed reception of a Rx
776	* frame in a receive priority queue[2].
777	* 19:19 RxBuffer-Queue[3] Rx Buffer Return in Priority Queue[3]
778	* Indicates a Rx buffer returned to CPU ownership
779	* or that the port completed reception of a Rx
780	* frame in a receive priority queue[3].
781	* 20:20 RxError-Queue[0] Rx Resource Error in Priority Queue[0]
782	* Indicates a Rx resource error event in receive
783	* priority queue[0].
784	* 21:21 RxError-Queue[1] Rx Resource Error in Priority Queue[1]
785	* Indicates a Rx resource error event in receive
786	* priority queue[1].
787	* 22:22 RxError-Queue[2] Rx Resource Error in Priority Queue[2]
788	* Indicates a Rx resource error event in receive
789	* priority queue[2].
790	* 23:23 RxError-Queue[3] Rx Resource Error in Priority Queue[3]
791	* Indicates a Rx resource error event in receive
792	* priority queue[3].
793	* 27:24 Reserved
794	* 28:29 MIIPhySTC MII PHY Status Change
795	* Indicates a status change reported by the PHY
796	* connected to this port. Set when the MII
797	* management interface block identifies a change
798	* in PHY's register 1.
799	* 29:29 SMIdone SMI Command Done
800	* Indicates that the SMI completed a MII
801	* management command (either read or write) that
802	* was initiated by the CPU writing to the SMI
803	* register.
804	* 30:30 Reserved
805	* 31:31 EtherIntSum Ethernet Interrupt Summary
806	* This bit is a logical OR of the (unmasked) bits
807	* [30:04] in the Interrupt Cause register.
808	*/
809
810	#define ETH_IR_RxBuffer ETH__BIT(0)
811	#define ETH_IR_TxBufferHigh ETH__BIT(2)
812	#define ETH_IR_TxBufferLow ETH__BIT(3)
813	#define ETH_IR_TxEndHigh ETH__BIT(6)
814	#define ETH_IR_TxEndLow ETH__BIT(7)
815	#define ETH_IR_RxError ETH__BIT(8)
816	#define ETH_IR_TxErrorHigh ETH__BIT(10)
817	#define ETH_IR_TxErrorLow ETH__BIT(11)
818	#define ETH_IR_RxOVR ETH__BIT(12)
819	#define ETH_IR_TxUdr ETH__BIT(13)
820	#define ETH_IR_RxBuffer_0 ETH__BIT(16)
821	#define ETH_IR_RxBuffer_1 ETH__BIT(17)
822	#define ETH_IR_RxBuffer_2 ETH__BIT(18)
823	#define ETH_IR_RxBuffer_3 ETH__BIT(19)
824	#define ETH_IR_RxBuffer_GET(v) ETH__EXT(v, 16, 4)
825	#define ETH_IR_RxError_0 ETH__BIT(20)
826	#define ETH_IR_RxError_1 ETH__BIT(21)
827	#define ETH_IR_RxError_2 ETH__BIT(22)
828	#define ETH_IR_RxError_3 ETH__BIT(23)
829	#define ETH_IR_RxError_GET(v) ETH__EXT(v, 20, 4)
830	#define ETH_IR_RxBits (ETH_IR_RxBuffer_0\|\
831	ETH_IR_RxBuffer_1\|\
832	ETH_IR_RxBuffer_2\|\
833	ETH_IR_RxBuffer_3\|\
834	ETH_IR_RxError_0\|\
835	ETH_IR_RxError_1\|\
836	ETH_IR_RxError_2\|\
837	ETH_IR_RxError_3)
838	#define ETH_IR_MIIPhySTC ETH__BIT(28)
839	#define ETH_IR_SMIdone ETH__BIT(29)
840	#define ETH_IR_EtherIntSum (1<<31)
841	#define ETH_IR_Summary (1<<31)
842	#define ETH_IR_ErrorSum 0x803d00
843	#define INTR_RX_ERROR 0x801100
844	#define INTR_TX_ERROR 0x002c00
845
846	/*
847	* Table 608: Interrupt Mask Register (IMR)
848	* 31:00 Various Mask bits for the Interrupt Cause register.
849	*/
850
851	/*
852	* Table 609: IP Differentiated Services CodePoint to Priority0 low (DSCP2P0L),
853	* 31:00 Priority0_low The LSB priority bits for DSCP[31:0] entries.
854	*/
855
856	/*
857	* Table 610: IP Differentiated Services CodePoint to Priority0 high (DSCP2P0H)
858	* 31:00 Priority0_high The LSB priority bits for DSCP[63:32] entries.
859	*/
860
861	/*
862	* Table 611: IP Differentiated Services CodePoint to Priority1 low (DSCP2P1L)
863	* 31:00 Priority1_low The MSB priority bits for DSCP[31:0] entries.
864	*/
865
866	/*
867	* Table 612: IP Differentiated Services CodePoint to Priority1 high (DSCP2P1H)
868	* 31:00 Priority1_high The MSB priority bit for DSCP[63:32] entries.
869	*/
870
871	/*
872	* Table 613: VLAN Priority Tag to Priority (VPT2P)
873	* 07:00 Priority0 The LSB priority bits for VLAN Priority[7:0]
874	* entries.
875	* 15:08 Priority1 The MSB priority bits for VLAN Priority[7:0]
876	* entries.
877	* 31:16 Reserved
878	*/
879	#endif /* _DEV_GTETHREG_H_ */

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source: rtems/c/src/lib/libbsp/powerpc/mvme5500/network/if_100MHz/GT64260ethreg.h @ 9b4422a2

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