source: rtems/c/src/lib/libbsp/powerpc/mvme5500/network/if_100MHz/GT64260eth.h @ d7196bf

4.8
Last change on this file since d7196bf was d7196bf, checked in by Joel Sherrill <joel.sherrill@…>, on 05/04/09 at 20:06:43

2009-04-20 Kate Feng <feng1@…>

1396/bsps

  • pci/pci.c : Updated it to be consistent with the original pci.c
  • written by Eric Valette. There is no change in its function.
  • irq/irq_init.c : set defaultIrq->next_handler to be 0
  • for BSP_SHARED_HANDLER_SUPPORT.
  • network/if_1GHz/if_wm.c : fixed some bugs in the 1GHz driver.
  • irq/BSP_irq.c : added supports for shared IRQ.
  • pci/pci_interface.c : Enabled PCI "Read", "Read Line", and "Read Multiple"
  • Agressive Prefetch to improve the performance of the PCI based
  • applications (e.g. 1GHz NIC).
  • irq/BSP_irq.c : Replaced the irq/irq.c, and used GT_GPP_Value
  • register to monitor the cause of the level sensitive interrupts.
  • This unique solution solves various bugs in the 1GHz network drivers
  • Fixed bugs in compute_pic_masks_from_prio()
  • Property mode set to 100644
File size: 5.8 KB
Line 
1/* GT64260eth.h
2 *
3 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
4 * All rights reserved.
5 *
6 * RTEMS/Mvme5500 port 2004  by S. Kate Feng, <feng1@bnl.gov>,
7 * under the Deaprtment of Energy contract DE-AC02-98CH10886
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 *    must display the following acknowledgement:
20 *      This product includes software developed for the NetBSD Project by
21 *      Allegro Networks, Inc., and Wasabi Systems, Inc.
22 * 4. The name of Allegro Networks, Inc. may not be used to endorse
23 *    or promote products derived from this software without specific prior
24 *    written permission.
25 * 5. The name of Wasabi Systems, Inc. may not be used to endorse
26 *    or promote products derived from this software without specific prior
27 *    written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND
30 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
31 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
33 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC.
34 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
35 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
36 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
37 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
38 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
39 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
40 * POSSIBILITY OF SUCH DAMAGE.
41 */
42
43/* Keep the ring sizes a power of two for efficiency.
44   Making the Tx ring too long decreases the effectiveness of channel
45   bonding and packet priority.
46   There are no ill effects from too-large receive rings. */
47#define TX_RING_SIZE    32
48#define GT_NEXTTX(x)    ((x + 1) % TX_RING_SIZE )
49#define TX_QUARTER_FULL TX_RING_SIZE/2
50#define TX_HALF_FULL    TX_RING_SIZE/2
51#define RX_RING_SIZE    16
52#define HASH_TABLE_SIZE 16
53#define HASH_DRAM_SIZE  HASH_TABLE_SIZE*1024  /* size of DRAM for hash table */
54#define IF_ERR_BUFSZE   16
55               
56enum GTeth_txprio {
57        GE_TXPRIO_HI=1,
58        GE_TXPRIO_LO=0,
59        GE_TXPRIO_NONE=2
60};
61enum GTeth_rxprio {
62        GE_RXPRIO_HI=3,
63        GE_RXPRIO_MEDHI=2,
64        GE_RXPRIO_MEDLO=1,
65        GE_RXPRIO_LO=0
66};
67
68struct GTeth_softc {
69  struct GTeth_desc txq_desc[TX_RING_SIZE]; /* transmit descriptor memory */
70  struct GTeth_desc rxq_desc[RX_RING_SIZE]; /* receive descriptor memory */
71  struct mbuf* txq_mbuf[TX_RING_SIZE];  /* transmit buffer memory */
72  struct mbuf* rxq_mbuf[RX_RING_SIZE];  /* receive buffer memory */
73  struct GTeth_softc *next_module;
74  volatile unsigned int if_errsts[IF_ERR_BUFSZE]; /* capture the right intr_status */
75  unsigned int if_err_ptr1;   /* ptr used in GTeth_error() */
76  unsigned int if_err_ptr2;   /* ptr used in ISR */
77  struct ifqueue txq_pendq;     /* these are ready to go to the GT */
78  unsigned int txq_pending;
79  unsigned int txq_lo;          /* next to be given to GT DMA */
80  unsigned int txq_fi;          /* next to be free */
81  unsigned int txq_to_cpu;      /* next to be returned to CPU */
82  unsigned int txq_ei_gapcount; /* counter until next EI */
83  unsigned int txq_nactive;     /* number of active descriptors */
84  unsigned int txq_nintr;       /* number of txq desc. send TX_EVENT */
85  unsigned int txq_outptr;      /* where to put next transmit packet */
86  unsigned int txq_inptr;       /* start of 1st queued tx packet */
87  unsigned int txq_free;        /* free Tx queue slots. */ 
88  unsigned txq_intrbits;        /* bits to write to EIMR */
89  unsigned txq_esdcmrbits;      /* bits to write to ESDCMR */
90  unsigned txq_epsrbits;        /* bits to test with EPSR */
91
92  caddr_t txq_ectdp;            /* offset to cur. tx desc ptr reg */
93  unsigned long txq_desc_busaddr;       /* bus addr of tx descriptors */
94  caddr_t txq_buf_busaddr;      /* bus addr of tx buffers */
95
96  struct mbuf *rxq_curpkt;      /* mbuf for current packet */
97  struct GTeth_desc *rxq_head_desc;  /* rxq head descriptor */
98  unsigned int rxq_fi;          /* next to be returned to CPU */
99  unsigned int rxq_active;      /* # of descriptors given to GT */
100  unsigned rxq_intrbits;                /* bits to write to EIMR */
101  unsigned long rxq_desc_busaddr;       /* bus addr of rx descriptors */
102
103  struct arpcom arpcom;         /* rtems if structure, contains ifnet */
104  int sc_macno;                 /* which mac? 0, 1, or 2 */
105
106  unsigned int sc_tickflags;
107  #define       GE_TICK_TX_IFSTART      0x0001
108  #define       GE_TICK_RX_RESTART      0x0002
109  unsigned int sc_flags;
110  #define       GE_ALLMULTI     0x0001
111  #define       GE_PHYSTSCHG    0x0002
112  #define       GE_RXACTIVE     0x0004
113  unsigned sc_pcr;              /* current EPCR value */
114  unsigned sc_pcxr;             /* current EPCXR value */
115  unsigned sc_intrmask;         /* current EIMR value */
116  unsigned sc_idlemask;         /* suspended EIMR bits */
117  unsigned sc_max_frame_length; /* maximum frame length */
118  unsigned rx_buf_sz;
119
120  /* Hash table related members */
121  unsigned long long *sc_hashtable;
122  unsigned int sc_hashmask;     /* 0x1ff or 0x1fff */
123
124  rtems_id      daemonTid;
125  rtems_id      daemonSync; /* synchronization with the daemon */
126  /* statistics */
127  struct {
128    volatile unsigned long       rxInterrupts;
129    volatile unsigned long       txInterrupts;
130    unsigned long       length_errors;
131    unsigned long       frame_errors;
132    unsigned long       crc_errors;
133    unsigned long       or_errors; /* overrun error */
134  } stats;
135};
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