source: rtems/c/src/lib/libbsp/powerpc/mvme5500/network/GT64260ethreg.h @ f8e0327

4.104.114.84.95
Last change on this file since f8e0327 was f8e0327, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 20, 2004 at 6:28:00 PM

2004-10-20 Joel Sherrill <joel@…>

  • README, configure.ac, GT64260/Makefile.am, include/bsp.h, irq/Makefile.am, irq/irq.c, irq/irq.h, irq/irq_init.c, network/GT64260ethreg.h, pci/pci.c, startup/bspstart.c: CVS Id string and license corrected.
  • GT64260/Makefile.in, clock/Makefile.in, console/Makefile.in, include/Makefile.am, include/Makefile.in, irq/Makefile.in, network/Makefile.in, pci/Makefile.in, start/Makefile.in, startup/Makefile.in, vectors/Makefile.in, vme/Makefile.in, wrapup/Makefile.in: Removed.
  • Property mode set to 100644
File size: 36.3 KB
Line 
1/*      $NetBSD: GT64260ethreg.h,v 1.2 2003/03/17 16:41:16 matt Exp $   */
2/*  $Id$ */
3
4/*
5 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 *    must display the following acknowledgement:
18 *      This product includes software developed for the NetBSD Project by
19 *      Allegro Networks, Inc., and Wasabi Systems, Inc.
20 * 4. The name of Allegro Networks, Inc. may not be used to endorse
21 *    or promote products derived from this software without specific prior
22 *    written permission.
23 * 5. The name of Wasabi Systems, Inc. may not be used to endorse
24 *    or promote products derived from this software without specific prior
25 *    written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND
28 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
29 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
30 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
31 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC.
32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 */
40
41#ifndef _DEV_GTETHREG_H_
42#define _DEV_GTETHREG_H_
43
44#define ETH__BIT(bit)                   (1U << (bit))
45#define ETH__LLBIT(bit)                 (1ULL << (bit))
46#define ETH__MASK(bit)                  (ETH__BIT(bit) - 1)
47#define ETH__LLMASK(bit)                (ETH__LLBIT(bit) - 1)
48#define ETH__GEN(n, off)                (0x2400+((n) << 10)+(ETH__ ## off))
49#define ETH__EXT(data, bit, len)        (((data) >> (bit)) & ETH__MASK(len))
50#define ETH__LLEXT(data, bit, len)      (((data) >> (bit)) & ETH__LLMASK(len))
51#define ETH__CLR(data, bit, len)        ((data) &= ~(ETH__MASK(len) << (bit)))
52#define ETH__INS(new, bit)              ((new) << (bit))
53#define ETH__LLINS(new, bit)            ((unsigned long long)(new) << (bit))
54
55/*
56 * Descriptors used for both receive & transmit data.  Note that the descriptor
57 * must start on a 4LW boundary.  Since the GT accesses the descriptor as
58 * two 64-bit quantities, we must present them 32bit quantities in the right
59 * order based on endianess.
60 */
61
62struct GTeth_desc {
63#if defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN /* for mvme5500 */
64        unsigned ed_lencnt;     /* Buffer size is hi 16 bits; Byte count (rx) is lo 16 */
65        unsigned ed_cmdsts;     /* command (hi16)/status (lo16) bits */
66        unsigned ed_nxtptr;     /* next descriptor (must be 4LW aligned) */
67        unsigned ed_bufptr;     /* pointer to packet buffer */
68#endif
69#if defined(BYTE_ORDER) && BYTE_ORDER == LITTLE_ENDIAN
70        unsigned ed_cmdsts;     /* command (hi16)/status (lo16) bits */
71        unsigned ed_lencnt;     /* length is hi 16 bits; count (rx) is lo 16 */
72        unsigned ed_bufptr;     /* pointer to packet buffer */
73        unsigned ed_nxtptr;     /* next descriptor (must be 4LW aligned) */
74#endif
75};
76
77/* Ethernet 0 address control (Low), Offset: 0xf200 */
78#define RxBSnoopEn      ETH__BIT(6)     /* Rx buffer snoop enable,1=enable*/
79#define TxBSnoopEn      ETH__BIT(14)    /* Tx buffer snoop enable */
80#define RxDSnoopEn      ETH__BIT(22)    /* Rx descriptor snoop enable */
81#define TxDSnoopEn      ETH__BIT(30)    /* Tx descriptor snoop enable */
82
83/* Ethernet 0 address control (High), Offset: 0xf204 */
84#define HashSnoopEn     ETH__BIT(6)     /* Hash Table snoop enable */
85
86/* <skf> */
87#define GT_CUU_Eth0_AddrCtrlLow  0xf200
88#define GT_CUU_Eth0_AddrCtrlHigh 0xf204
89
90/* Table 578: Ethernet TX Descriptor - Command/Status word
91 * All bits except F, EI, AM, O are only valid if TX_CMD_L is also set,
92 * otherwise should be 0 (tx).
93 */
94
95#define TX_STS_LC       ETH__BIT(5)     /* Late Collision */
96#define TX_STS_UR       ETH__BIT(6)     /* Underrun error */
97#define TX_STS_RL       ETH__BIT(8)     /* Retransmit Limit (excession coll) */
98#define TX_STS_COL      ETH__BIT(9)     /* Collision Occurred */
99#define TX_STS_RC(v)    ETH__GETBITS(v, 10, 4)  /* Retransmit Count */
100#define TX_STS_ES       ETH__BIT(15)    /* Error Summary (LC|UR|RL) */
101#define TX_CMD_L        ETH__BIT(16)    /* Last - End Of Packet */
102#define TX_CMD_F        ETH__BIT(17)    /* First - Start Of Packet */
103#define TX_CMD_P        ETH__BIT(18)    /* Pad Packet */
104#define TX_CMD_GC       ETH__BIT(22)    /* Generate CRC */
105#define TX_CMD_EI       ETH__BIT(23)    /* Enable Interrupt */
106#define TX_CMD_AM       ETH__BIT(30)    /* Auto Mode */
107#define TX_CMD_O        ETH__BIT(31)    /* Ownership (1=GT 0=CPU) */
108
109#define TX_CMD_FIRST    (TX_CMD_F|TX_CMD_O)
110#define TX_CMD_LAST     (TX_CMD_L|TX_CMD_GC|TX_CMD_P|TX_CMD_O)
111
112/* Table 608: Ethernet RX Descriptor - Command/Status Word
113 * All bits except F, EI, AM, O are only valid if RX_CMD_L is also set,
114 * otherwise should be ignored (rx).
115 */
116#define RX_STS_CE       ETH__BIT(0)     /* CRC Error */
117#define RX_STS_COL      ETH__BIT(1)     /* Collision sensed during reception */
118#define RX_STS_LC       ETH__BIT(5)     /* Late Collision (Reserved) */
119#define RX_STS_OR       ETH__BIT(6)     /* Overrun Error */
120#define RX_STS_MFL      ETH__BIT(7)     /* Max Frame Len Error */
121#define RX_STS_SF       ETH__BIT(8)     /* Short Frame Error (< 64 bytes) */
122#define RX_STS_FT       ETH__BIT(11)    /* Frame Type (1 = 802.3) */
123#define RX_STS_M        ETH__BIT(12)    /* Missed Frame */
124#define RX_STS_HE       ETH__BIT(13)    /* Hash Expired (manual match) */
125#define RX_STS_IGMP     ETH__BIT(14)    /* IGMP Packet */
126#define RX_STS_ES       ETH__BIT(15)    /* Error Summary (CE|COL|LC|OR|MFL|SF) */
127#define RX_CMD_L        ETH__BIT(16)    /* Last - End Of Packet */
128#define RX_CMD_F        ETH__BIT(17)    /* First - Start Of Packet */
129#define RX_CMD_EI       ETH__BIT(23)    /* Enable Interrupt */
130#define RX_CMD_AM       ETH__BIT(30)    /* Auto Mode */
131#define RX_CMD_O        ETH__BIT(31)    /* Ownership (1=GT 0=CPU) */
132
133/* Table 586: Hash Table Entry Fields
134 */
135#define HSH_V           ETH__LLBIT(0)   /* Entry is valid */
136#define HSH_S           ETH__LLBIT(1)   /* Skip this entry */
137#define HSH_RD          ETH__LLBIT(2)   /* Receive(1) / Discard (0) */
138#define HSH_R           ETH__LLBIT(2)   /* Receive(1) */
139#define HSH_PRIO_GET(v) ETH__LLEXT(v, 51, 2)
140#define HSH_PRIO_INS(v) ETH__LLINS(v, 51)
141#define HSH_ADDR_MASK   0x7fffff8LLU
142#define HSH_LIMIT       12
143
144
145#define ETH_EPAR        0x2000          /* PHY Address Register */
146#define ETH_ESMIR       0x2010          /* SMI Register */
147
148#define ETH_BASE_ETH0   0x2400          /* Ethernet0 Register Base */
149#define ETH_BASE_ETH1   0x2800          /* Ethernet1 Register Base */
150#define ETH_BASE_ETH2   0x2c00          /* Ethernet2 Register Base */
151#define ETH_SIZE        0x0400          /* Register Space */
152
153#define ETH__EBASE      0x0000          /* Base of Registers */
154#define ETH__EPCR       0x0000          /* Port Config. Register */
155#define ETH__EPCXR      0x0008          /* Port Config. Extend Reg */
156#define ETH__EPCMR      0x0010          /* Port Command Register */
157#define ETH__EPSR       0x0018          /* Port Status Register */
158#define ETH__ESPR       0x0020          /* Port Serial Parameters Reg */
159#define ETH__EHTPR      0x0028          /* Port Hash Table Pointer Reg*/
160#define ETH__EFCSAL     0x0030          /* Flow Control Src Addr Low */
161#define ETH__EFCSAH     0x0038          /* Flow Control Src Addr High */
162#define ETH__ESDCR      0x0040          /* SDMA Configuration Reg */
163#define ETH__ESDCMR     0x0048          /* SDMA Command Register */
164#define ETH__EICR       0x0050          /* Interrupt Cause Register */
165#define ETH__EIMR       0x0058          /* Interrupt Mask Register */
166#define ETH__EFRDP0     0x0080          /* First Rx Desc Pointer 0 */
167#define ETH__EFRDP1     0x0084          /* First Rx Desc Pointer 1 */
168#define ETH__EFRDP2     0x0088          /* First Rx Desc Pointer 2 */
169#define ETH__EFRDP3     0x008c          /* First Rx Desc Pointer 3 */
170#define ETH__ECRDP0     0x00a0          /* Current Rx Desc Pointer 0 */
171#define ETH__ECRDP1     0x00a4          /* Current Rx Desc Pointer 1 */
172#define ETH__ECRDP2     0x00a8          /* Current Rx Desc Pointer 2 */
173#define ETH__ECRDP3     0x00ac          /* Current Rx Desc Pointer 3 */
174#define ETH__ECTDP0     0x00e0          /* Current Tx Desc Pointer 0 */
175#define ETH__ECTDP1     0x00e4          /* Current Tx Desc Pointer 1 */
176#define ETH__EDSCP2P0L  0x0060          /* IP Differentiated Services
177                                           CodePoint to Priority0 low */
178#define ETH__EDSCP2P0H  0x0064          /* IP Differentiated Services
179                                           CodePoint to Priority0 high*/
180#define ETH__EDSCP2P1L  0x0068          /* IP Differentiated Services
181                                           CodePoint to Priority1 low */
182#define ETH__EDSCP2P1H  0x006c          /* IP Differentiated Services
183                                           CodePoint to Priority1 high*/
184#define ETH__EVPT2P     0x0068          /* VLAN Prio. Tag to Priority */
185#define ETH__EMIBCTRS   0x0100          /* MIB Counters */
186
187/* SKF : we are only concerned with the Ethernet0 for the mvme5500 board */
188#define ETH0_EBASE      0x2400          /* Base of Registers */
189#define ETH0_EPCR       0x2400          /* Port Config. Register */
190#define ETH0_EPCXR      0x2408          /* Port Config. Extend Reg */
191#define ETH0_EPCMR      0x2410          /* Port Command Register */
192#define ETH0_EPSR       0x2418          /* Port Status Register */
193#define ETH0_ESPR       0x2420          /* Port Serial Parameters Reg */
194#define ETH0_EHTPR      0x2428          /* Port Hash Table Pointer Reg*/
195#define ETH0_EFCSAL     0x2430          /* Flow Control Src Addr Low */
196#define ETH0_EFCSAH     0x2438          /* Flow Control Src Addr High */
197#define ETH0_ESDCR      0x2440          /* SDMA Configuration Reg */
198#define ETH0_ESDCMR     0x2448          /* SDMA Command Register */
199#define ETH0_EICR       0x2450          /* Interrupt Cause Register */
200#define ETH0_EIMR       0x2458          /* Interrupt Mask Register */
201#define ETH0_EFRDP0     0x2480          /* First Rx Desc Pointer 0 */
202#define ETH0_EFRDP1     0x2484          /* First Rx Desc Pointer 1 */
203#define ETH0_EFRDP2     0x2488          /* First Rx Desc Pointer 2 */
204#define ETH0_EFRDP3     0x248c          /* First Rx Desc Pointer 3 */
205#define ETH0_ECRDP0     0x24a0          /* Current Rx Desc Pointer 0 */
206#define ETH0_ECRDP1     0x24a4          /* Current Rx Desc Pointer 1 */
207#define ETH0_ECRDP2     0x24a8          /* Current Rx Desc Pointer 2 */
208#define ETH0_ECRDP3     0x24ac          /* Current Rx Desc Pointer 3 */
209#define ETH0_ECTDP0     0x24e0          /* Current Tx Desc Pointer 0 */
210#define ETH0_ECTDP1     0x24e4          /* Current Tx Desc Pointer 1 */
211#define ETH0_EDSCP2P0L  0x2460          /* IP Differentiated Services
212                                           CodePoint to Priority0 low */
213#define ETH0_EDSCP2P0H  0x2464          /* IP Differentiated Services
214                                           CodePoint to Priority0 high*/
215#define ETH0_EDSCP2P1L  0x2468          /* IP Differentiated Services
216                                           CodePoint to Priority1 low */
217#define ETH0_EDSCP2P1H  0x246c          /* IP Differentiated Services
218                                           CodePoint to Priority1 high*/
219#define ETH0_EVPT2P     0x2468          /* VLAN Prio. Tag to Priority */
220#define ETH0_EMIBCTRS   0x2500          /* MIB Counters */
221
222#define ETH_BASE(n)     ETH__GEN(n, EBASE)
223#define ETH_EPCR(n)     ETH__GEN(n, EPCR)       /* Port Config. Register */
224#define ETH_EPCXR(n)    ETH__GEN(n, EPCXR)      /* Port Config. Extend Reg */
225#define ETH_EPCMR(n)    ETH__GEN(n, EPCMR)      /* Port Command Register */
226#define ETH_EPSR(n)     ETH__GEN(n, EPSR)       /* Port Status Register */
227#define ETH_ESPR(n)     ETH__GEN(n, ESPR)       /* Port Serial Parameters Reg */
228#define ETH_EHTPR(n)    ETH__GEN(n, EHPTR)      /* Port Hash Table Pointer Reg*/
229#define ETH_EFCSAL(n)   ETH__GEN(n, EFCSAL)     /* Flow Control Src Addr Low */
230#define ETH_EFCSAH(n)   ETH__GEN(n, EFCSAH)     /* Flow Control Src Addr High */
231#define ETH_ESDCR(n)    ETH__GEN(n, ESDCR)      /* SDMA Configuration Reg */
232#define ETH_ESDCMR(n)   ETH__GEN(n, ESDCMR)     /* SDMA Command Register */
233#define ETH_EICR(n)     ETH__GEN(n, EICR)       /* Interrupt Cause Register */
234#define ETH_EIMR(n)     ETH__GEN(n, EIMR)       /* Interrupt Mask Register */
235#define ETH_EFRDP0(n)   ETH__GEN(n, EFRDP0)     /* First Rx Desc Pointer 0 */
236#define ETH_EFRDP1(n)   ETH__GEN(n, EFRDP1)     /* First Rx Desc Pointer 1 */
237#define ETH_EFRDP2(n)   ETH__GEN(n, EFRDP2)     /* First Rx Desc Pointer 2 */
238#define ETH_EFRDP3(n)   ETH__GEN(n, EFRDP3)     /* First Rx Desc Pointer 3 */
239#define ETH_ECRDP0(n)   ETH__GEN(n, ECRDP0)     /* Current Rx Desc Pointer 0 */
240#define ETH_ECRDP1(n)   ETH__GEN(n, ECRDP1)     /* Current Rx Desc Pointer 1 */
241#define ETH_ECRDP2(n)   ETH__GEN(n, ECRDP2)     /* Current Rx Desc Pointer 2 */
242#define ETH_ECRDP3(n)   ETH__GEN(n, ECRDP3)     /* Current Rx Desc Pointer 3 */
243#define ETH_ECTDP0(n)   ETH__GEN(n, ECTDP0)     /* Current Tx Desc Pointer 0 */
244#define ETH_ECTDP1(n)   ETH__GEN(n, ECTDP1)     /* Current Tx Desc Pointer 1 */
245#define ETH_EDSCP2P0L(n) ETH__GEN(n, EDSCP2P0L) /* IP Differentiated Services
246                                                   CodePoint to Priority0 low */
247#define ETH_EDSCP2P0H(n) ETH__GEN(n, EDSCP2P0H) /* IP Differentiated Services
248                                                   CodePoint to Priority0 high*/
249#define ETH_EDSCP2P1L(n) ETH__GEN(n, EDSCP2P1L) /* IP Differentiated Services
250                                                   CodePoint to Priority1 low */
251#define ETH_EDSCP2P1H(n) ETH__GEN(n, EDSCP1P1H) /* IP Differentiated Services
252                                                   CodePoint to Priority1 high*/
253#define ETH_EVPT2P(n)   ETH__GEN(n, EVPT2P)     /* VLAN Prio. Tag to Priority */
254#define ETH_EMIBCTRS(n) ETH__GEN(n, EMIBCTRS)   /* MIB Counters */
255
256#define ETH_EPAR_PhyAD_GET(v, n)        (((v) >> ((n) * 5)) & 0x1f)
257
258#define ETH_ESMIR_READ(phy, reg)        (ETH__INS(phy, 16)|\
259                                         ETH__INS(reg, 21)|\
260                                         ETH_ESMIR_ReadOpcode)
261#define ETH_ESMIR_WRITE(phy, reg, val)  (ETH__INS(phy, 16)|\
262                                         ETH__INS(reg, 21)|\
263                                         ETH__INS(val,  0)|\
264                                         ETH_ESMIR_WriteOpcode)
265#define ETH_ESMIR_Value_GET(v)          ETH__EXT(v, 0, 16)
266#define ETH_ESMIR_WriteOpcode           0
267#define ETH_ESMIR_ReadOpcode            ETH__BIT(26)
268#define ETH_ESMIR_ReadValid             ETH__BIT(27)
269#define ETH_ESMIR_Busy                  ETH__BIT(28)
270
271/*
272 * Table 597: Port Configuration Register (PCR)
273 * 00:00 PM                     Promiscuous mode
274 *                              0: Normal mode (Frames are only received if the
275 *                                 destination address is found in the hash
276 *                                 table)
277 *                              1: Promiscuous mode (Frames are received
278 *                                 regardless of their destination address.
279 *                                 Errored frames are discarded unless the Port
280 *                                 Configuration register's PBF bit is set)
281 * 01:01 RBM                    Reject Broadcast Mode
282 *                              0: Receive broadcast address
283 *                              1: Reject frames with broadcast address
284 *                              Overridden by the promiscuous mode.
285 * 02:02 PBF                    Pass Bad Frames
286 *                              (0: Normal mode, 1: Pass bad Frames)
287 *                              The Ethernet receiver passes to the CPU errored
288 *                              frames (like fragments and collided packets)
289 *                              that are normally rejected.
290 *                              NOTE: Frames are only passed if they
291 *                                    successfully pass address filtering.
292 * 06:03 Reserved
293 * 07:07 EN                     Enable (0: Disabled, 1: Enable)
294 *                              When enabled, the ethernet port is ready to
295 *                              transmit/receive.
296 * 09:08 LPBK                   Loop Back Mode
297 *                              00: Normal mode
298 *                              01: Internal loop back mode (TX data is looped
299 *                                  back to the RX lines. No transition is seen
300 *                                  on the interface pins)
301 *                              10: External loop back mode (TX data is looped
302 *                                  back to the RX lines and also transmitted
303 *                                  out to the MII interface pins)
304 *                              11: Reserved
305 * 10:10 FC                     Force Collision
306 *                              0: Normal mode.
307 *                              1: Force Collision on any TX frame.
308 *                                 For RXM test (in Loopback mode).
309 * 11:11 Reserved.
310 * 12:12 HS                     Hash Size
311 *                              0: 8K address filtering
312 *                                 (256KB of memory space required).
313 *                              1: 512 address filtering
314 *                                 ( 16KB of memory space required).
315 * 13:13 HM                     Hash Mode (0: Hash Func. 0; 1: Hash Func. 1)
316 * 14:14 HDM                    Hash Default Mode
317 *                              0: Discard addresses not found in address table
318 *                              1: Pass addresses not found in address table
319 * 15:15 HD                     Duplex Mode (0: Half Duplex, 1: Full Duplex)
320 *                              NOTE: Valid only when auto-negotiation for
321 *                                    duplex mode is disabled.
322 * 30:16 Reserved
323 * 31:31 ACCS                   Accelerate Slot Time
324 *                              (0: Normal mode, 1: Reserved)
325 */
326#define ETH_EPCR_PM             ETH__BIT(0)
327#define ETH_EPCR_RBM            ETH__BIT(1)
328#define ETH_EPCR_PBF            ETH__BIT(2)
329#define ETH_EPCR_EN             ETH__BIT(7)
330#define ETH_EPCR_LPBK_GET(v)    ETH__BIT(v, 8, 2)
331#define ETH_EPCR_LPBK_Normal    0
332#define ETH_EPCR_LPBK_Internal  1
333#define ETH_EPCR_LPBK_External  2
334#define ETH_EPCR_FC             ETH__BIT(10)
335
336#define ETH_EPCR_HS             ETH__BIT(12)
337#define ETH_EPCR_HS_8K          0
338#define ETH_EPCR_HS_512         ETH_EPCR_HS
339
340#define ETH_EPCR_HM             ETH__BIT(13)
341#define ETH_EPCR_HM_0           0
342#define ETH_EPCR_HM_1           ETH_EPCR_HM
343
344#define ETH_EPCR_HDM            ETH__BIT(14)
345#define ETH_EPCR_HDM_Discard    0
346#define ETH_EPCR_HDM_Pass       ETH_EPCR_HDM
347
348#define ETH_EPCR_HD_Half        0
349#define ETH_EPCR_HD_Full        ETH_EPCR_HD_Full
350
351#define ETH_EPCR_ACCS           ETH__BIT(31)
352
353
354
355/*
356 * Table 598: Port Configuration Extend Register (PCXR)
357 * 00:00 IGMP                   IGMP Packets Capture Enable
358 *                              0: IGMP packets are treated as normal Multicast
359 *                                 packets.
360 *                              1: IGMP packets on IPv4/Ipv6 over Ethernet/802.3
361 *                                 are trapped and sent to high priority RX
362 *                                 queue.
363 * 01:01 SPAN                   Spanning Tree Packets Capture Enable
364 *                              0: BPDU (Bridge Protocol Data Unit) packets are
365 *                                 treated as normal Multicast packets.
366 *                              1: BPDU packets are trapped and sent to high
367 *                                 priority RX queue.
368 * 02:02 PAR                    Partition Enable (0: Normal, 1: Partition)
369 *                              When more than 61 collisions occur while
370 *                              transmitting, the port enters Partition mode.
371 *                              It waits for the first good packet from the
372 *                              wire and then goes back to Normal mode.  Under
373 *                              Partition mode it continues transmitting, but
374 *                              it does not receive.
375 * 05:03 PRIOtx                 Priority weight in the round-robin between high
376 *                              and low priority TX queues.
377 *                              000: 1 pkt from HIGH, 1 pkt from LOW.
378 *                              001: 2 pkt from HIGH, 1 pkt from LOW.
379 *                              010: 4 pkt from HIGH, 1 pkt from LOW.
380 *                              011: 6 pkt from HIGH, 1 pkt from LOW.
381 *                              100: 8 pkt from HIGH, 1 pkt from LOW.
382 *                              101: 10 pkt from HIGH, 1 pkt from LOW.
383 *                              110: 12 pkt from HIGH, 1 pkt from LOW.
384 *                              111: All pkt from HIGH, 0 pkt from LOW. LOW is
385 *                                   served only if HIGH is empty.
386 *                              NOTE: If the HIGH queue is emptied before
387 *                                    finishing the count, the count is reset
388 *                                    until the next first HIGH comes in.
389 * 07:06 PRIOrx                 Default Priority for Packets Received on this
390 *                              Port (00: Lowest priority, 11: Highest priority)
391 * 08:08 PRIOrx_Override        Override Priority for Packets Received on this
392 *                              Port (0: Do not override, 1: Override with
393 *                              <PRIOrx> field)
394 * 09:09 DPLXen                 Enable Auto-negotiation for Duplex Mode
395 *                              (0: Enable, 1: Disable)
396 * 11:10 FCTLen                 Enable Auto-negotiation for 802.3x Flow-control
397 *                              0: Enable; When enabled, 1 is written (through
398 *                                 SMI access) to the PHY's register 4 bit 10
399 *                                 to advertise flow-control capability.
400 *                              1: Disable; Only enables flow control after the
401 *                                 PHY address is set by the CPU. When changing
402 *                                 the PHY address the flow control
403 *                                 auto-negotiation must be disabled.
404 * 11:11 FLP                    Force Link Pass
405 *                              (0: Force Link Pass, 1: Do NOT Force Link pass)
406 * 12:12 FCTL                   802.3x Flow-Control Mode (0: Enable, 1: Disable)
407 *                              NOTE: Only valid when auto negotiation for flow
408 *                                    control is disabled.
409 * 13:13 Reserved
410 * 15:14 MFL                    Max Frame Length
411 *                              Maximum packet allowed for reception (including
412 *                              CRC):   00: 1518 bytes,   01: 1536 bytes,
413 *                                      10: 2048 bytes,   11:  64K bytes
414 * 16:16 MIBclrMode             MIB Counters Clear Mode (0: Clear, 1: No effect)
415 * 17:17 MIBctrMode             Reserved. (MBZ)
416 * 18:18 Speed                  Port Speed (0: 10Mbit/Sec, 1: 100Mbit/Sec)
417 *                              NOTE: Only valid if SpeedEn bit is set.
418 * 19:19 SpeedEn                Enable Auto-negotiation for Speed
419 *                              (0: Enable, 1: Disable)
420 * 20:20 RMIIen                 RMII enable
421 *                              0: Port functions as MII port
422 *                              1: Port functions as RMII port
423 * 21:21 DSCPen                 DSCP enable
424 *                              0: IP DSCP field decoding is disabled.
425 *                              1: IP DSCP field decoding is enabled.
426 * 31:22 Reserved
427 */
428#define ETH_EPCXR_IGMP                  ETH__BIT(0)
429#define ETH_EPCXR_SPAN                  ETH__BIT(1)
430#define ETH_EPCXR_PAR                   ETH__BIT(2)
431#define ETH_EPCXR_PRIOtx_GET(v)         ETH__EXT(v, 3, 3)
432#define ETH_EPCXR_PRIOrx_GET(v)         ETH__EXT(v, 3, 3)
433#define ETH_EPCXR_PRIOrx_Override       ETH__BIT(8)
434#define ETH_EPCXR_DLPXen                ETH__BIT(9)
435#define ETH_EPCXR_FCTLen                ETH__BIT(10)
436#define ETH_EPCXR_FLP                   ETH__BIT(11)
437#define ETH_EPCXR_FCTL                  ETH__BIT(12)
438#define ETH_EPCXR_MFL_GET(v)            ETH__EXT(v, 14, 2)
439#define ETH_EPCXR_MFL_1518              0
440#define ETH_EPCXR_MFL_1536              1
441#define ETH_EPCXR_MFL_2048              2
442#define ETH_EPCXR_MFL_64K               3
443#define ETH_EPCXR_MIBclrMode            ETH__BIT(16)
444#define ETH_EPCXR_MIBctrMode            ETH__BIT(17)
445#define ETH_EPCXR_Speed                 ETH__BIT(18)
446#define ETH_EPCXR_SpeedEn               ETH__BIT(19)
447#define ETH_EPCXR_RMIIEn                ETH__BIT(20)
448#define ETH_EPCXR_DSCPEn                ETH__BIT(21)
449
450
451
452/*
453 * Table 599: Port Command Register (PCMR)
454 * 14:00 Reserved
455 * 15:15 FJ                     Force Jam / Flow Control
456 *                              When in half-duplex mode, the CPU uses this bit
457 *                              to force collisions on the Ethernet segment.
458 *                              When the CPU recognizes that it is going to run
459 *                              out of receive buffers, it can force the
460 *                              transmitter to send jam frames, forcing
461 *                              collisions on the wire.  To allow transmission
462 *                              on the Ethernet segment, the CPU must clear the
463 *                              FJ bit when more resources are available.  When
464 *                              in full-duplex and flow-control is enabled, this
465 *                              bit causes the port's transmitter to send
466 *                              flow-control PAUSE packets. The CPU must reset
467 *                              this bit when more resources are available.
468 * 31:16 Reserved
469 */
470
471#define ETH_EPCMR_FJ            ETH__BIT(15)
472
473
474/*
475 * Table 600: Port Status Register (PSR) -- Read Only
476 * 00:00 Speed                  Indicates Port Speed (0: 10Mbs, 1: 100Mbs)
477 * 01:01 Duplex                 Indicates Port Duplex Mode (0: Half, 1: Full)
478 * 02:02 Fctl                   Indicates Flow-control Mode
479 *                              (0: enabled, 1: disabled)
480 * 03:03 Link                   Indicates Link Status (0: down, 1: up)
481 * 04:04 Pause                  Indicates that the port is in flow-control
482 *                              disabled state.  This bit is set when an IEEE
483 *                              802.3x flow-control PAUSE (XOFF) packet is
484 *                              received (assuming that flow-control is
485 *                              enabled and the port is in full-duplex mode).
486 *                              Reset when XON is received, or when the XOFF
487 *                              timer has expired.
488 * 05:05 TxLow                  Tx Low Priority Status
489 *                              Indicates the status of the low priority
490 *                              transmit queue: (0: Stopped, 1: Running)
491 * 06:06 TxHigh                 Tx High Priority Status
492 *                              Indicates the status of the high priority
493 *                              transmit queue: (0: Stopped, 1: Running)
494 * 07:07 TXinProg               TX in Progress
495 *                              Indicates that the port's transmitter is in an
496 *                              active transmission state.
497 * 31:08 Reserved
498 */
499#define ETH_EPSR_Speed          ETH__BIT(0)
500#define ETH_EPSR_Duplex         ETH__BIT(1)
501#define ETH_EPSR_Fctl           ETH__BIT(2)
502#define ETH_EPSR_Link           ETH__BIT(3)
503#define ETH_EPSR_Pause          ETH__BIT(4)
504#define ETH_EPSR_TxLow          ETH__BIT(5)
505#define ETH_EPSR_TxHigh         ETH__BIT(6)
506#define ETH_EPSR_TXinProg       ETH__BIT(7)
507
508
509/*
510 * Table 601: Serial Parameters Register (SPR)
511 * 01:00 JAM_LENGTH             Two bits to determine the JAM Length
512 *                              (in Backpressure) as follows:
513 *                                      00 = 12K bit-times
514 *                                      01 = 24K bit-times
515 *                                      10 = 32K bit-times
516 *                                      11 = 48K bit-times
517 * 06:02 JAM_IPG                Five bits to determine the JAM IPG.
518 *                              The step is four bit-times. The value may vary
519 *                              between 4 bit time to 124.
520 * 11:07 IPG_JAM_TO_DATA        Five bits to determine the IPG JAM to DATA.
521 *                              The step is four bit-times. The value may vary
522 *                              between 4 bit time to 124.
523 * 16:12 IPG_DATA               Inter-Packet Gap (IPG)
524 *                              The step is four bit-times. The value may vary
525 *                              between 12 bit time to 124.
526 *                              NOTE: These bits may be changed only when the
527 *                                    Ethernet ports is disabled.
528 * 21:17 Data_Blind             Data Blinder
529 *                              The number of nibbles from the beginning of the
530 *                              IPG, in which the IPG counter is restarted when
531 *                              detecting a carrier activity.  Following this
532 *                              value, the port enters the Data Blinder zone and
533 *                              does not reset the IPG counter. This ensures
534 *                              fair access to the medium.
535 *                              The default is 10 hex (64 bit times - 2/3 of the
536 *                              default IPG).  The step is 4 bit-times. Valid
537 *                              range is 3 to 1F hex nibbles.
538 *                              NOTE: These bits may be only changed when the
539 *                                    Ethernet port is disabled.
540 * 22:22 Limit4                 The number of consecutive packet collisions that
541 *                              occur before the collision counter is reset.
542 *                                0: The port resets its collision counter after
543 *                                   16 consecutive retransmit trials and
544 *                                   restarts the Backoff algorithm.
545 *                                1: The port resets its collision counter and
546 *                                   restarts the Backoff algorithm after 4
547 *                                   consecutive transmit trials.
548 * 31:23 Reserved
549 */
550#define ETH_ESPR_JAM_LENGTH_GET(v)      ETH__EXT(v, 0, 2)
551#define ETH_ESPR_JAM_IPG_GET(v)         ETH__EXT(v, 2, 5)
552#define ETH_ESPR_IPG_JAM_TO_DATA_GET(v) ETH__EXT(v, 7, 5)
553#define ETH_ESPR_IPG_DATA_GET(v)        ETH__EXT(v, 12, 5)
554#define ETH_ESPR_Data_Bilnd_GET(v)      ETH__EXT(v, 17, 5)
555#define ETH_ESPR_Limit4(v)              ETH__BIT(22)
556
557/*
558 * Table 602: Hash Table Pointer Register (HTPR)
559 * 31:00 HTP                    32-bit pointer to the address table.
560 *                              Bits [2:0] must be set to zero.
561 */
562
563/*
564 * Table 603: Flow Control Source Address Low (FCSAL)
565 * 15:0 SA[15:0]                Source Address
566 *                              The least significant bits of the source
567 *                              address for the port.  This address is used for
568 *                              Flow Control.
569 * 31:16 Reserved
570 */
571
572/*
573 * Table 604: Flow Control Source Address High (FCSAH)
574 * 31:0 SA[47:16]               Source Address
575 *                              The most significant bits of the source address
576 *                              for the port.  This address is used for Flow
577 *                              Control.
578 */
579
580
581/*
582 * Table 605: SDMA Configuration Register (SDCR)
583 * 01:00 Reserved
584 * 05:02 RC                     Retransmit Count
585 *                              Sets the maximum number of retransmits per
586 *                              packet.  After executing retransmit for RC
587 *                              times, the TX SDMA closes the descriptor with a
588 *                              Retransmit Limit error indication and processes
589 *                              the next packet.  When RC is set to 0, the
590 *                              number of retransmits is unlimited. In this
591 *                              case, the retransmit process is only terminated
592 *                              if CPU issues an Abort command.
593 * 06:06 BLMR                   Big/Little Endian Receive Mode
594 *                              The DMA supports Big or Little Endian
595 *                              configurations on a per channel basis. The BLMR
596 *                              bit only affects data transfer to memory.
597 *                                      0: Big Endian
598 *                                      1: Little Endian
599 * 07:07 BLMT                   Big/Little Endian Transmit Mode
600 *                              The DMA supports Big or Little Endian
601 *                              configurations on a per channel basis. The BLMT
602 *                              bit only affects data transfer from memory.
603 *                                      0: Big Endian
604 *                                      1: Little Endian
605 * 08:08 POVR                   PCI Override
606 *                              When set, causes the SDMA to direct all its
607 *                              accesses in PCI_0 direction and overrides
608 *                              normal address decoding process.
609 * 09:09 RIFB                   Receive Interrupt on Frame Boundaries
610 *                              When set, the SDMA Rx generates interrupts only
611 *                              on frame boundaries (i.e. after writing the
612 *                              frame status to the descriptor).
613 * 11:10 Reserved
614 * 13:12 BSZ                    Burst Size
615 *                              Sets the maximum burst size for SDMA
616 *                              transactions:
617 *                                      00: Burst is limited to 1 64bit words.
618 *                                      01: Burst is limited to 2 64bit words.
619 *                                      10: Burst is limited to 4 64bit words.
620 *                                      11: Burst is limited to 8 64bit words.
621 * 31:14 Reserved
622 */
623#define ETH_ESDCR_RC_GET(v)             ETH__EXT(v, 2, 4)
624#define ETH_ESDCR_BLMR                  ETH__BIT(6)
625#define ETH_ESDCR_BLMT                  ETH__BIT(7)
626#define ETH_ESDCR_POVR                  ETH__BIT(8)
627#define ETH_ESDCR_RIFB                  ETH__BIT(9)
628#define ETH_ESDCR_BSZ_GET(v)            ETH__EXT(v, 12, 2)
629#define ETH_ESDCR_BSZ_SET(v, n)         (ETH__CLR(v, 12, 2),\
630                                         (v) |= ETH__INS(n, 12))
631#define ETH_ESDCR_BSZ_1                 0
632#define ETH_ESDCR_BSZ_2                 1
633#define ETH_ESDCR_BSZ_4                 2
634#define ETH_ESDCR_BSZ_8                 3
635
636#define ETH_ESDCR_BSZ_Strings           { "1 64-bit word", "2 64-bit words", \
637                                          "4 64-bit words", "8 64-bit words" }
638
639/*
640 * Table 606: SDMA Command Register (SDCMR)
641 * 06:00 Reserved
642 * 07:07 ERD                    Enable RX DMA.
643 *                              Set to 1 by the CPU to cause the SDMA to start
644 *                              a receive process.  Cleared when the CPU issues
645 *                              an Abort Receive command.
646 * 14:08 Reserved
647 * 15:15 AR                     Abort Receive
648 *                              Set to 1 by the CPU to abort a receive SDMA
649 *                              operation.  When the AR bit is set, the SDMA
650 *                              aborts its current operation and moves to IDLE.
651 *                              No descriptor is closed.  The AR bit is cleared
652 *                              upon entering IDLE.  After setting the AR bit,
653 *                              the CPU must poll the bit to verify that the
654 *                              abort sequence is completed.
655 * 16:16 STDH                   Stop TX High
656 *                              Set to 1 by the CPU to stop the transmission
657 *                              process from the high priority queue at the end
658 *                              of the current frame. An interrupt is generated
659 *                              when the stop command has been executed.
660 *                                Writing 1 to STDH resets TXDH bit.
661 *                                Writing 0 to this bit has no effect.
662 * 17:17 STDL                   Stop TX Low
663 *                              Set to 1 by the CPU to stop the transmission
664 *                              process from the low priority queue at the end
665 *                              of the current frame. An interrupt is generated
666 *                              when the stop command has been executed.
667 *                                Writing 1 to STDL resets TXDL bit.
668 *                                Writing 0 to this bit has no effect.
669 * 22:18 Reserved
670 * 23:23 TXDH                   Start Tx High
671 *                              Set to 1 by the CPU to cause the SDMA to fetch
672 *                              the first descriptor and start a transmit
673 *                              process from the high priority Tx queue.
674 *                                Writing 1 to TXDH resets STDH bit.
675 *                                Writing 0 to this bit has no effect.
676 * 24:24 TXDL                   Start Tx Low
677 *                              Set to 1 by the CPU to cause the SDMA to fetch
678 *                              the first descriptor and start a transmit
679 *                              process from the low priority Tx queue.
680 *                                Writing 1 to TXDL resets STDL bit.
681 *                                Writing 0 to this bit has no effect.
682 * 30:25 Reserved
683 * 31:31 AT                     Abort Transmit
684 *                              Set to 1 by the CPU to abort a transmit DMA
685 *                              operation.  When the AT bit is set, the SDMA
686 *                              aborts its current operation and moves to IDLE.
687 *                              No descriptor is closed.  Cleared upon entering
688 *                              IDLE.  After setting AT bit, the CPU must poll
689 *                              it in order to verify that the abort sequence
690 *                              is completed.
691 */
692#define ETH_ESDCMR_ERD                  ETH__BIT(7)
693#define ETH_ESDCMR_AR                   ETH__BIT(15)
694#define ETH_ESDCMR_STDH                 ETH__BIT(16)
695#define ETH_ESDCMR_STDL                 ETH__BIT(17)
696#define ETH_ESDCMR_TXDH                 ETH__BIT(23)
697#define ETH_ESDCMR_TXDL                 ETH__BIT(24)
698#define ETH_ESDCMR_AT                   ETH__BIT(31)
699
700/*
701 * Table 607: Interrupt Cause Register (ICR)
702 * 00:00 RxBuffer               Rx Buffer Return
703 *                              Indicates an Rx buffer returned to CPU ownership
704 *                              or that the port finished reception of a Rx
705 *                              frame in either priority queues.
706 *                              NOTE: In order to get a Rx Buffer return per
707 *                                    priority queue, use bit 19:16. This bit is
708 *                                    set upon closing any Rx descriptor which
709 *                                    has its EI bit set. To limit the
710 *                                    interrupts to frame (rather than buffer)
711 *                                    boundaries, the user must set SDMA
712 *                                    Configuration register's RIFB bit. When
713 *                                    the RIFB bit is set, an interrupt
714 *                                    generates only upon closing the first
715 *                                    descriptor of a received packet, if this
716 *                                    descriptor has it EI bit set.
717 * 01:01 Reserved
718 * 02:02 TxBufferHigh           Tx Buffer for High priority Queue
719 *                              Indicates a Tx buffer returned to CPU ownership
720 *                              or that the port finished transmission of a Tx
721 *                              frame.
722 *                              NOTE: This bit is set upon closing any Tx
723 *                                    descriptor which has its EI bit set. To
724 *                                    limit the interrupts to frame (rather than
725 *                                    buffer) boundaries, the user must set EI
726 *                                    only in the last descriptor.
727 * 03:03 TxBufferLow            Tx Buffer for Low Priority Queue
728 *                              Indicates a Tx buffer returned to CPU ownership
729 *                              or that the port finished transmission of a Tx
730 *                              frame.
731 *                              NOTE: This bit is set upon closing any Tx
732 *                                    descriptor which has its EI bit set. To
733 *                                    limit the interrupts to frame (rather than
734 *                                    buffer) boundaries, the user must set EI
735 *                                    only in the last descriptor.
736 * 05:04 Reserved
737 * 06:06 TxEndHigh              Tx End for High Priority Queue
738 *                              Indicates that the Tx DMA stopped processing the
739 *                              high priority queue after stop command, or that
740 *                              it reached the end of the high priority
741 *                              descriptor chain.
742 * 07:07 TxEndLow               Tx End for Low Priority Queue
743 *                              Indicates that the Tx DMA stopped processing the
744 *                              low priority queue after stop command, or that
745 *                              it reached the end of the low priority
746 *                              descriptor chain.
747 * 08:08 RxError                Rx Resource Error
748 *                              Indicates a Rx resource error event in one of
749 *                              the priority queues.
750 *                              NOTE: To get a Rx Resource Error Indication per
751 *                                    priority queue, use bit 23:20.
752 * 09:09 Reserved
753 * 10:10 TxErrorHigh            Tx Resource Error for High Priority Queue
754 *                              Indicates a Tx resource error event during
755 *                              packet transmission from the high priority queue
756 * 11:11 TxErrorLow             Tx Resource Error for Low Priority Queue
757 *                              Indicates a Tx resource error event during
758 *                              packet transmission from the low priority queue
759 * 12:12 RxOVR                  Rx Overrun
760 *                              Indicates an overrun event that occurred during
761 *                              reception of a packet.
762 * 13:13 TxUdr                  Tx Underrun
763 *                              Indicates an underrun event that occurred during
764 *                              transmission of packet from either queue.
765 * 15:14 Reserved
766 * 16:16 RxBuffer-Queue[0]      Rx Buffer Return in Priority Queue[0]
767 *                              Indicates a Rx buffer returned to CPU ownership
768 *                              or that the port completed reception of a Rx
769 *                              frame in a receive priority queue[0]
770 * 17:17 RxBuffer-Queue[1]      Rx Buffer Return in Priority Queue[1]
771 *                              Indicates a Rx buffer returned to CPU ownership
772 *                              or that the port completed reception of a Rx
773 *                              frame in a receive priority queue[1].
774 * 18:18 RxBuffer-Queue[2]      Rx Buffer Return in Priority Queue[2]
775 *                              Indicates a Rx buffer returned to CPU ownership
776 *                              or that the port completed reception of a Rx
777 *                              frame in a receive priority queue[2].
778 * 19:19 RxBuffer-Queue[3]      Rx Buffer Return in Priority Queue[3]
779 *                              Indicates a Rx buffer returned to CPU ownership
780 *                              or that the port completed reception of a Rx
781 *                              frame in a receive priority queue[3].
782 * 20:20 RxError-Queue[0]       Rx Resource Error in Priority Queue[0]
783 *                              Indicates a Rx resource error event in receive
784 *                              priority queue[0].
785 * 21:21 RxError-Queue[1]       Rx Resource Error in Priority Queue[1]
786 *                              Indicates a Rx resource error event in receive
787 *                              priority queue[1].
788 * 22:22 RxError-Queue[2]       Rx Resource Error in Priority Queue[2]
789 *                              Indicates a Rx resource error event in receive
790 *                              priority queue[2].
791 * 23:23 RxError-Queue[3]       Rx Resource Error in Priority Queue[3]
792 *                              Indicates a Rx resource error event in receive
793 *                              priority queue[3].
794 * 27:24 Reserved
795 * 28:29 MIIPhySTC              MII PHY Status Change
796 *                              Indicates a status change reported by the PHY
797 *                              connected to this port.  Set when the MII
798 *                              management interface block identifies a change
799 *                              in PHY's register 1.
800 * 29:29 SMIdone                SMI Command Done
801 *                              Indicates that the SMI completed a MII
802 *                              management command (either read or write) that
803 *                              was initiated by the CPU writing to the SMI
804 *                              register.
805 * 30:30 Reserved
806 * 31:31 EtherIntSum            Ethernet Interrupt Summary
807 *                              This bit is a logical OR of the (unmasked) bits
808 *                              [30:04] in the Interrupt Cause register.
809 */
810
811#define ETH_IR_RxBuffer         ETH__BIT(0)
812#define ETH_IR_TxBufferHigh     ETH__BIT(2)
813#define ETH_IR_TxBufferLow      ETH__BIT(3)
814#define ETH_IR_TxEndHigh        ETH__BIT(6)
815#define ETH_IR_TxEndLow         ETH__BIT(7)
816#define ETH_IR_RxError          ETH__BIT(8)
817#define ETH_IR_TxErrorHigh      ETH__BIT(10)
818#define ETH_IR_TxErrorLow       ETH__BIT(11)
819#define ETH_IR_RxOVR            ETH__BIT(12)
820#define ETH_IR_TxUdr            ETH__BIT(13)
821#define ETH_IR_RxBuffer_0       ETH__BIT(16)
822#define ETH_IR_RxBuffer_1       ETH__BIT(17)
823#define ETH_IR_RxBuffer_2       ETH__BIT(18)
824#define ETH_IR_RxBuffer_3       ETH__BIT(19)
825#define ETH_IR_RxBuffer_GET(v)  ETH__EXT(v, 16, 4)
826#define ETH_IR_RxError_0        ETH__BIT(20)
827#define ETH_IR_RxError_1        ETH__BIT(21)
828#define ETH_IR_RxError_2        ETH__BIT(22)
829#define ETH_IR_RxError_3        ETH__BIT(23)
830#define ETH_IR_RxError_GET(v)   ETH__EXT(v, 20, 4)
831#define ETH_IR_RxBits           (ETH_IR_RxBuffer_0|\
832                                 ETH_IR_RxBuffer_1|\
833                                 ETH_IR_RxBuffer_2|\
834                                 ETH_IR_RxBuffer_3|\
835                                 ETH_IR_RxError_0|\
836                                 ETH_IR_RxError_1|\
837                                 ETH_IR_RxError_2|\
838                                 ETH_IR_RxError_3)
839#define ETH_IR_MIIPhySTC         ETH__BIT(28)
840#define ETH_IR_SMIdone           ETH__BIT(29)
841#define ETH_IR_EtherIntSum       (1<<31)
842#define ETH_IR_Summary           (1<<31)
843#define ETH_IR_ErrorSum          0x803d00
844#define INTR_RX_ERROR            0x801100
845#define INTR_TX_ERROR            0x002c00
846
847/*
848 * Table 608: Interrupt Mask Register (IMR)
849 * 31:00 Various                Mask bits for the Interrupt Cause register.
850 */
851
852/*
853 * Table 609: IP Differentiated Services CodePoint to Priority0 low (DSCP2P0L),
854 * 31:00 Priority0_low          The LSB priority bits for DSCP[31:0] entries.
855 */
856
857/*
858 * Table 610: IP Differentiated Services CodePoint to Priority0 high (DSCP2P0H)
859 * 31:00 Priority0_high         The LSB priority bits for DSCP[63:32] entries.
860 */
861
862/*
863 * Table 611: IP Differentiated Services CodePoint to Priority1 low (DSCP2P1L)
864 * 31:00 Priority1_low          The MSB priority bits for DSCP[31:0] entries.
865 */
866
867/*
868 * Table 612: IP Differentiated Services CodePoint to Priority1 high (DSCP2P1H)
869 * 31:00 Priority1_high         The MSB priority bit for DSCP[63:32] entries.
870 */
871
872/*
873 * Table 613: VLAN Priority Tag to Priority (VPT2P)
874 * 07:00 Priority0              The LSB priority bits for VLAN Priority[7:0]
875 *                              entries.
876 * 15:08 Priority1              The MSB priority bits for VLAN Priority[7:0]
877 *                              entries.
878 * 31:16 Reserved
879 */
880#endif /* _DEV_GTETHREG_H_ */
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