| 1 | /* $NetBSD: GT64260ethreg.h,v 1.2 2003/03/17 16:41:16 matt Exp $ */ |
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| 2 | /* $Id$ */ |
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| 3 | |
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| 4 | /* |
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| 5 | * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. |
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| 6 | * All rights reserved. |
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| 7 | * |
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| 8 | * Redistribution and use in source and binary forms, with or without |
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| 9 | * modification, are permitted provided that the following conditions |
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| 10 | * are met: |
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| 11 | * 1. Redistributions of source code must retain the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer. |
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| 13 | * 2. Redistributions in binary form must reproduce the above copyright |
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| 14 | * notice, this list of conditions and the following disclaimer in the |
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| 15 | * documentation and/or other materials provided with the distribution. |
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| 16 | * 3. All advertising materials mentioning features or use of this software |
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| 17 | * must display the following acknowledgement: |
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| 18 | * This product includes software developed for the NetBSD Project by |
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| 19 | * Allegro Networks, Inc., and Wasabi Systems, Inc. |
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| 20 | * 4. The name of Allegro Networks, Inc. may not be used to endorse |
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| 21 | * or promote products derived from this software without specific prior |
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| 22 | * written permission. |
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| 23 | * 5. The name of Wasabi Systems, Inc. may not be used to endorse |
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| 24 | * or promote products derived from this software without specific prior |
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| 25 | * written permission. |
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| 26 | * |
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| 27 | * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND |
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| 28 | * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, |
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| 29 | * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY |
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| 30 | * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 31 | * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. |
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| 32 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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| 33 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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| 34 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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| 35 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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| 36 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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| 37 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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| 38 | * POSSIBILITY OF SUCH DAMAGE. |
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| 39 | */ |
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| 40 | |
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| 41 | #ifndef _DEV_GTETHREG_H_ |
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| 42 | #define _DEV_GTETHREG_H_ |
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| 43 | |
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| 44 | #define ETH__BIT(bit) (1U << (bit)) |
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| 45 | #define ETH__LLBIT(bit) (1ULL << (bit)) |
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| 46 | #define ETH__MASK(bit) (ETH__BIT(bit) - 1) |
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| 47 | #define ETH__LLMASK(bit) (ETH__LLBIT(bit) - 1) |
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| 48 | #define ETH__GEN(n, off) (0x2400+((n) << 10)+(ETH__ ## off)) |
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| 49 | #define ETH__EXT(data, bit, len) (((data) >> (bit)) & ETH__MASK(len)) |
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| 50 | #define ETH__LLEXT(data, bit, len) (((data) >> (bit)) & ETH__LLMASK(len)) |
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| 51 | #define ETH__CLR(data, bit, len) ((data) &= ~(ETH__MASK(len) << (bit))) |
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| 52 | #define ETH__INS(new, bit) ((new) << (bit)) |
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| 53 | #define ETH__LLINS(new, bit) ((unsigned long long)(new) << (bit)) |
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| 54 | |
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| 55 | /* |
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| 56 | * Descriptors used for both receive & transmit data. Note that the descriptor |
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| 57 | * must start on a 4LW boundary. Since the GT accesses the descriptor as |
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| 58 | * two 64-bit quantities, we must present them 32bit quantities in the right |
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| 59 | * order based on endianess. |
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| 60 | */ |
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| 61 | |
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| 62 | struct GTeth_desc { |
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| 63 | #if defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN /* for mvme5500 */ |
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| 64 | unsigned ed_lencnt; /* Buffer size is hi 16 bits; Byte count (rx) is lo 16 */ |
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| 65 | unsigned ed_cmdsts; /* command (hi16)/status (lo16) bits */ |
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| 66 | unsigned ed_nxtptr; /* next descriptor (must be 4LW aligned) */ |
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| 67 | unsigned ed_bufptr; /* pointer to packet buffer */ |
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| 68 | #endif |
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| 69 | #if defined(BYTE_ORDER) && BYTE_ORDER == LITTLE_ENDIAN |
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| 70 | unsigned ed_cmdsts; /* command (hi16)/status (lo16) bits */ |
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| 71 | unsigned ed_lencnt; /* length is hi 16 bits; count (rx) is lo 16 */ |
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| 72 | unsigned ed_bufptr; /* pointer to packet buffer */ |
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| 73 | unsigned ed_nxtptr; /* next descriptor (must be 4LW aligned) */ |
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| 74 | #endif |
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| 75 | }; |
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| 76 | |
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| 77 | /* Ethernet 0 address control (Low), Offset: 0xf200 */ |
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| 78 | #define RxBSnoopEn ETH__BIT(6) /* Rx buffer snoop enable,1=enable*/ |
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| 79 | #define TxBSnoopEn ETH__BIT(14) /* Tx buffer snoop enable */ |
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| 80 | #define RxDSnoopEn ETH__BIT(22) /* Rx descriptor snoop enable */ |
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| 81 | #define TxDSnoopEn ETH__BIT(30) /* Tx descriptor snoop enable */ |
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| 82 | |
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| 83 | /* Ethernet 0 address control (High), Offset: 0xf204 */ |
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| 84 | #define HashSnoopEn ETH__BIT(6) /* Hash Table snoop enable */ |
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| 85 | |
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| 86 | /* <skf> */ |
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| 87 | #define GT_CUU_Eth0_AddrCtrlLow 0xf200 |
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| 88 | #define GT_CUU_Eth0_AddrCtrlHigh 0xf204 |
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| 89 | |
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| 90 | /* Table 578: Ethernet TX Descriptor - Command/Status word |
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| 91 | * All bits except F, EI, AM, O are only valid if TX_CMD_L is also set, |
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| 92 | * otherwise should be 0 (tx). |
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| 93 | */ |
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| 94 | |
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| 95 | #define TX_STS_LC ETH__BIT(5) /* Late Collision */ |
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| 96 | #define TX_STS_UR ETH__BIT(6) /* Underrun error */ |
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| 97 | #define TX_STS_RL ETH__BIT(8) /* Retransmit Limit (excession coll) */ |
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| 98 | #define TX_STS_COL ETH__BIT(9) /* Collision Occurred */ |
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| 99 | #define TX_STS_RC(v) ETH__GETBITS(v, 10, 4) /* Retransmit Count */ |
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| 100 | #define TX_STS_ES ETH__BIT(15) /* Error Summary (LC|UR|RL) */ |
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| 101 | #define TX_CMD_L ETH__BIT(16) /* Last - End Of Packet */ |
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| 102 | #define TX_CMD_F ETH__BIT(17) /* First - Start Of Packet */ |
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| 103 | #define TX_CMD_P ETH__BIT(18) /* Pad Packet */ |
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| 104 | #define TX_CMD_GC ETH__BIT(22) /* Generate CRC */ |
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| 105 | #define TX_CMD_EI ETH__BIT(23) /* Enable Interrupt */ |
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| 106 | #define TX_CMD_AM ETH__BIT(30) /* Auto Mode */ |
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| 107 | #define TX_CMD_O ETH__BIT(31) /* Ownership (1=GT 0=CPU) */ |
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| 108 | |
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| 109 | #define TX_CMD_FIRST (TX_CMD_F|TX_CMD_O) |
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| 110 | #define TX_CMD_LAST (TX_CMD_L|TX_CMD_GC|TX_CMD_P|TX_CMD_O) |
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| 111 | |
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| 112 | /* Table 608: Ethernet RX Descriptor - Command/Status Word |
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| 113 | * All bits except F, EI, AM, O are only valid if RX_CMD_L is also set, |
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| 114 | * otherwise should be ignored (rx). |
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| 115 | */ |
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| 116 | #define RX_STS_CE ETH__BIT(0) /* CRC Error */ |
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| 117 | #define RX_STS_COL ETH__BIT(1) /* Collision sensed during reception */ |
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| 118 | #define RX_STS_LC ETH__BIT(5) /* Late Collision (Reserved) */ |
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| 119 | #define RX_STS_OR ETH__BIT(6) /* Overrun Error */ |
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| 120 | #define RX_STS_MFL ETH__BIT(7) /* Max Frame Len Error */ |
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| 121 | #define RX_STS_SF ETH__BIT(8) /* Short Frame Error (< 64 bytes) */ |
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| 122 | #define RX_STS_FT ETH__BIT(11) /* Frame Type (1 = 802.3) */ |
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| 123 | #define RX_STS_M ETH__BIT(12) /* Missed Frame */ |
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| 124 | #define RX_STS_HE ETH__BIT(13) /* Hash Expired (manual match) */ |
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| 125 | #define RX_STS_IGMP ETH__BIT(14) /* IGMP Packet */ |
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| 126 | #define RX_STS_ES ETH__BIT(15) /* Error Summary (CE|COL|LC|OR|MFL|SF) */ |
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| 127 | #define RX_CMD_L ETH__BIT(16) /* Last - End Of Packet */ |
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| 128 | #define RX_CMD_F ETH__BIT(17) /* First - Start Of Packet */ |
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| 129 | #define RX_CMD_EI ETH__BIT(23) /* Enable Interrupt */ |
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| 130 | #define RX_CMD_AM ETH__BIT(30) /* Auto Mode */ |
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| 131 | #define RX_CMD_O ETH__BIT(31) /* Ownership (1=GT 0=CPU) */ |
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| 132 | |
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| 133 | /* Table 586: Hash Table Entry Fields |
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| 134 | */ |
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| 135 | #define HSH_V ETH__LLBIT(0) /* Entry is valid */ |
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| 136 | #define HSH_S ETH__LLBIT(1) /* Skip this entry */ |
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| 137 | #define HSH_RD ETH__LLBIT(2) /* Receive(1) / Discard (0) */ |
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| 138 | #define HSH_R ETH__LLBIT(2) /* Receive(1) */ |
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| 139 | #define HSH_PRIO_GET(v) ETH__LLEXT(v, 51, 2) |
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| 140 | #define HSH_PRIO_INS(v) ETH__LLINS(v, 51) |
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| 141 | #define HSH_ADDR_MASK 0x7fffff8LLU |
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| 142 | #define HSH_LIMIT 12 |
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| 143 | |
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| 144 | |
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| 145 | #define ETH_EPAR 0x2000 /* PHY Address Register */ |
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| 146 | #define ETH_ESMIR 0x2010 /* SMI Register */ |
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| 147 | |
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| 148 | #define ETH_BASE_ETH0 0x2400 /* Ethernet0 Register Base */ |
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| 149 | #define ETH_BASE_ETH1 0x2800 /* Ethernet1 Register Base */ |
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| 150 | #define ETH_BASE_ETH2 0x2c00 /* Ethernet2 Register Base */ |
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| 151 | #define ETH_SIZE 0x0400 /* Register Space */ |
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| 152 | |
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| 153 | #define ETH__EBASE 0x0000 /* Base of Registers */ |
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| 154 | #define ETH__EPCR 0x0000 /* Port Config. Register */ |
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| 155 | #define ETH__EPCXR 0x0008 /* Port Config. Extend Reg */ |
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| 156 | #define ETH__EPCMR 0x0010 /* Port Command Register */ |
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| 157 | #define ETH__EPSR 0x0018 /* Port Status Register */ |
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| 158 | #define ETH__ESPR 0x0020 /* Port Serial Parameters Reg */ |
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| 159 | #define ETH__EHTPR 0x0028 /* Port Hash Table Pointer Reg*/ |
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| 160 | #define ETH__EFCSAL 0x0030 /* Flow Control Src Addr Low */ |
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| 161 | #define ETH__EFCSAH 0x0038 /* Flow Control Src Addr High */ |
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| 162 | #define ETH__ESDCR 0x0040 /* SDMA Configuration Reg */ |
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| 163 | #define ETH__ESDCMR 0x0048 /* SDMA Command Register */ |
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| 164 | #define ETH__EICR 0x0050 /* Interrupt Cause Register */ |
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| 165 | #define ETH__EIMR 0x0058 /* Interrupt Mask Register */ |
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| 166 | #define ETH__EFRDP0 0x0080 /* First Rx Desc Pointer 0 */ |
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| 167 | #define ETH__EFRDP1 0x0084 /* First Rx Desc Pointer 1 */ |
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| 168 | #define ETH__EFRDP2 0x0088 /* First Rx Desc Pointer 2 */ |
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| 169 | #define ETH__EFRDP3 0x008c /* First Rx Desc Pointer 3 */ |
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| 170 | #define ETH__ECRDP0 0x00a0 /* Current Rx Desc Pointer 0 */ |
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| 171 | #define ETH__ECRDP1 0x00a4 /* Current Rx Desc Pointer 1 */ |
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| 172 | #define ETH__ECRDP2 0x00a8 /* Current Rx Desc Pointer 2 */ |
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| 173 | #define ETH__ECRDP3 0x00ac /* Current Rx Desc Pointer 3 */ |
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| 174 | #define ETH__ECTDP0 0x00e0 /* Current Tx Desc Pointer 0 */ |
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| 175 | #define ETH__ECTDP1 0x00e4 /* Current Tx Desc Pointer 1 */ |
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| 176 | #define ETH__EDSCP2P0L 0x0060 /* IP Differentiated Services |
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| 177 | CodePoint to Priority0 low */ |
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| 178 | #define ETH__EDSCP2P0H 0x0064 /* IP Differentiated Services |
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| 179 | CodePoint to Priority0 high*/ |
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| 180 | #define ETH__EDSCP2P1L 0x0068 /* IP Differentiated Services |
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| 181 | CodePoint to Priority1 low */ |
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| 182 | #define ETH__EDSCP2P1H 0x006c /* IP Differentiated Services |
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| 183 | CodePoint to Priority1 high*/ |
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| 184 | #define ETH__EVPT2P 0x0068 /* VLAN Prio. Tag to Priority */ |
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| 185 | #define ETH__EMIBCTRS 0x0100 /* MIB Counters */ |
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| 186 | |
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| 187 | /* SKF : we are only concerned with the Ethernet0 for the mvme5500 board */ |
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| 188 | #define ETH0_EBASE 0x2400 /* Base of Registers */ |
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| 189 | #define ETH0_EPCR 0x2400 /* Port Config. Register */ |
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| 190 | #define ETH0_EPCXR 0x2408 /* Port Config. Extend Reg */ |
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| 191 | #define ETH0_EPCMR 0x2410 /* Port Command Register */ |
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| 192 | #define ETH0_EPSR 0x2418 /* Port Status Register */ |
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| 193 | #define ETH0_ESPR 0x2420 /* Port Serial Parameters Reg */ |
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| 194 | #define ETH0_EHTPR 0x2428 /* Port Hash Table Pointer Reg*/ |
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| 195 | #define ETH0_EFCSAL 0x2430 /* Flow Control Src Addr Low */ |
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| 196 | #define ETH0_EFCSAH 0x2438 /* Flow Control Src Addr High */ |
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| 197 | #define ETH0_ESDCR 0x2440 /* SDMA Configuration Reg */ |
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| 198 | #define ETH0_ESDCMR 0x2448 /* SDMA Command Register */ |
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| 199 | #define ETH0_EICR 0x2450 /* Interrupt Cause Register */ |
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| 200 | #define ETH0_EIMR 0x2458 /* Interrupt Mask Register */ |
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| 201 | #define ETH0_EFRDP0 0x2480 /* First Rx Desc Pointer 0 */ |
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| 202 | #define ETH0_EFRDP1 0x2484 /* First Rx Desc Pointer 1 */ |
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| 203 | #define ETH0_EFRDP2 0x2488 /* First Rx Desc Pointer 2 */ |
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| 204 | #define ETH0_EFRDP3 0x248c /* First Rx Desc Pointer 3 */ |
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| 205 | #define ETH0_ECRDP0 0x24a0 /* Current Rx Desc Pointer 0 */ |
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| 206 | #define ETH0_ECRDP1 0x24a4 /* Current Rx Desc Pointer 1 */ |
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| 207 | #define ETH0_ECRDP2 0x24a8 /* Current Rx Desc Pointer 2 */ |
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| 208 | #define ETH0_ECRDP3 0x24ac /* Current Rx Desc Pointer 3 */ |
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| 209 | #define ETH0_ECTDP0 0x24e0 /* Current Tx Desc Pointer 0 */ |
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| 210 | #define ETH0_ECTDP1 0x24e4 /* Current Tx Desc Pointer 1 */ |
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| 211 | #define ETH0_EDSCP2P0L 0x2460 /* IP Differentiated Services |
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| 212 | CodePoint to Priority0 low */ |
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| 213 | #define ETH0_EDSCP2P0H 0x2464 /* IP Differentiated Services |
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| 214 | CodePoint to Priority0 high*/ |
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| 215 | #define ETH0_EDSCP2P1L 0x2468 /* IP Differentiated Services |
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| 216 | CodePoint to Priority1 low */ |
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| 217 | #define ETH0_EDSCP2P1H 0x246c /* IP Differentiated Services |
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| 218 | CodePoint to Priority1 high*/ |
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| 219 | #define ETH0_EVPT2P 0x2468 /* VLAN Prio. Tag to Priority */ |
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| 220 | #define ETH0_EMIBCTRS 0x2500 /* MIB Counters */ |
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| 221 | |
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| 222 | #define ETH_BASE(n) ETH__GEN(n, EBASE) |
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| 223 | #define ETH_EPCR(n) ETH__GEN(n, EPCR) /* Port Config. Register */ |
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| 224 | #define ETH_EPCXR(n) ETH__GEN(n, EPCXR) /* Port Config. Extend Reg */ |
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| 225 | #define ETH_EPCMR(n) ETH__GEN(n, EPCMR) /* Port Command Register */ |
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| 226 | #define ETH_EPSR(n) ETH__GEN(n, EPSR) /* Port Status Register */ |
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| 227 | #define ETH_ESPR(n) ETH__GEN(n, ESPR) /* Port Serial Parameters Reg */ |
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| 228 | #define ETH_EHTPR(n) ETH__GEN(n, EHPTR) /* Port Hash Table Pointer Reg*/ |
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| 229 | #define ETH_EFCSAL(n) ETH__GEN(n, EFCSAL) /* Flow Control Src Addr Low */ |
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| 230 | #define ETH_EFCSAH(n) ETH__GEN(n, EFCSAH) /* Flow Control Src Addr High */ |
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| 231 | #define ETH_ESDCR(n) ETH__GEN(n, ESDCR) /* SDMA Configuration Reg */ |
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| 232 | #define ETH_ESDCMR(n) ETH__GEN(n, ESDCMR) /* SDMA Command Register */ |
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| 233 | #define ETH_EICR(n) ETH__GEN(n, EICR) /* Interrupt Cause Register */ |
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| 234 | #define ETH_EIMR(n) ETH__GEN(n, EIMR) /* Interrupt Mask Register */ |
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| 235 | #define ETH_EFRDP0(n) ETH__GEN(n, EFRDP0) /* First Rx Desc Pointer 0 */ |
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| 236 | #define ETH_EFRDP1(n) ETH__GEN(n, EFRDP1) /* First Rx Desc Pointer 1 */ |
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| 237 | #define ETH_EFRDP2(n) ETH__GEN(n, EFRDP2) /* First Rx Desc Pointer 2 */ |
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| 238 | #define ETH_EFRDP3(n) ETH__GEN(n, EFRDP3) /* First Rx Desc Pointer 3 */ |
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| 239 | #define ETH_ECRDP0(n) ETH__GEN(n, ECRDP0) /* Current Rx Desc Pointer 0 */ |
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| 240 | #define ETH_ECRDP1(n) ETH__GEN(n, ECRDP1) /* Current Rx Desc Pointer 1 */ |
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| 241 | #define ETH_ECRDP2(n) ETH__GEN(n, ECRDP2) /* Current Rx Desc Pointer 2 */ |
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| 242 | #define ETH_ECRDP3(n) ETH__GEN(n, ECRDP3) /* Current Rx Desc Pointer 3 */ |
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| 243 | #define ETH_ECTDP0(n) ETH__GEN(n, ECTDP0) /* Current Tx Desc Pointer 0 */ |
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| 244 | #define ETH_ECTDP1(n) ETH__GEN(n, ECTDP1) /* Current Tx Desc Pointer 1 */ |
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| 245 | #define ETH_EDSCP2P0L(n) ETH__GEN(n, EDSCP2P0L) /* IP Differentiated Services |
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| 246 | CodePoint to Priority0 low */ |
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| 247 | #define ETH_EDSCP2P0H(n) ETH__GEN(n, EDSCP2P0H) /* IP Differentiated Services |
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| 248 | CodePoint to Priority0 high*/ |
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| 249 | #define ETH_EDSCP2P1L(n) ETH__GEN(n, EDSCP2P1L) /* IP Differentiated Services |
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| 250 | CodePoint to Priority1 low */ |
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| 251 | #define ETH_EDSCP2P1H(n) ETH__GEN(n, EDSCP1P1H) /* IP Differentiated Services |
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| 252 | CodePoint to Priority1 high*/ |
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| 253 | #define ETH_EVPT2P(n) ETH__GEN(n, EVPT2P) /* VLAN Prio. Tag to Priority */ |
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| 254 | #define ETH_EMIBCTRS(n) ETH__GEN(n, EMIBCTRS) /* MIB Counters */ |
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| 255 | |
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| 256 | #define ETH_EPAR_PhyAD_GET(v, n) (((v) >> ((n) * 5)) & 0x1f) |
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| 257 | |
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| 258 | #define ETH_ESMIR_READ(phy, reg) (ETH__INS(phy, 16)|\ |
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| 259 | ETH__INS(reg, 21)|\ |
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| 260 | ETH_ESMIR_ReadOpcode) |
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| 261 | #define ETH_ESMIR_WRITE(phy, reg, val) (ETH__INS(phy, 16)|\ |
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| 262 | ETH__INS(reg, 21)|\ |
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| 263 | ETH__INS(val, 0)|\ |
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| 264 | ETH_ESMIR_WriteOpcode) |
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| 265 | #define ETH_ESMIR_Value_GET(v) ETH__EXT(v, 0, 16) |
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| 266 | #define ETH_ESMIR_WriteOpcode 0 |
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| 267 | #define ETH_ESMIR_ReadOpcode ETH__BIT(26) |
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| 268 | #define ETH_ESMIR_ReadValid ETH__BIT(27) |
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| 269 | #define ETH_ESMIR_Busy ETH__BIT(28) |
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| 270 | |
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| 271 | /* |
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| 272 | * Table 597: Port Configuration Register (PCR) |
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| 273 | * 00:00 PM Promiscuous mode |
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| 274 | * 0: Normal mode (Frames are only received if the |
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| 275 | * destination address is found in the hash |
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| 276 | * table) |
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| 277 | * 1: Promiscuous mode (Frames are received |
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| 278 | * regardless of their destination address. |
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| 279 | * Errored frames are discarded unless the Port |
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| 280 | * Configuration register's PBF bit is set) |
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| 281 | * 01:01 RBM Reject Broadcast Mode |
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| 282 | * 0: Receive broadcast address |
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| 283 | * 1: Reject frames with broadcast address |
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| 284 | * Overridden by the promiscuous mode. |
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| 285 | * 02:02 PBF Pass Bad Frames |
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| 286 | * (0: Normal mode, 1: Pass bad Frames) |
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| 287 | * The Ethernet receiver passes to the CPU errored |
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| 288 | * frames (like fragments and collided packets) |
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| 289 | * that are normally rejected. |
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| 290 | * NOTE: Frames are only passed if they |
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| 291 | * successfully pass address filtering. |
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| 292 | * 06:03 Reserved |
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| 293 | * 07:07 EN Enable (0: Disabled, 1: Enable) |
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| 294 | * When enabled, the ethernet port is ready to |
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| 295 | * transmit/receive. |
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| 296 | * 09:08 LPBK Loop Back Mode |
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| 297 | * 00: Normal mode |
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| 298 | * 01: Internal loop back mode (TX data is looped |
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| 299 | * back to the RX lines. No transition is seen |
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| 300 | * on the interface pins) |
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| 301 | * 10: External loop back mode (TX data is looped |
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| 302 | * back to the RX lines and also transmitted |
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| 303 | * out to the MII interface pins) |
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| 304 | * 11: Reserved |
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| 305 | * 10:10 FC Force Collision |
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| 306 | * 0: Normal mode. |
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| 307 | * 1: Force Collision on any TX frame. |
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| 308 | * For RXM test (in Loopback mode). |
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| 309 | * 11:11 Reserved. |
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| 310 | * 12:12 HS Hash Size |
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| 311 | * 0: 8K address filtering |
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| 312 | * (256KB of memory space required). |
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| 313 | * 1: 512 address filtering |
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| 314 | * ( 16KB of memory space required). |
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| 315 | * 13:13 HM Hash Mode (0: Hash Func. 0; 1: Hash Func. 1) |
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| 316 | * 14:14 HDM Hash Default Mode |
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| 317 | * 0: Discard addresses not found in address table |
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| 318 | * 1: Pass addresses not found in address table |
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| 319 | * 15:15 HD Duplex Mode (0: Half Duplex, 1: Full Duplex) |
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| 320 | * NOTE: Valid only when auto-negotiation for |
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| 321 | * duplex mode is disabled. |
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| 322 | * 30:16 Reserved |
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| 323 | * 31:31 ACCS Accelerate Slot Time |
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| 324 | * (0: Normal mode, 1: Reserved) |
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| 325 | */ |
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| 326 | #define ETH_EPCR_PM ETH__BIT(0) |
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| 327 | #define ETH_EPCR_RBM ETH__BIT(1) |
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| 328 | #define ETH_EPCR_PBF ETH__BIT(2) |
|---|
| 329 | #define ETH_EPCR_EN ETH__BIT(7) |
|---|
| 330 | #define ETH_EPCR_LPBK_GET(v) ETH__BIT(v, 8, 2) |
|---|
| 331 | #define ETH_EPCR_LPBK_Normal 0 |
|---|
| 332 | #define ETH_EPCR_LPBK_Internal 1 |
|---|
| 333 | #define ETH_EPCR_LPBK_External 2 |
|---|
| 334 | #define ETH_EPCR_FC ETH__BIT(10) |
|---|
| 335 | |
|---|
| 336 | #define ETH_EPCR_HS ETH__BIT(12) |
|---|
| 337 | #define ETH_EPCR_HS_8K 0 |
|---|
| 338 | #define ETH_EPCR_HS_512 ETH_EPCR_HS |
|---|
| 339 | |
|---|
| 340 | #define ETH_EPCR_HM ETH__BIT(13) |
|---|
| 341 | #define ETH_EPCR_HM_0 0 |
|---|
| 342 | #define ETH_EPCR_HM_1 ETH_EPCR_HM |
|---|
| 343 | |
|---|
| 344 | #define ETH_EPCR_HDM ETH__BIT(14) |
|---|
| 345 | #define ETH_EPCR_HDM_Discard 0 |
|---|
| 346 | #define ETH_EPCR_HDM_Pass ETH_EPCR_HDM |
|---|
| 347 | |
|---|
| 348 | #define ETH_EPCR_HD_Half 0 |
|---|
| 349 | #define ETH_EPCR_HD_Full ETH_EPCR_HD_Full |
|---|
| 350 | |
|---|
| 351 | #define ETH_EPCR_ACCS ETH__BIT(31) |
|---|
| 352 | |
|---|
| 353 | |
|---|
| 354 | |
|---|
| 355 | /* |
|---|
| 356 | * Table 598: Port Configuration Extend Register (PCXR) |
|---|
| 357 | * 00:00 IGMP IGMP Packets Capture Enable |
|---|
| 358 | * 0: IGMP packets are treated as normal Multicast |
|---|
| 359 | * packets. |
|---|
| 360 | * 1: IGMP packets on IPv4/Ipv6 over Ethernet/802.3 |
|---|
| 361 | * are trapped and sent to high priority RX |
|---|
| 362 | * queue. |
|---|
| 363 | * 01:01 SPAN Spanning Tree Packets Capture Enable |
|---|
| 364 | * 0: BPDU (Bridge Protocol Data Unit) packets are |
|---|
| 365 | * treated as normal Multicast packets. |
|---|
| 366 | * 1: BPDU packets are trapped and sent to high |
|---|
| 367 | * priority RX queue. |
|---|
| 368 | * 02:02 PAR Partition Enable (0: Normal, 1: Partition) |
|---|
| 369 | * When more than 61 collisions occur while |
|---|
| 370 | * transmitting, the port enters Partition mode. |
|---|
| 371 | * It waits for the first good packet from the |
|---|
| 372 | * wire and then goes back to Normal mode. Under |
|---|
| 373 | * Partition mode it continues transmitting, but |
|---|
| 374 | * it does not receive. |
|---|
| 375 | * 05:03 PRIOtx Priority weight in the round-robin between high |
|---|
| 376 | * and low priority TX queues. |
|---|
| 377 | * 000: 1 pkt from HIGH, 1 pkt from LOW. |
|---|
| 378 | * 001: 2 pkt from HIGH, 1 pkt from LOW. |
|---|
| 379 | * 010: 4 pkt from HIGH, 1 pkt from LOW. |
|---|
| 380 | * 011: 6 pkt from HIGH, 1 pkt from LOW. |
|---|
| 381 | * 100: 8 pkt from HIGH, 1 pkt from LOW. |
|---|
| 382 | * 101: 10 pkt from HIGH, 1 pkt from LOW. |
|---|
| 383 | * 110: 12 pkt from HIGH, 1 pkt from LOW. |
|---|
| 384 | * 111: All pkt from HIGH, 0 pkt from LOW. LOW is |
|---|
| 385 | * served only if HIGH is empty. |
|---|
| 386 | * NOTE: If the HIGH queue is emptied before |
|---|
| 387 | * finishing the count, the count is reset |
|---|
| 388 | * until the next first HIGH comes in. |
|---|
| 389 | * 07:06 PRIOrx Default Priority for Packets Received on this |
|---|
| 390 | * Port (00: Lowest priority, 11: Highest priority) |
|---|
| 391 | * 08:08 PRIOrx_Override Override Priority for Packets Received on this |
|---|
| 392 | * Port (0: Do not override, 1: Override with |
|---|
| 393 | * <PRIOrx> field) |
|---|
| 394 | * 09:09 DPLXen Enable Auto-negotiation for Duplex Mode |
|---|
| 395 | * (0: Enable, 1: Disable) |
|---|
| 396 | * 11:10 FCTLen Enable Auto-negotiation for 802.3x Flow-control |
|---|
| 397 | * 0: Enable; When enabled, 1 is written (through |
|---|
| 398 | * SMI access) to the PHY's register 4 bit 10 |
|---|
| 399 | * to advertise flow-control capability. |
|---|
| 400 | * 1: Disable; Only enables flow control after the |
|---|
| 401 | * PHY address is set by the CPU. When changing |
|---|
| 402 | * the PHY address the flow control |
|---|
| 403 | * auto-negotiation must be disabled. |
|---|
| 404 | * 11:11 FLP Force Link Pass |
|---|
| 405 | * (0: Force Link Pass, 1: Do NOT Force Link pass) |
|---|
| 406 | * 12:12 FCTL 802.3x Flow-Control Mode (0: Enable, 1: Disable) |
|---|
| 407 | * NOTE: Only valid when auto negotiation for flow |
|---|
| 408 | * control is disabled. |
|---|
| 409 | * 13:13 Reserved |
|---|
| 410 | * 15:14 MFL Max Frame Length |
|---|
| 411 | * Maximum packet allowed for reception (including |
|---|
| 412 | * CRC): 00: 1518 bytes, 01: 1536 bytes, |
|---|
| 413 | * 10: 2048 bytes, 11: 64K bytes |
|---|
| 414 | * 16:16 MIBclrMode MIB Counters Clear Mode (0: Clear, 1: No effect) |
|---|
| 415 | * 17:17 MIBctrMode Reserved. (MBZ) |
|---|
| 416 | * 18:18 Speed Port Speed (0: 10Mbit/Sec, 1: 100Mbit/Sec) |
|---|
| 417 | * NOTE: Only valid if SpeedEn bit is set. |
|---|
| 418 | * 19:19 SpeedEn Enable Auto-negotiation for Speed |
|---|
| 419 | * (0: Enable, 1: Disable) |
|---|
| 420 | * 20:20 RMIIen RMII enable |
|---|
| 421 | * 0: Port functions as MII port |
|---|
| 422 | * 1: Port functions as RMII port |
|---|
| 423 | * 21:21 DSCPen DSCP enable |
|---|
| 424 | * 0: IP DSCP field decoding is disabled. |
|---|
| 425 | * 1: IP DSCP field decoding is enabled. |
|---|
| 426 | * 31:22 Reserved |
|---|
| 427 | */ |
|---|
| 428 | #define ETH_EPCXR_IGMP ETH__BIT(0) |
|---|
| 429 | #define ETH_EPCXR_SPAN ETH__BIT(1) |
|---|
| 430 | #define ETH_EPCXR_PAR ETH__BIT(2) |
|---|
| 431 | #define ETH_EPCXR_PRIOtx_GET(v) ETH__EXT(v, 3, 3) |
|---|
| 432 | #define ETH_EPCXR_PRIOrx_GET(v) ETH__EXT(v, 3, 3) |
|---|
| 433 | #define ETH_EPCXR_PRIOrx_Override ETH__BIT(8) |
|---|
| 434 | #define ETH_EPCXR_DLPXen ETH__BIT(9) |
|---|
| 435 | #define ETH_EPCXR_FCTLen ETH__BIT(10) |
|---|
| 436 | #define ETH_EPCXR_FLP ETH__BIT(11) |
|---|
| 437 | #define ETH_EPCXR_FCTL ETH__BIT(12) |
|---|
| 438 | #define ETH_EPCXR_MFL_GET(v) ETH__EXT(v, 14, 2) |
|---|
| 439 | #define ETH_EPCXR_MFL_1518 0 |
|---|
| 440 | #define ETH_EPCXR_MFL_1536 1 |
|---|
| 441 | #define ETH_EPCXR_MFL_2048 2 |
|---|
| 442 | #define ETH_EPCXR_MFL_64K 3 |
|---|
| 443 | #define ETH_EPCXR_MIBclrMode ETH__BIT(16) |
|---|
| 444 | #define ETH_EPCXR_MIBctrMode ETH__BIT(17) |
|---|
| 445 | #define ETH_EPCXR_Speed ETH__BIT(18) |
|---|
| 446 | #define ETH_EPCXR_SpeedEn ETH__BIT(19) |
|---|
| 447 | #define ETH_EPCXR_RMIIEn ETH__BIT(20) |
|---|
| 448 | #define ETH_EPCXR_DSCPEn ETH__BIT(21) |
|---|
| 449 | |
|---|
| 450 | |
|---|
| 451 | |
|---|
| 452 | /* |
|---|
| 453 | * Table 599: Port Command Register (PCMR) |
|---|
| 454 | * 14:00 Reserved |
|---|
| 455 | * 15:15 FJ Force Jam / Flow Control |
|---|
| 456 | * When in half-duplex mode, the CPU uses this bit |
|---|
| 457 | * to force collisions on the Ethernet segment. |
|---|
| 458 | * When the CPU recognizes that it is going to run |
|---|
| 459 | * out of receive buffers, it can force the |
|---|
| 460 | * transmitter to send jam frames, forcing |
|---|
| 461 | * collisions on the wire. To allow transmission |
|---|
| 462 | * on the Ethernet segment, the CPU must clear the |
|---|
| 463 | * FJ bit when more resources are available. When |
|---|
| 464 | * in full-duplex and flow-control is enabled, this |
|---|
| 465 | * bit causes the port's transmitter to send |
|---|
| 466 | * flow-control PAUSE packets. The CPU must reset |
|---|
| 467 | * this bit when more resources are available. |
|---|
| 468 | * 31:16 Reserved |
|---|
| 469 | */ |
|---|
| 470 | |
|---|
| 471 | #define ETH_EPCMR_FJ ETH__BIT(15) |
|---|
| 472 | |
|---|
| 473 | |
|---|
| 474 | /* |
|---|
| 475 | * Table 600: Port Status Register (PSR) -- Read Only |
|---|
| 476 | * 00:00 Speed Indicates Port Speed (0: 10Mbs, 1: 100Mbs) |
|---|
| 477 | * 01:01 Duplex Indicates Port Duplex Mode (0: Half, 1: Full) |
|---|
| 478 | * 02:02 Fctl Indicates Flow-control Mode |
|---|
| 479 | * (0: enabled, 1: disabled) |
|---|
| 480 | * 03:03 Link Indicates Link Status (0: down, 1: up) |
|---|
| 481 | * 04:04 Pause Indicates that the port is in flow-control |
|---|
| 482 | * disabled state. This bit is set when an IEEE |
|---|
| 483 | * 802.3x flow-control PAUSE (XOFF) packet is |
|---|
| 484 | * received (assuming that flow-control is |
|---|
| 485 | * enabled and the port is in full-duplex mode). |
|---|
| 486 | * Reset when XON is received, or when the XOFF |
|---|
| 487 | * timer has expired. |
|---|
| 488 | * 05:05 TxLow Tx Low Priority Status |
|---|
| 489 | * Indicates the status of the low priority |
|---|
| 490 | * transmit queue: (0: Stopped, 1: Running) |
|---|
| 491 | * 06:06 TxHigh Tx High Priority Status |
|---|
| 492 | * Indicates the status of the high priority |
|---|
| 493 | * transmit queue: (0: Stopped, 1: Running) |
|---|
| 494 | * 07:07 TXinProg TX in Progress |
|---|
| 495 | * Indicates that the port's transmitter is in an |
|---|
| 496 | * active transmission state. |
|---|
| 497 | * 31:08 Reserved |
|---|
| 498 | */ |
|---|
| 499 | #define ETH_EPSR_Speed ETH__BIT(0) |
|---|
| 500 | #define ETH_EPSR_Duplex ETH__BIT(1) |
|---|
| 501 | #define ETH_EPSR_Fctl ETH__BIT(2) |
|---|
| 502 | #define ETH_EPSR_Link ETH__BIT(3) |
|---|
| 503 | #define ETH_EPSR_Pause ETH__BIT(4) |
|---|
| 504 | #define ETH_EPSR_TxLow ETH__BIT(5) |
|---|
| 505 | #define ETH_EPSR_TxHigh ETH__BIT(6) |
|---|
| 506 | #define ETH_EPSR_TXinProg ETH__BIT(7) |
|---|
| 507 | |
|---|
| 508 | |
|---|
| 509 | /* |
|---|
| 510 | * Table 601: Serial Parameters Register (SPR) |
|---|
| 511 | * 01:00 JAM_LENGTH Two bits to determine the JAM Length |
|---|
| 512 | * (in Backpressure) as follows: |
|---|
| 513 | * 00 = 12K bit-times |
|---|
| 514 | * 01 = 24K bit-times |
|---|
| 515 | * 10 = 32K bit-times |
|---|
| 516 | * 11 = 48K bit-times |
|---|
| 517 | * 06:02 JAM_IPG Five bits to determine the JAM IPG. |
|---|
| 518 | * The step is four bit-times. The value may vary |
|---|
| 519 | * between 4 bit time to 124. |
|---|
| 520 | * 11:07 IPG_JAM_TO_DATA Five bits to determine the IPG JAM to DATA. |
|---|
| 521 | * The step is four bit-times. The value may vary |
|---|
| 522 | * between 4 bit time to 124. |
|---|
| 523 | * 16:12 IPG_DATA Inter-Packet Gap (IPG) |
|---|
| 524 | * The step is four bit-times. The value may vary |
|---|
| 525 | * between 12 bit time to 124. |
|---|
| 526 | * NOTE: These bits may be changed only when the |
|---|
| 527 | * Ethernet ports is disabled. |
|---|
| 528 | * 21:17 Data_Blind Data Blinder |
|---|
| 529 | * The number of nibbles from the beginning of the |
|---|
| 530 | * IPG, in which the IPG counter is restarted when |
|---|
| 531 | * detecting a carrier activity. Following this |
|---|
| 532 | * value, the port enters the Data Blinder zone and |
|---|
| 533 | * does not reset the IPG counter. This ensures |
|---|
| 534 | * fair access to the medium. |
|---|
| 535 | * The default is 10 hex (64 bit times - 2/3 of the |
|---|
| 536 | * default IPG). The step is 4 bit-times. Valid |
|---|
| 537 | * range is 3 to 1F hex nibbles. |
|---|
| 538 | * NOTE: These bits may be only changed when the |
|---|
| 539 | * Ethernet port is disabled. |
|---|
| 540 | * 22:22 Limit4 The number of consecutive packet collisions that |
|---|
| 541 | * occur before the collision counter is reset. |
|---|
| 542 | * 0: The port resets its collision counter after |
|---|
| 543 | * 16 consecutive retransmit trials and |
|---|
| 544 | * restarts the Backoff algorithm. |
|---|
| 545 | * 1: The port resets its collision counter and |
|---|
| 546 | * restarts the Backoff algorithm after 4 |
|---|
| 547 | * consecutive transmit trials. |
|---|
| 548 | * 31:23 Reserved |
|---|
| 549 | */ |
|---|
| 550 | #define ETH_ESPR_JAM_LENGTH_GET(v) ETH__EXT(v, 0, 2) |
|---|
| 551 | #define ETH_ESPR_JAM_IPG_GET(v) ETH__EXT(v, 2, 5) |
|---|
| 552 | #define ETH_ESPR_IPG_JAM_TO_DATA_GET(v) ETH__EXT(v, 7, 5) |
|---|
| 553 | #define ETH_ESPR_IPG_DATA_GET(v) ETH__EXT(v, 12, 5) |
|---|
| 554 | #define ETH_ESPR_Data_Bilnd_GET(v) ETH__EXT(v, 17, 5) |
|---|
| 555 | #define ETH_ESPR_Limit4(v) ETH__BIT(22) |
|---|
| 556 | |
|---|
| 557 | /* |
|---|
| 558 | * Table 602: Hash Table Pointer Register (HTPR) |
|---|
| 559 | * 31:00 HTP 32-bit pointer to the address table. |
|---|
| 560 | * Bits [2:0] must be set to zero. |
|---|
| 561 | */ |
|---|
| 562 | |
|---|
| 563 | /* |
|---|
| 564 | * Table 603: Flow Control Source Address Low (FCSAL) |
|---|
| 565 | * 15:0 SA[15:0] Source Address |
|---|
| 566 | * The least significant bits of the source |
|---|
| 567 | * address for the port. This address is used for |
|---|
| 568 | * Flow Control. |
|---|
| 569 | * 31:16 Reserved |
|---|
| 570 | */ |
|---|
| 571 | |
|---|
| 572 | /* |
|---|
| 573 | * Table 604: Flow Control Source Address High (FCSAH) |
|---|
| 574 | * 31:0 SA[47:16] Source Address |
|---|
| 575 | * The most significant bits of the source address |
|---|
| 576 | * for the port. This address is used for Flow |
|---|
| 577 | * Control. |
|---|
| 578 | */ |
|---|
| 579 | |
|---|
| 580 | |
|---|
| 581 | /* |
|---|
| 582 | * Table 605: SDMA Configuration Register (SDCR) |
|---|
| 583 | * 01:00 Reserved |
|---|
| 584 | * 05:02 RC Retransmit Count |
|---|
| 585 | * Sets the maximum number of retransmits per |
|---|
| 586 | * packet. After executing retransmit for RC |
|---|
| 587 | * times, the TX SDMA closes the descriptor with a |
|---|
| 588 | * Retransmit Limit error indication and processes |
|---|
| 589 | * the next packet. When RC is set to 0, the |
|---|
| 590 | * number of retransmits is unlimited. In this |
|---|
| 591 | * case, the retransmit process is only terminated |
|---|
| 592 | * if CPU issues an Abort command. |
|---|
| 593 | * 06:06 BLMR Big/Little Endian Receive Mode |
|---|
| 594 | * The DMA supports Big or Little Endian |
|---|
| 595 | * configurations on a per channel basis. The BLMR |
|---|
| 596 | * bit only affects data transfer to memory. |
|---|
| 597 | * 0: Big Endian |
|---|
| 598 | * 1: Little Endian |
|---|
| 599 | * 07:07 BLMT Big/Little Endian Transmit Mode |
|---|
| 600 | * The DMA supports Big or Little Endian |
|---|
| 601 | * configurations on a per channel basis. The BLMT |
|---|
| 602 | * bit only affects data transfer from memory. |
|---|
| 603 | * 0: Big Endian |
|---|
| 604 | * 1: Little Endian |
|---|
| 605 | * 08:08 POVR PCI Override |
|---|
| 606 | * When set, causes the SDMA to direct all its |
|---|
| 607 | * accesses in PCI_0 direction and overrides |
|---|
| 608 | * normal address decoding process. |
|---|
| 609 | * 09:09 RIFB Receive Interrupt on Frame Boundaries |
|---|
| 610 | * When set, the SDMA Rx generates interrupts only |
|---|
| 611 | * on frame boundaries (i.e. after writing the |
|---|
| 612 | * frame status to the descriptor). |
|---|
| 613 | * 11:10 Reserved |
|---|
| 614 | * 13:12 BSZ Burst Size |
|---|
| 615 | * Sets the maximum burst size for SDMA |
|---|
| 616 | * transactions: |
|---|
| 617 | * 00: Burst is limited to 1 64bit words. |
|---|
| 618 | * 01: Burst is limited to 2 64bit words. |
|---|
| 619 | * 10: Burst is limited to 4 64bit words. |
|---|
| 620 | * 11: Burst is limited to 8 64bit words. |
|---|
| 621 | * 31:14 Reserved |
|---|
| 622 | */ |
|---|
| 623 | #define ETH_ESDCR_RC_GET(v) ETH__EXT(v, 2, 4) |
|---|
| 624 | #define ETH_ESDCR_BLMR ETH__BIT(6) |
|---|
| 625 | #define ETH_ESDCR_BLMT ETH__BIT(7) |
|---|
| 626 | #define ETH_ESDCR_POVR ETH__BIT(8) |
|---|
| 627 | #define ETH_ESDCR_RIFB ETH__BIT(9) |
|---|
| 628 | #define ETH_ESDCR_BSZ_GET(v) ETH__EXT(v, 12, 2) |
|---|
| 629 | #define ETH_ESDCR_BSZ_SET(v, n) (ETH__CLR(v, 12, 2),\ |
|---|
| 630 | (v) |= ETH__INS(n, 12)) |
|---|
| 631 | #define ETH_ESDCR_BSZ_1 0 |
|---|
| 632 | #define ETH_ESDCR_BSZ_2 1 |
|---|
| 633 | #define ETH_ESDCR_BSZ_4 2 |
|---|
| 634 | #define ETH_ESDCR_BSZ_8 3 |
|---|
| 635 | |
|---|
| 636 | #define ETH_ESDCR_BSZ_Strings { "1 64-bit word", "2 64-bit words", \ |
|---|
| 637 | "4 64-bit words", "8 64-bit words" } |
|---|
| 638 | |
|---|
| 639 | /* |
|---|
| 640 | * Table 606: SDMA Command Register (SDCMR) |
|---|
| 641 | * 06:00 Reserved |
|---|
| 642 | * 07:07 ERD Enable RX DMA. |
|---|
| 643 | * Set to 1 by the CPU to cause the SDMA to start |
|---|
| 644 | * a receive process. Cleared when the CPU issues |
|---|
| 645 | * an Abort Receive command. |
|---|
| 646 | * 14:08 Reserved |
|---|
| 647 | * 15:15 AR Abort Receive |
|---|
| 648 | * Set to 1 by the CPU to abort a receive SDMA |
|---|
| 649 | * operation. When the AR bit is set, the SDMA |
|---|
| 650 | * aborts its current operation and moves to IDLE. |
|---|
| 651 | * No descriptor is closed. The AR bit is cleared |
|---|
| 652 | * upon entering IDLE. After setting the AR bit, |
|---|
| 653 | * the CPU must poll the bit to verify that the |
|---|
| 654 | * abort sequence is completed. |
|---|
| 655 | * 16:16 STDH Stop TX High |
|---|
| 656 | * Set to 1 by the CPU to stop the transmission |
|---|
| 657 | * process from the high priority queue at the end |
|---|
| 658 | * of the current frame. An interrupt is generated |
|---|
| 659 | * when the stop command has been executed. |
|---|
| 660 | * Writing 1 to STDH resets TXDH bit. |
|---|
| 661 | * Writing 0 to this bit has no effect. |
|---|
| 662 | * 17:17 STDL Stop TX Low |
|---|
| 663 | * Set to 1 by the CPU to stop the transmission |
|---|
| 664 | * process from the low priority queue at the end |
|---|
| 665 | * of the current frame. An interrupt is generated |
|---|
| 666 | * when the stop command has been executed. |
|---|
| 667 | * Writing 1 to STDL resets TXDL bit. |
|---|
| 668 | * Writing 0 to this bit has no effect. |
|---|
| 669 | * 22:18 Reserved |
|---|
| 670 | * 23:23 TXDH Start Tx High |
|---|
| 671 | * Set to 1 by the CPU to cause the SDMA to fetch |
|---|
| 672 | * the first descriptor and start a transmit |
|---|
| 673 | * process from the high priority Tx queue. |
|---|
| 674 | * Writing 1 to TXDH resets STDH bit. |
|---|
| 675 | * Writing 0 to this bit has no effect. |
|---|
| 676 | * 24:24 TXDL Start Tx Low |
|---|
| 677 | * Set to 1 by the CPU to cause the SDMA to fetch |
|---|
| 678 | * the first descriptor and start a transmit |
|---|
| 679 | * process from the low priority Tx queue. |
|---|
| 680 | * Writing 1 to TXDL resets STDL bit. |
|---|
| 681 | * Writing 0 to this bit has no effect. |
|---|
| 682 | * 30:25 Reserved |
|---|
| 683 | * 31:31 AT Abort Transmit |
|---|
| 684 | * Set to 1 by the CPU to abort a transmit DMA |
|---|
| 685 | * operation. When the AT bit is set, the SDMA |
|---|
| 686 | * aborts its current operation and moves to IDLE. |
|---|
| 687 | * No descriptor is closed. Cleared upon entering |
|---|
| 688 | * IDLE. After setting AT bit, the CPU must poll |
|---|
| 689 | * it in order to verify that the abort sequence |
|---|
| 690 | * is completed. |
|---|
| 691 | */ |
|---|
| 692 | #define ETH_ESDCMR_ERD ETH__BIT(7) |
|---|
| 693 | #define ETH_ESDCMR_AR ETH__BIT(15) |
|---|
| 694 | #define ETH_ESDCMR_STDH ETH__BIT(16) |
|---|
| 695 | #define ETH_ESDCMR_STDL ETH__BIT(17) |
|---|
| 696 | #define ETH_ESDCMR_TXDH ETH__BIT(23) |
|---|
| 697 | #define ETH_ESDCMR_TXDL ETH__BIT(24) |
|---|
| 698 | #define ETH_ESDCMR_AT ETH__BIT(31) |
|---|
| 699 | |
|---|
| 700 | /* |
|---|
| 701 | * Table 607: Interrupt Cause Register (ICR) |
|---|
| 702 | * 00:00 RxBuffer Rx Buffer Return |
|---|
| 703 | * Indicates an Rx buffer returned to CPU ownership |
|---|
| 704 | * or that the port finished reception of a Rx |
|---|
| 705 | * frame in either priority queues. |
|---|
| 706 | * NOTE: In order to get a Rx Buffer return per |
|---|
| 707 | * priority queue, use bit 19:16. This bit is |
|---|
| 708 | * set upon closing any Rx descriptor which |
|---|
| 709 | * has its EI bit set. To limit the |
|---|
| 710 | * interrupts to frame (rather than buffer) |
|---|
| 711 | * boundaries, the user must set SDMA |
|---|
| 712 | * Configuration register's RIFB bit. When |
|---|
| 713 | * the RIFB bit is set, an interrupt |
|---|
| 714 | * generates only upon closing the first |
|---|
| 715 | * descriptor of a received packet, if this |
|---|
| 716 | * descriptor has it EI bit set. |
|---|
| 717 | * 01:01 Reserved |
|---|
| 718 | * 02:02 TxBufferHigh Tx Buffer for High priority Queue |
|---|
| 719 | * Indicates a Tx buffer returned to CPU ownership |
|---|
| 720 | * or that the port finished transmission of a Tx |
|---|
| 721 | * frame. |
|---|
| 722 | * NOTE: This bit is set upon closing any Tx |
|---|
| 723 | * descriptor which has its EI bit set. To |
|---|
| 724 | * limit the interrupts to frame (rather than |
|---|
| 725 | * buffer) boundaries, the user must set EI |
|---|
| 726 | * only in the last descriptor. |
|---|
| 727 | * 03:03 TxBufferLow Tx Buffer for Low Priority Queue |
|---|
| 728 | * Indicates a Tx buffer returned to CPU ownership |
|---|
| 729 | * or that the port finished transmission of a Tx |
|---|
| 730 | * frame. |
|---|
| 731 | * NOTE: This bit is set upon closing any Tx |
|---|
| 732 | * descriptor which has its EI bit set. To |
|---|
| 733 | * limit the interrupts to frame (rather than |
|---|
| 734 | * buffer) boundaries, the user must set EI |
|---|
| 735 | * only in the last descriptor. |
|---|
| 736 | * 05:04 Reserved |
|---|
| 737 | * 06:06 TxEndHigh Tx End for High Priority Queue |
|---|
| 738 | * Indicates that the Tx DMA stopped processing the |
|---|
| 739 | * high priority queue after stop command, or that |
|---|
| 740 | * it reached the end of the high priority |
|---|
| 741 | * descriptor chain. |
|---|
| 742 | * 07:07 TxEndLow Tx End for Low Priority Queue |
|---|
| 743 | * Indicates that the Tx DMA stopped processing the |
|---|
| 744 | * low priority queue after stop command, or that |
|---|
| 745 | * it reached the end of the low priority |
|---|
| 746 | * descriptor chain. |
|---|
| 747 | * 08:08 RxError Rx Resource Error |
|---|
| 748 | * Indicates a Rx resource error event in one of |
|---|
| 749 | * the priority queues. |
|---|
| 750 | * NOTE: To get a Rx Resource Error Indication per |
|---|
| 751 | * priority queue, use bit 23:20. |
|---|
| 752 | * 09:09 Reserved |
|---|
| 753 | * 10:10 TxErrorHigh Tx Resource Error for High Priority Queue |
|---|
| 754 | * Indicates a Tx resource error event during |
|---|
| 755 | * packet transmission from the high priority queue |
|---|
| 756 | * 11:11 TxErrorLow Tx Resource Error for Low Priority Queue |
|---|
| 757 | * Indicates a Tx resource error event during |
|---|
| 758 | * packet transmission from the low priority queue |
|---|
| 759 | * 12:12 RxOVR Rx Overrun |
|---|
| 760 | * Indicates an overrun event that occurred during |
|---|
| 761 | * reception of a packet. |
|---|
| 762 | * 13:13 TxUdr Tx Underrun |
|---|
| 763 | * Indicates an underrun event that occurred during |
|---|
| 764 | * transmission of packet from either queue. |
|---|
| 765 | * 15:14 Reserved |
|---|
| 766 | * 16:16 RxBuffer-Queue[0] Rx Buffer Return in Priority Queue[0] |
|---|
| 767 | * Indicates a Rx buffer returned to CPU ownership |
|---|
| 768 | * or that the port completed reception of a Rx |
|---|
| 769 | * frame in a receive priority queue[0] |
|---|
| 770 | * 17:17 RxBuffer-Queue[1] Rx Buffer Return in Priority Queue[1] |
|---|
| 771 | * Indicates a Rx buffer returned to CPU ownership |
|---|
| 772 | * or that the port completed reception of a Rx |
|---|
| 773 | * frame in a receive priority queue[1]. |
|---|
| 774 | * 18:18 RxBuffer-Queue[2] Rx Buffer Return in Priority Queue[2] |
|---|
| 775 | * Indicates a Rx buffer returned to CPU ownership |
|---|
| 776 | * or that the port completed reception of a Rx |
|---|
| 777 | * frame in a receive priority queue[2]. |
|---|
| 778 | * 19:19 RxBuffer-Queue[3] Rx Buffer Return in Priority Queue[3] |
|---|
| 779 | * Indicates a Rx buffer returned to CPU ownership |
|---|
| 780 | * or that the port completed reception of a Rx |
|---|
| 781 | * frame in a receive priority queue[3]. |
|---|
| 782 | * 20:20 RxError-Queue[0] Rx Resource Error in Priority Queue[0] |
|---|
| 783 | * Indicates a Rx resource error event in receive |
|---|
| 784 | * priority queue[0]. |
|---|
| 785 | * 21:21 RxError-Queue[1] Rx Resource Error in Priority Queue[1] |
|---|
| 786 | * Indicates a Rx resource error event in receive |
|---|
| 787 | * priority queue[1]. |
|---|
| 788 | * 22:22 RxError-Queue[2] Rx Resource Error in Priority Queue[2] |
|---|
| 789 | * Indicates a Rx resource error event in receive |
|---|
| 790 | * priority queue[2]. |
|---|
| 791 | * 23:23 RxError-Queue[3] Rx Resource Error in Priority Queue[3] |
|---|
| 792 | * Indicates a Rx resource error event in receive |
|---|
| 793 | * priority queue[3]. |
|---|
| 794 | * 27:24 Reserved |
|---|
| 795 | * 28:29 MIIPhySTC MII PHY Status Change |
|---|
| 796 | * Indicates a status change reported by the PHY |
|---|
| 797 | * connected to this port. Set when the MII |
|---|
| 798 | * management interface block identifies a change |
|---|
| 799 | * in PHY's register 1. |
|---|
| 800 | * 29:29 SMIdone SMI Command Done |
|---|
| 801 | * Indicates that the SMI completed a MII |
|---|
| 802 | * management command (either read or write) that |
|---|
| 803 | * was initiated by the CPU writing to the SMI |
|---|
| 804 | * register. |
|---|
| 805 | * 30:30 Reserved |
|---|
| 806 | * 31:31 EtherIntSum Ethernet Interrupt Summary |
|---|
| 807 | * This bit is a logical OR of the (unmasked) bits |
|---|
| 808 | * [30:04] in the Interrupt Cause register. |
|---|
| 809 | */ |
|---|
| 810 | |
|---|
| 811 | #define ETH_IR_RxBuffer ETH__BIT(0) |
|---|
| 812 | #define ETH_IR_TxBufferHigh ETH__BIT(2) |
|---|
| 813 | #define ETH_IR_TxBufferLow ETH__BIT(3) |
|---|
| 814 | #define ETH_IR_TxEndHigh ETH__BIT(6) |
|---|
| 815 | #define ETH_IR_TxEndLow ETH__BIT(7) |
|---|
| 816 | #define ETH_IR_RxError ETH__BIT(8) |
|---|
| 817 | #define ETH_IR_TxErrorHigh ETH__BIT(10) |
|---|
| 818 | #define ETH_IR_TxErrorLow ETH__BIT(11) |
|---|
| 819 | #define ETH_IR_RxOVR ETH__BIT(12) |
|---|
| 820 | #define ETH_IR_TxUdr ETH__BIT(13) |
|---|
| 821 | #define ETH_IR_RxBuffer_0 ETH__BIT(16) |
|---|
| 822 | #define ETH_IR_RxBuffer_1 ETH__BIT(17) |
|---|
| 823 | #define ETH_IR_RxBuffer_2 ETH__BIT(18) |
|---|
| 824 | #define ETH_IR_RxBuffer_3 ETH__BIT(19) |
|---|
| 825 | #define ETH_IR_RxBuffer_GET(v) ETH__EXT(v, 16, 4) |
|---|
| 826 | #define ETH_IR_RxError_0 ETH__BIT(20) |
|---|
| 827 | #define ETH_IR_RxError_1 ETH__BIT(21) |
|---|
| 828 | #define ETH_IR_RxError_2 ETH__BIT(22) |
|---|
| 829 | #define ETH_IR_RxError_3 ETH__BIT(23) |
|---|
| 830 | #define ETH_IR_RxError_GET(v) ETH__EXT(v, 20, 4) |
|---|
| 831 | #define ETH_IR_RxBits (ETH_IR_RxBuffer_0|\ |
|---|
| 832 | ETH_IR_RxBuffer_1|\ |
|---|
| 833 | ETH_IR_RxBuffer_2|\ |
|---|
| 834 | ETH_IR_RxBuffer_3|\ |
|---|
| 835 | ETH_IR_RxError_0|\ |
|---|
| 836 | ETH_IR_RxError_1|\ |
|---|
| 837 | ETH_IR_RxError_2|\ |
|---|
| 838 | ETH_IR_RxError_3) |
|---|
| 839 | #define ETH_IR_MIIPhySTC ETH__BIT(28) |
|---|
| 840 | #define ETH_IR_SMIdone ETH__BIT(29) |
|---|
| 841 | #define ETH_IR_EtherIntSum (1<<31) |
|---|
| 842 | #define ETH_IR_Summary (1<<31) |
|---|
| 843 | #define ETH_IR_ErrorSum 0x803d00 |
|---|
| 844 | #define INTR_RX_ERROR 0x801100 |
|---|
| 845 | #define INTR_TX_ERROR 0x002c00 |
|---|
| 846 | |
|---|
| 847 | /* |
|---|
| 848 | * Table 608: Interrupt Mask Register (IMR) |
|---|
| 849 | * 31:00 Various Mask bits for the Interrupt Cause register. |
|---|
| 850 | */ |
|---|
| 851 | |
|---|
| 852 | /* |
|---|
| 853 | * Table 609: IP Differentiated Services CodePoint to Priority0 low (DSCP2P0L), |
|---|
| 854 | * 31:00 Priority0_low The LSB priority bits for DSCP[31:0] entries. |
|---|
| 855 | */ |
|---|
| 856 | |
|---|
| 857 | /* |
|---|
| 858 | * Table 610: IP Differentiated Services CodePoint to Priority0 high (DSCP2P0H) |
|---|
| 859 | * 31:00 Priority0_high The LSB priority bits for DSCP[63:32] entries. |
|---|
| 860 | */ |
|---|
| 861 | |
|---|
| 862 | /* |
|---|
| 863 | * Table 611: IP Differentiated Services CodePoint to Priority1 low (DSCP2P1L) |
|---|
| 864 | * 31:00 Priority1_low The MSB priority bits for DSCP[31:0] entries. |
|---|
| 865 | */ |
|---|
| 866 | |
|---|
| 867 | /* |
|---|
| 868 | * Table 612: IP Differentiated Services CodePoint to Priority1 high (DSCP2P1H) |
|---|
| 869 | * 31:00 Priority1_high The MSB priority bit for DSCP[63:32] entries. |
|---|
| 870 | */ |
|---|
| 871 | |
|---|
| 872 | /* |
|---|
| 873 | * Table 613: VLAN Priority Tag to Priority (VPT2P) |
|---|
| 874 | * 07:00 Priority0 The LSB priority bits for VLAN Priority[7:0] |
|---|
| 875 | * entries. |
|---|
| 876 | * 15:08 Priority1 The MSB priority bits for VLAN Priority[7:0] |
|---|
| 877 | * entries. |
|---|
| 878 | * 31:16 Reserved |
|---|
| 879 | */ |
|---|
| 880 | #endif /* _DEV_GTETHREG_H_ */ |
|---|
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