source: rtems/c/src/lib/libbsp/powerpc/mvme5500/network/GT64260eth.c @ 21ca2199

4.104.114.84.95
Last change on this file since 21ca2199 was de7e68db, checked in by Ralf Corsepius <ralf.corsepius@…>, on Dec 15, 2006 at 7:31:14 AM

Use ioctl_command_t as arg to ioctl functions.

  • Property mode set to 100644
File size: 44.8 KB
Line 
1/* GT64260eth.c : GT64260 10/100 Mb ethernet MAC driver
2 *
3 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
4 *
5 * Copyright (c) 2003,2004 RTEMS/Mvme5500 port by S. Kate Feng <feng1@bnl.gov>
6 *
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 *    notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 *    notice, this list of conditions and the following disclaimer in the
16 *    documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 *    must display the following acknowledgement:
19 *      This product includes software developed for the NetBSD Project by
20 *      Allegro Networks, Inc., and Wasabi Systems, Inc.
21 * 4. The name of Allegro Networks, Inc. may not be used to endorse
22 *    or promote products derived from this software without specific prior
23 *    written permission.
24 * 5. The name of Wasabi Systems, Inc. may not be used to endorse
25 *    or promote products derived from this software without specific prior
26 *    written permission.
27 *
28 * S. Kate Feng, other notes in addition to porting to RTEMS :
29 *
30 * 1) Mvme5500 uses Eth0 (controller 0) of the GT64260 to implement
31 *    the 10/100 BaseT Ethernet with PCI Master Data Byte Swap\
32 *    control.
33 * 2) It implements hardware snoop instead of software snoop
34 *    to ensure SDRAM cache coherency.
35 * 3) The origianl ISR is optimized to minimize interrupt latencies,
36 *    and to reduce system overhead. The driver's work is done by one single
37 *    task who blocks on an event while it is idle.  This implemetation
38 *    is heavily inspired by the modification of SVGM network driver for
39 *    RTEMS port written by Till Straumann, whihc is licensed under the
40 *    EPICS open source. Ditto the GT64260eth_sendpacket().
41 *
42 */
43#define BYTE_ORDER BIG_ENDIAN
44
45#define INET
46
47#include <rtems.h>
48#include <rtems/bspIo.h>            /* printk */
49#include <stdio.h>                  /* printf for statistics */
50#include <string.h>
51
52#include <libcpu/io.h>              /* inp & friends */
53#include <libcpu/spr.h>             /* registers.h is included here */
54#include <bsp.h>
55
56#include <sys/param.h>
57#include <sys/systm.h>
58#include <sys/mbuf.h>
59
60#include <rtems/rtems_bsdnet.h>
61#include <rtems/rtems_bsdnet_internal.h>
62#include <rtems/error.h>          
63#include <errno.h>
64
65#include <rtems/rtems/types.h>
66
67#include <sys/queue.h>
68
69#include <sys/ioctl.h>
70#include <sys/socket.h>
71#include <sys/sockio.h>             /* SIOCADDMULTI, SIOC...     */
72#include <net/if.h>
73#include <net/if_dl.h>
74#include <netinet/in.h>
75#include <netinet/if_ether.h>
76
77#ifdef INET
78#include <netinet/in_var.h>
79#endif
80
81#include <bsp/irq.h>
82#include <bsp/GT64260ethreg.h>
83#include <bsp/GT64260eth.h>
84#include <bsp/VPD.h>
85
86#define GT_ETH_TASK_NAME  "Geth"
87#define PKT_BUF_SZ 1536
88#define SOFTC_ALIGN  31   
89#define HASH_ALIGN   15   
90
91#define TXQ_HiLmt_OFF 2
92
93/* <skf>
94 * 1. printk debug is for diagnosis only, which may cause
95 * unexpected result, especially if txq is under heavy load
96 * because CPU is fast with a decent cache.
97 */
98#define GTeth_debug 0
99#define GTeth_rx_debug 0
100
101#if 0
102#define GE_FORGOT
103#define GE_NORX
104#define GT_DEBUG
105#endif
106
107/* RTEMS event to kill the daemon */
108#define KILL_EVENT              RTEMS_EVENT_1
109/* RTEMS event to (re)start the transmitter */
110#define START_TRANSMIT_EVENT    RTEMS_EVENT_2
111/* RTEMS events used by the ISR */
112#define RX_EVENT                RTEMS_EVENT_3
113#define TX_EVENT                RTEMS_EVENT_4
114#define ERR_EVENT               RTEMS_EVENT_5
115
116#define ALL_EVENTS (KILL_EVENT|START_TRANSMIT_EVENT|RX_EVENT|TX_EVENT|ERR_EVENT)
117
118enum GTeth_whack_op {
119        GE_WHACK_START,         GE_WHACK_RESTART,
120        GE_WHACK_CHANGE,        GE_WHACK_STOP
121};
122
123enum GTeth_hash_op {
124        GE_HASH_ADD,            GE_HASH_REMOVE,
125};
126
127#define ET_MINLEN 64            /* minimum message length */
128
129static int GTeth_ifioctl(struct ifnet *ifp, ioctl_command_t cmd, caddr_t data);
130static void GTeth_ifstart (struct ifnet *);
131static void GTeth_ifchange(struct GTeth_softc *sc);
132static void GTeth_init_rx_ring(struct GTeth_softc *sc);
133static void GT64260eth_daemon(void *arg);
134static int GT64260eth_sendpacket(struct GTeth_softc *sc,struct mbuf *m);
135static unsigned GTeth_txq_done(struct GTeth_softc *sc);
136static void GTeth_tx_cleanup(struct GTeth_softc *sc);
137static void GTeth_tx_start(struct GTeth_softc *sc);
138static void GTeth_tx_stop(struct GTeth_softc *sc);
139static void GTeth_rx_cleanup(struct GTeth_softc *sc);
140static int GT64260eth_rx(struct GTeth_softc *sc);
141static void GTeth_rx_setup(struct GTeth_softc *sc);
142static void GTeth_rxprio_setup(struct GTeth_softc *sc);
143static void GTeth_rx_stop(struct GTeth_softc *dc);
144static void GT64260eth_isr();
145static int GTeth_hash_compute(struct GTeth_softc *sc,unsigned char eaddr[ETHER_ADDR_LEN]);
146static int GTeth_hash_entry_op(struct GTeth_softc *sc, enum GTeth_hash_op op,
147        enum GTeth_rxprio prio,unsigned char eaddr[ETHER_ADDR_LEN]);
148
149static int GTeth_hash_fill(struct GTeth_softc *sc);
150static void GTeth_hash_init(struct GTeth_softc *sc);
151
152static struct GTeth_softc *root_GT64260eth_dev = NULL;
153
154static void GT64260eth_irq_on(const rtems_irq_connect_data *irq)
155{
156  struct GTeth_softc *sc;
157
158  for (sc= root_GT64260eth_dev; sc; sc= sc-> next_module) {
159    printk("GT64260eth_irq_on\n");
160    outl(0x30883444,ETH0_EIMR); /* MOTLoad default interrupt mask */
161    return;
162  } 
163}
164
165static void GT64260eth_irq_off(const rtems_irq_connect_data *irq)
166{
167  struct GTeth_softc *sc;
168
169  for (sc= root_GT64260eth_dev; sc; sc= sc-> next_module)
170      outl(0, ETH0_EIMR);
171}
172
173static int GT64260eth_irq_is_on(const rtems_irq_connect_data *irq)
174{
175  return(inl(ETH0_EICR) & ETH_IR_EtherIntSum);
176}
177
178static void GT64260eth_isr()
179{
180  struct GTeth_softc *sc = root_GT64260eth_dev;
181  rtems_event_set  events=0;
182  uint32_t cause;
183
184
185  cause = inl(ETH0_EICR);
186  outl( ~cause,ETH0_EICR);  /* clear the ICR */
187
188  /* ETH_IR_RxBuffer_3|ETH_IR_RxError_3 */
189  if (cause & 0x880000) {
190     sc->stats.rxInterrupts++;
191     events |= RX_EVENT;
192  }
193  /* If there is an error, we want to continue to next descriptor */
194  /* ETH_IR_TxBufferHigh|ETH_IR_TxEndHigh|ETH_IR_TxErrorHigh */
195  if (cause & 0x444) {
196       sc->stats.txInterrupts++;
197       events |= TX_EVENT;
198       /* It seems to be unnecessary. However, it's there
199        * to be on the safe side due to the datasheet.
200        * So far, it does not seem to affect the network performance
201        * based on the EPICS catime.
202        */
203       /* ETH_ESDCMR_TXDH | ETH_ESDCMR_ERD = 0x800080 */
204       if ((sc->txq_nactive > 1)&& ((inl(ETH0_ESDCMR)&ETH_ESDCMR_TXDH)==0))
205          outl(0x800080,ETH0_ESDCMR);
206
207
208  }
209  if ( (!cause) || (cause & 0x803d00)) {
210       sc->intr_errsts[sc->intr_err_ptr2++]=cause;
211       sc->intr_err_ptr2 %=INTR_ERR_SIZE;   /* Till Straumann */
212       events |= ERR_EVENT;
213  }
214
215  rtems_event_send(sc->daemonTid, events);
216}
217
218static rtems_irq_connect_data GT64260ethIrqData={
219        BSP_MAIN_ETH0_IRQ,
220        (rtems_irq_hdl) GT64260eth_isr,
221        NULL,
222        (rtems_irq_enable) GT64260eth_irq_on,
223        (rtems_irq_disable) GT64260eth_irq_off,
224        (rtems_irq_is_enabled) GT64260eth_irq_is_on, 
225};
226
227static void GT64260eth_init_hw(struct GTeth_softc *sc)
228{
229
230#ifdef GT_DEBUG
231  printk("GT64260eth_init_hw(");
232#endif
233  /* Kate Feng : Turn the hardware snoop on as MOTLoad did not have
234   * it on by default.
235   */
236  outl(RxBSnoopEn|TxBSnoopEn|RxDSnoopEn|TxDSnoopEn, GT_CUU_Eth0_AddrCtrlLow);
237  outl(HashSnoopEn, GT_CUU_Eth0_AddrCtrlHigh);
238
239  sc->rxq_intrbits=0;
240  sc->sc_flags=0;
241 
242#ifndef GE_NORX
243  GTeth_rx_setup(sc);
244#endif
245
246#ifndef GE_NOTX
247  GTeth_tx_start(sc);
248#endif
249
250  sc->sc_pcr |= ETH_EPCR_HS_512;
251  outl(sc->sc_pcr, ETH0_EPCR);
252  outl(sc->sc_pcxr, ETH0_EPCXR); /* port config. extended reg. */
253  outl(0, ETH0_EICR); /* interrupt cause register */
254  outl(sc->sc_intrmask, ETH0_EIMR);
255#ifndef GE_NOHASH
256  /* Port Hash Table Pointer Reg*/
257  outl(((unsigned) sc->sc_hashtable),ETH0_EHTPR);
258#endif
259#ifndef GE_NORX
260  outl(ETH_ESDCMR_ERD,ETH0_ESDCMR); /* enable Rx DMA in SDMA Command Register */
261  sc->sc_flags |= GE_RXACTIVE;
262#endif
263#ifdef GT_DEBUG
264  printk("SDCMR 0x%x ", inl(ETH0_ESDCMR));
265#endif
266
267  /* connect the interrupt handler which should
268   * take care of enabling interrupts
269   */
270  if (!BSP_install_rtems_irq_handler(&GT64260ethIrqData))
271     rtems_panic("GT64260eth: unable to install ISR");
272   
273  /* The ethernet port is ready to transmit/receive */
274  outl(sc->sc_pcr | ETH_EPCR_EN, ETH0_EPCR);
275
276#ifdef GT_DEBUG
277  printk(")\n");
278#endif
279}
280
281static void GT64260eth_stop_hw(struct GTeth_softc *sc)
282{
283
284  printk("GT64260eth_stop_hw(");
285
286  /* remove our interrupt handler which will also
287  * disable interrupts at the MPIC and the device
288  * itself
289  */
290  if (!BSP_remove_rtems_irq_handler(&GT64260ethIrqData))
291     rtems_panic("Yellowfin: unable to remove IRQ handler!");
292
293  outl(sc->sc_pcr, ETH0_EPCR);
294  outl(0, ETH0_EIMR);
295
296  sc->arpcom.ac_if.if_flags &= ~IFF_RUNNING;
297#ifndef GE_NOTX
298  GTeth_tx_stop(sc);
299#endif
300#ifndef GE_NORX
301  GTeth_rx_stop(sc);
302#endif
303  sc->sc_hashtable = NULL;
304  if (GTeth_debug>0) printk(")");
305}
306
307static void GT64260eth_stop(struct GTeth_softc *sc)
308{
309  if (GTeth_debug>0) printk("GT64260eth_stop(");
310
311  /* The hardware is shutdown in the daemon */
312  /* kill the daemon. We also must release the networking
313   * semaphore or there'll be a deadlock...
314   */
315  rtems_event_send(sc->daemonTid, KILL_EVENT);
316  rtems_bsdnet_semaphore_release();
317
318  sc->daemonTid=0;
319  /* now wait for it to die */
320  rtems_semaphore_obtain(sc->daemonSync,RTEMS_WAIT,RTEMS_NO_TIMEOUT);
321
322  /* reacquire the bsdnet semaphore */
323  rtems_bsdnet_semaphore_obtain();
324  if (GTeth_debug>0) printk(")");
325}
326
327static void GT64260eth_ifinit(void *arg)
328{
329  struct GTeth_softc *sc = (struct GTeth_softc*)arg;
330  int i;
331
332#ifdef GT_DEBUG
333  printk("GT64260eth_ifinit(): daemon ID: 0x%08x)\n", sc->daemonTid);
334#endif
335  if (sc->daemonTid) {
336#ifdef GT_DEBUG
337     printk("GT64260eth: daemon already up, doing nothing\n");
338#endif
339     return;
340  }
341
342#ifndef GE_NOHASH
343  /* Mvme5500, the user must initialize the hash table before enabling the
344   * Ethernet controller
345   */
346  GTeth_hash_init(sc);
347  GTeth_hash_fill(sc);
348#endif
349
350  sc->intr_err_ptr1=0;
351  sc->intr_err_ptr2=0;
352  for (i=0; i< INTR_ERR_SIZE; i++) sc->intr_errsts[i]=0;
353
354  /* initialize the hardware (we are holding the network semaphore at this point) */
355  (void)GT64260eth_init_hw(sc);
356
357  /* launch network daemon */
358
359  /* NOTE:
360   * in ss-20011025 (and later) any task created by 'bsdnet_newproc' is
361   * wrapped by code which acquires the network semaphore...
362   */
363   sc->daemonTid = rtems_bsdnet_newproc(GT_ETH_TASK_NAME,4096,GT64260eth_daemon,arg);
364
365  /* Tell the world that we're running */
366  sc->arpcom.ac_if.if_flags |= IFF_RUNNING;
367
368}
369
370/* attach parameter tells us whether to attach or to detach the driver */
371/* Attach this instance, and then all the sub-devices */
372int rtems_GT64260eth_driver_attach(struct rtems_bsdnet_ifconfig *config, int attach)
373{
374  struct GTeth_softc *sc;
375  struct ifnet *ifp;
376  unsigned sdcr, data;
377  unsigned char hwaddr[6];
378  int i, unit, phyaddr;
379  void     *softc_mem;
380  char     *name;
381
382  unit = rtems_bsdnet_parse_driver_name(config, &name);
383  if (unit < 0) return 0;
384 
385  printk("\nEthernet driver name %s unit %d \n",name, unit);
386  printk("Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.\n");
387  printk("(c) 2004, Brookhaven National Lab. <feng1@bnl.gov> (RTEMS/mvme5500 port)\n");
388
389  /* Make certain elements e.g. descriptor lists are aligned. */
390  softc_mem = rtems_bsdnet_malloc(sizeof(*sc) + SOFTC_ALIGN, M_FREE, M_NOWAIT);
391
392  /* Check for the very unlikely case of no memory. */
393  if (softc_mem == NULL)
394     rtems_panic("GT64260eth: OUT OF MEMORY");
395
396  sc = (void *)(((long)softc_mem + SOFTC_ALIGN) & ~SOFTC_ALIGN);
397  memset(sc, 0, sizeof(*sc));
398
399  if (GTeth_debug>0) printk("txq_desc[0] addr:%x, rxq_desc[0] addr:%x, sizeof sc %d\n",&sc->txq_desc[0], &sc->rxq_desc[0], sizeof(*sc));
400
401  sc->sc_macno = unit-1;
402
403  data = inl(ETH_EPAR);
404  phyaddr = ETH_EPAR_PhyAD_GET(data, sc->sc_macno);
405
406  /* try to read HW address from the device if not overridden
407   * by config
408   */
409  if (config->hardware_address) {
410     memcpy(hwaddr, config->hardware_address, ETHER_ADDR_LEN);
411  } else {
412    printk("Read EEPROM ");
413     for (i = 0; i < 6; i++)
414       hwaddr[i] = ConfVPD_buff[VPD_ENET0_OFFSET+i];
415  }
416
417#ifdef GT_DEBUG
418  printk("using MAC addr from device:");
419  for (i = 0; i < ETHER_ADDR_LEN; i++) printk("%x:", hwaddr[i]);
420  printk("\n");
421#endif
422
423  memcpy(sc->arpcom.ac_enaddr, hwaddr, ETHER_ADDR_LEN);
424
425  ifp = &sc->arpcom.ac_if;
426
427  sc->sc_pcr = inl(ETH0_EPCR);
428  sc->sc_pcxr = inl(ETH0_EPCXR);
429  sc->sc_intrmask = inl(ETH0_EIMR) | ETH_IR_MIIPhySTC;
430
431  printk("address %s\n", ether_sprintf(hwaddr));
432
433#ifdef GT_DEBUG
434  printk(", pcr %x, pcxr %x ", sc->sc_pcr, sc->sc_pcxr);
435#endif
436
437
438  sc->sc_pcxr |= ETH_EPCXR_PRIOrx_Override;
439  sc->sc_pcxr |= (3<<6); /* highest priority only */
440  sc->sc_pcxr &= ~ETH_EPCXR_RMIIEn;  /* MII mode */
441
442  /* Max. Frame Length (packet) allowed for reception is 1536 bytes,
443   * instead of 2048 (MOTLoad default) or 64K.
444   */
445  sc->sc_pcxr &= ~(3 << 14);
446  sc->sc_pcxr |= (ETH_EPCXR_MFL_1536 << 14);
447  sc->sc_max_frame_length = PKT_BUF_SZ;
448
449
450  if (sc->sc_pcr & ETH_EPCR_EN) {
451      int tries = 1000;
452      /* Abort transmitter and receiver and wait for them to quiese*/
453      outl(ETH_ESDCMR_AR|ETH_ESDCMR_AT,ETH0_ESDCMR);
454      do {
455        rtems_bsp_delay(100);
456      } while (tries-- > 0 && (inl(ETH0_ESDCMR) & (ETH_ESDCMR_AR|ETH_ESDCMR_AT)));
457  }
458#ifdef GT_DEBUG
459  printk(", phy %d (mii)\n", phyaddr);
460  printk("ETH0_ESDCMR %x ", inl(ETH0_ESDCMR));
461#endif
462
463  sc->sc_pcr &= ~(ETH_EPCR_EN | ETH_EPCR_RBM | ETH_EPCR_PM | ETH_EPCR_PBF);
464
465#ifdef GT_DEBUG
466        printk("Now sc_pcr %x,sc_pcxr %x", sc->sc_pcr, sc->sc_pcxr);
467#endif
468
469  /*
470   * Now turn off the GT.  If it didn't quiese, too ***ing bad.
471   */
472  outl(sc->sc_pcr, ETH0_EPCR);
473  outl(sc->sc_intrmask, ETH0_EIMR);
474  sdcr = inl(ETH0_ESDCR);
475  /* Burst size is limited to 4 64bit words */
476  ETH_ESDCR_BSZ_SET(sdcr, ETH_ESDCR_BSZ_4);
477  sdcr |= ETH_ESDCR_RIFB;/*limit interrupt on frame boundaries, instead of buffer*/
478#if 0
479  sdcr &= ~(ETH_ESDCR_BLMT|ETH_ESDCR_BLMR); /* MOTLoad defualt Big-endian */
480#endif
481  outl(sdcr, ETH0_ESDCR);
482
483#ifdef GT_DEBUG
484  printk("sdcr %x \n", sdcr);
485#endif
486
487  if (phyaddr== -1) rtems_panic("MII auto negotiation ?");
488
489  ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
490
491  ifp->if_softc = sc;
492
493  /* set this interface's name and unit */
494  ifp->if_unit = unit;
495  ifp->if_name = name;
496
497  ifp->if_mtu = config->mtu ? config->mtu : ETHERMTU;
498
499  ifp->if_init = GT64260eth_ifinit;
500  ifp->if_ioctl = GTeth_ifioctl;
501  ifp->if_start = GTeth_ifstart;
502  ifp->if_output = ether_output;
503
504  /*  ifp->if_watchdog = GTeth_ifwatchdog;*/
505
506  if (ifp->if_snd.ifq_maxlen == 0)
507    ifp->if_snd.ifq_maxlen = ifqmaxlen; 
508
509  /* create the synchronization semaphore */
510  if (RTEMS_SUCCESSFUL != rtems_semaphore_create(
511     rtems_build_name('G','e','t','h'),0,0,0,&sc->daemonSync))
512     rtems_panic("GT64260eth: semaphore creation failed");
513
514  sc->next_module = root_GT64260eth_dev;
515  root_GT64260eth_dev = sc;
516
517  /* Actually attach the interface */
518  if_attach(ifp);
519  ether_ifattach(ifp);
520
521#ifdef GT_DEBUG
522  printk("GT64260eth: Ethernet driver has been attached (handle 0x%08x,ifp 0x%08x)\n",sc, ifp);
523#endif
524
525  return(1);
526}
527
528static void GT64260eth_stats(struct GTeth_softc *sc)
529{
530  struct ifnet *ifp = &sc->arpcom.ac_if;
531
532  printf("       Rx Interrupts:%-8lu\n", sc->stats.rxInterrupts);
533  printf("     Receive Packets:%-8lu\n", ifp->if_ipackets);
534  printf("     Receive  errors:%-8lu\n", ifp->if_ierrors);
535  printf("      Framing Errors:%-8lu\n", sc->stats.frame_errors);
536  printf("          Crc Errors:%-8lu\n", sc->stats.crc_errors);
537  printf("    Oversized Frames:%-8lu\n", sc->stats.length_errors);
538  printf("         Active Rxqs:%-8u\n",  sc->rxq_active); 
539  printf("       Tx Interrupts:%-8lu\n", sc->stats.txInterrupts);
540  printf("Multi-Buffer Packets:%-8lu\n", sc->stats.txMultiBuffPacket);
541  printf("   Transmitt Packets:%-8lu\n", ifp->if_opackets);
542  printf("   Transmitt  errors:%-8lu\n", ifp->if_oerrors);
543  printf("    Tx/Rx collisions:%-8lu\n", ifp->if_collisions);
544  printf("         Active Txqs:%-8u\n", sc->txq_nactive); 
545}
546
547static int GTeth_ifioctl(struct ifnet *ifp, ioctl_command_t cmd, caddr_t data)
548{
549  struct GTeth_softc *sc = ifp->if_softc;
550  struct ifreq *ifr = (struct ifreq *) data;
551
552  int error = 0;
553
554#ifdef GT_DEBUG
555  printk("GTeth_ifioctl(");
556#endif
557
558  switch (cmd) {
559    default:
560      if (GTeth_debug >0) {
561         printk("etherioctl(");
562         if (cmd== SIOCSIFADDR) printk("SIOCSIFADDR ");
563      }
564      return ether_ioctl(ifp, cmd, data);
565
566    case SIOCSIFFLAGS:
567       switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) {
568            case IFF_RUNNING:   /* not up, so we stop */
569                 GT64260eth_stop(sc);
570                 break;
571            case IFF_UP:  /* not running, so we start */
572                 GT64260eth_ifinit(sc);
573                 break;
574            case IFF_UP|IFF_RUNNING:/* active->active, update */
575                 GT64260eth_stop(sc);
576                 GT64260eth_ifinit(sc);
577                 break;
578            default:                    /* idle->idle: do nothing */
579                 break;
580       }
581       break;
582    case SIO_RTEMS_SHOW_STATS:
583       GT64260eth_stats (sc);
584       break;
585    case SIOCADDMULTI:
586    case SIOCDELMULTI:
587       error = (cmd == SIOCADDMULTI)
588                  ? ether_addmulti(ifr, &sc->arpcom)
589                  : ether_delmulti(ifr, &sc->arpcom);
590       if (error == ENETRESET) {
591           if (ifp->if_flags & IFF_RUNNING)
592              GTeth_ifchange(sc);
593              error = 0;
594       }
595       break;
596    case SIOCSIFMTU:
597       if (ifr->ifr_mtu > ETHERMTU || ifr->ifr_mtu < ETHERMIN) {
598          error = EINVAL;
599          break;
600       }
601       ifp->if_mtu = ifr->ifr_mtu;
602       break;
603  }
604
605#ifdef GT_DEBUG
606  printk("exit ioctl\n");
607#endif 
608  return error;
609}
610
611static void GTeth_ifstart(struct ifnet *ifp)
612{
613  struct GTeth_softc *sc = ifp->if_softc;
614
615#ifdef GT_DEBUG
616  printk("GTeth_ifstart(");
617#endif
618
619  if ((ifp->if_flags & IFF_RUNNING) == 0) {
620#ifdef GT_DEBUG
621     printk("IFF_RUNNING==0\n");
622#endif         
623     return;
624  }
625
626  ifp->if_flags |= IFF_OACTIVE;
627  rtems_event_send (sc->daemonTid, START_TRANSMIT_EVENT);
628#ifdef GT_DEBUG
629  printk(")\n");
630#endif
631}
632
633/* Initialize the Rx rings */
634static void GTeth_init_rx_ring(struct GTeth_softc *sc)
635{
636  int i;
637  volatile struct GTeth_desc *rxd;
638  unsigned nxtaddr;
639
640  sc->rxq_fi=0;
641  sc->rxq_head_desc = &sc->rxq_desc[0];
642  rxd = sc->rxq_head_desc;
643
644  sc->rxq_desc_busaddr = (unsigned long) sc->rxq_head_desc;
645#ifdef GT_DEBUG
646  printk("rxq_desc_busaddr %x ,&sc->rxq_desc[0] %x\n",
647        sc->rxq_desc_busaddr, sc->rxq_head_desc);
648#endif
649
650  nxtaddr = sc->rxq_desc_busaddr + sizeof(*rxd);
651  sc->rx_buf_sz = (sc->arpcom.ac_if.if_mtu <= 1500 ? PKT_BUF_SZ : sc->arpcom.ac_if.if_mtu + 32);
652  sc->rxq_active = RX_RING_SIZE;
653
654  for (i = 0; i < RX_RING_SIZE; i++, rxd++, nxtaddr += sizeof(*rxd)) {
655    struct mbuf *m;
656 
657    rxd->ed_lencnt= sc->rx_buf_sz <<16;
658    rxd->ed_cmdsts = RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI;
659
660    MGETHDR(m, M_WAIT, MT_DATA);
661    MCLGET(m, M_WAIT);
662    m->m_pkthdr.rcvif =  &sc->arpcom.ac_if;
663    sc->rxq_mbuf[i] = m;
664
665    /* convert mbuf pointer to data pointer of correct type */ 
666    rxd->ed_bufptr = (unsigned) mtod(m, void *);
667
668    /*
669     * update the nxtptr to point to the next txd.
670     */
671    if (i == RX_RING_SIZE - 1)
672        nxtaddr = sc->rxq_desc_busaddr;
673    rxd->ed_nxtptr = nxtaddr;
674
675#ifdef GT_DEBUG
676  printk("ed_lencnt %x, rx_buf_sz %x ",rxd->ed_lencnt, sc->rx_buf_sz);
677  printk("ed_cmdsts %x \n",rxd->ed_cmdsts);
678  printk("mbuf @ 0x%x, next desc. @ 0x%x\n",rxd->ed_bufptr,rxd->ed_nxtptr);
679#endif
680  }
681}
682
683void GTeth_rxprio_setup(struct GTeth_softc *sc)
684{
685
686  GTeth_init_rx_ring(sc);
687
688  sc->rxq_intrbits = ETH_IR_RxBuffer|ETH_IR_RxError|ETH_IR_RxBuffer_3|ETH_IR_RxError_3;
689}
690
691static int GT64260eth_rx(struct GTeth_softc *sc)
692{
693  struct ifnet *ifp = &sc->arpcom.ac_if;
694  struct mbuf *m;
695  int nloops=0;
696
697#ifdef GT_DEBUG
698  if (GTeth_rx_debug>0) printk("GT64260eth_rx(");
699#endif
700
701  while (sc->rxq_active > 0) {
702    volatile struct GTeth_desc *rxd = &sc->rxq_desc[sc->rxq_fi];
703    struct ether_header *eh;
704    unsigned int cmdsts;
705    unsigned int byteCount;
706
707    cmdsts = rxd->ed_cmdsts;
708
709    /*
710     * Sometimes the GE "forgets" to reset the ownership bit.
711     * But if the length has been rewritten, the packet is ours
712     * so pretend the O bit is set.
713     *
714     */
715    byteCount = rxd->ed_lencnt & 0xffff;
716
717    if (cmdsts & RX_CMD_O) {
718      if (byteCount == 0) 
719         return(0);
720
721     /* <Kate Feng> Setting command/status to be zero seems to eliminate
722      * the spurious interrupt associated with the GE_FORGOT issue.
723      */
724      rxd->ed_cmdsts=0; 
725
726#ifdef GE_FORGOT
727      /*
728       * For dignosis purpose only. Not a good practice to turn it on
729       */
730      printk("Rxq %d %d %d\n", sc->rxq_fi, byteCount,nloops);
731#endif
732    }
733
734    /* GT gave the ownership back to the CPU or the length has
735     * been rewritten , which means there
736     * is new packet in the descriptor/buffer
737     */
738
739    nloops++;
740    /*
741     * If this is not a single buffer packet with no errors
742     * or for some reason it's bigger than our frame size,
743     * ignore it and go to the next packet.
744     */
745    if ((cmdsts & (RX_CMD_F|RX_CMD_L|RX_STS_ES)) !=
746                            (RX_CMD_F|RX_CMD_L) ||
747                    byteCount > sc->sc_max_frame_length) {
748        --sc->rxq_active;
749        ifp->if_ipackets++;
750        ifp->if_ierrors++;
751        if (cmdsts & RX_STS_OR) sc->stats.or_errors++;
752        if (cmdsts & RX_STS_CE) sc->stats.crc_errors++;
753        if (cmdsts & RX_STS_MFL) sc->stats.length_errors++;
754        if (cmdsts & RX_STS_SF) sc->stats.frame_errors++;
755        if ((cmdsts & RX_STS_LC) || (cmdsts & RX_STS_COL))
756           ifp->if_collisions++;
757        goto give_it_back;
758     }
759     m = sc->rxq_mbuf[sc->rxq_fi];
760     m->m_len = m->m_pkthdr.len = byteCount - sizeof(struct ether_header);
761     eh = mtod (m, struct ether_header *);
762     m->m_data += sizeof(struct ether_header);
763     ether_input (ifp, eh, m);
764
765     ifp->if_ipackets++;
766     ifp->if_ibytes+=byteCount;
767     --sc->rxq_active;
768
769     give_it_back:
770     MGETHDR (m, M_WAIT, MT_DATA);
771     MCLGET (m, M_WAIT);
772     m->m_pkthdr.rcvif = ifp;
773     sc->rxq_mbuf[sc->rxq_fi]= m;
774     /* convert mbuf pointer to data pointer of correct type */ 
775     rxd->ed_bufptr = (unsigned) mtod(m, void*); 
776     rxd->ed_lencnt = (unsigned long) sc->rx_buf_sz <<16;
777     rxd->ed_cmdsts = RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI;
778
779     if (++sc->rxq_fi == RX_RING_SIZE) sc->rxq_fi = 0;
780
781     sc->rxq_active++;
782  } /* while (sc->rxq_active > 0) */
783#ifdef GT_DEBUG
784  if (GTeth_rx_debug>0) printk(")");
785#endif
786  return nloops;
787}
788
789static void GTeth_rx_setup(struct GTeth_softc *sc)
790{
791
792  if (GTeth_rx_debug>0) printk("GTeth_rx_setup(");
793
794  GTeth_rxprio_setup(sc);
795
796  if ((sc->sc_flags & GE_RXACTIVE) == 0) {
797     /* First Rx Descriptor Pointer 3 */
798     outl( sc->rxq_desc_busaddr, ETH0_EFRDP3);
799     /* Current Rx Descriptor Pointer 3 */
800     outl( sc->rxq_desc_busaddr,ETH0_ECRDP3);
801#ifdef GT_DEBUG
802     printk("ETH0_EFRDP3 0x%x, ETH0_ECRDP3 0x%x \n", inl(ETH0_EFRDP3),
803            inl(ETH0_ECRDP3)); 
804#endif
805  }
806  sc->sc_intrmask |= sc->rxq_intrbits;
807
808  if (GTeth_rx_debug>0) printk(")\n");
809}
810
811static void GTeth_rx_cleanup(struct GTeth_softc *sc)
812{
813  int i;
814
815  if (GTeth_rx_debug>0) printk( "GTeth_rx_cleanup(");
816
817  for (i=0; i< RX_RING_SIZE; i++) {
818    if (sc->rxq_mbuf[i]) {
819      m_freem(sc->rxq_mbuf[i]);
820      sc->rxq_mbuf[i]=0;
821    }
822  }
823  if (GTeth_rx_debug>0) printk(")");
824}
825
826static void GTeth_rx_stop(struct GTeth_softc *sc)
827{
828  if (GTeth_rx_debug>0) printk( "GTeth_rx_stop(");
829  sc->sc_flags &= ~GE_RXACTIVE;
830  sc->sc_idlemask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer_3|ETH_IR_RxError_3);
831  sc->sc_intrmask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer_3|ETH_IR_RxError_3);
832  outl(sc->sc_intrmask, ETH0_EIMR);
833  outl(ETH_ESDCMR_AR, ETH0_ESDCMR); /* abort receive */
834  do {
835     rtems_bsp_delay(10);
836  } while (inl(ETH0_ESDCMR) & ETH_ESDCMR_AR);
837  GTeth_rx_cleanup(sc);
838  if (GTeth_rx_debug>0) printk(")");
839}
840
841static void GTeth_txq_free(struct GTeth_softc *sc, unsigned cmdsts)
842{
843  struct ifnet *ifp = &sc->arpcom.ac_if;
844  volatile struct GTeth_desc *txd = &sc->txq_desc[sc->txq_fi];
845
846  /* ownership is sent back to CPU */
847  if (GTeth_debug>0) printk("txq%d,active %d\n", sc->txq_fi, sc->txq_nactive);
848
849  txd->ed_cmdsts &= ~TX_CMD_O; /* <skf> in case GT forgot */
850
851  /* statistics */
852  ifp->if_opackets++;
853  ifp->if_obytes += sc->txq_mbuf[sc->txq_fi]->m_len;
854  if (cmdsts & TX_STS_ES) {
855       ifp->if_oerrors++;
856       if ((cmdsts & TX_STS_LC) || (cmdsts & TX_STS_COL))
857           ifp->if_collisions++;
858  }
859  /* Free the original mbuf chain */
860  m_freem(sc->txq_mbuf[sc->txq_fi]);
861  sc->txq_mbuf[sc->txq_fi] = 0;
862  ifp->if_timer = 5;
863
864  sc->txq_free++;
865  if (++sc->txq_fi == TX_RING_SIZE) sc->txq_fi = 0;
866  --sc->txq_nactive;
867}
868
869static int txq_high_limit(struct GTeth_softc *sc)
870{
871  /*
872   * Have we [over]consumed our limit of descriptors?
873   * Do we have enough free descriptors?
874   */
875  if ( TX_RING_SIZE == sc->txq_nactive + TXQ_HiLmt_OFF) {
876     volatile struct GTeth_desc *txd2 = &sc->txq_desc[sc->txq_fi];
877     unsigned cmdsts;
878
879     cmdsts = txd2->ed_cmdsts;
880     if (cmdsts & TX_CMD_O) {  /* Ownership (1=GT 0=CPU) */
881         int nextin;
882
883         /*
884          * Sometime the Discovery forgets to update the
885          * last descriptor.  See if CPU owned the descriptor
886          * after it (since we know we've turned that to
887          * the discovery and if CPU owned it, the Discovery
888          * gave it back).  If CPU does, we know the Discovery
889          * gave back this one but forgot to mark it back to CPU.
890          */
891         nextin = (sc->txq_fi + 1) % TX_RING_SIZE;
892         if (sc->txq_desc[nextin].ed_cmdsts & TX_CMD_O) {
893#if 0
894            printk("Overconsuming Tx descriptors!\n");
895#endif
896            return 1;
897         }
898         printk("Txq %d forgot\n", sc->txq_fi);
899     }
900    /* Txq ring is almost full, let's free the current buffer here */
901#if 0
902    printk("Txq ring near full, free desc%d\n",sc->txq_fi);
903#endif
904    GTeth_txq_free(sc, cmdsts);
905  } /* end if ( TX_RING_SIZE == sc->txq_nactive + TXQ_HiLmt_OFF) */
906  return 0;
907}
908
909static int GT64260eth_sendpacket(struct GTeth_softc *sc,struct mbuf *m)
910{
911  volatile struct GTeth_desc *txd = &sc->txq_desc[sc->txq_lo];
912  unsigned intrmask = sc->sc_intrmask;
913  unsigned index= sc->txq_lo;
914
915  /*
916   * The end-of-list descriptor we put on last time is the starting point
917   * for this packet.  The GT is supposed to terminate list processing on
918   * a NULL nxtptr but that currently is broken so a CPU-owned descriptor
919   * must terminate the list.
920   */
921  intrmask = sc->sc_intrmask;
922
923  if ( !(m->m_next)) /* single buffer packet */
924    sc->txq_mbuf[index]= m;
925  else /* multiple mbufs in this packet */
926  { 
927    struct mbuf *mtp, *mdest;
928    volatile unsigned char *pt;
929    int len, y;
930
931#ifdef GT_DEBUG
932    printk("multi mbufs ");
933#endif   
934    MGETHDR(mdest, M_WAIT, MT_DATA);
935    MCLGET(mdest, M_WAIT);
936    pt = (volatile unsigned char *)mdest->m_data;
937    for (mtp=m,len=0;mtp;mtp=mtp->m_next) {
938      if ( (y=(len+mtp->m_len)) > sizeof(union mcluster)) {
939        /* GT64260 allows us to chain the remaining to the nex
940         * free descriptors.
941         */
942        printk("packet size %x > mcluster %x\n", y,sizeof(union mcluster)); 
943        rtems_panic("GT64260eth : packet too large ");
944      }
945      memcpy((void *)pt,(char *)mtp->m_data, mtp->m_len);
946      pt += mtp->m_len;
947#if 0
948      printk("%d ",mtp->m_len);
949#endif
950      len += mtp->m_len;
951    }
952#if 0
953    printk("\n");
954#endif
955    mdest->m_len=len;
956    /* free old mbuf chain */
957    m_freem(m);
958    sc->txq_mbuf[index] = m = mdest;
959    sc->stats.txMultiBuffPacket++;
960  }
961  if (m->m_len < ET_MINLEN) m->m_len = ET_MINLEN;
962
963  txd->ed_bufptr = (unsigned) mtod(m, void*); 
964  txd->ed_lencnt = m->m_len << 16;
965  /*txd->ed_cmdsts = TX_CMD_L|TX_CMD_GC|TX_CMD_P|TX_CMD_O|TX_CMD_F|TX_CMD_EI;*/
966  txd->ed_cmdsts = 0x80c70000;
967
968#ifdef GT_DEBUG
969  printk("len = %d, cmdsts 0x%x ", m->m_len,txd->ed_cmdsts);
970#endif
971
972  /*
973   * Tell the SDMA engine to "Fetch!"
974   * Start Tx high.
975   */
976  sc->txq_nactive++;
977  outl(0x800080, ETH0_ESDCMR); /* ETH_ESDCMR_TXDH| ETH_ESDCMR_ERD */
978  if ( ++sc->txq_lo == TX_RING_SIZE) sc->txq_lo = 0;
979  sc->txq_free--;
980
981#if 0
982  /*
983   * Since we have put an item into the packet queue, we now want
984   * an interrupt when the transmit queue finishes processing the
985   * list.  But only update the mask if needs changing.
986   */
987  intrmask |= sc->txq_intrbits & ( ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh);
988  if (sc->sc_intrmask != intrmask) {
989      sc->sc_intrmask = intrmask;
990      outl(sc->sc_intrmask, ETH0_EIMR);
991  }
992#endif
993
994#if 0
995  printk("EICR= %x, EIMR= %x ", inl(ETH0_EICR), inl(ETH0_EIMR));
996  printk("%s:transmit frame #%d queued in slot %d.\n",
997              sc->arpcom.ac_if.if_name, sc->txq_lo, index);
998  printk("pcr %x, pcxr %x DMA dcr %x cmr %x\n", inl(ETH0_EPCR), inl(ETH0_EPCXR), inl(ETH0_ESDCR), inl(ETH0_ESDCMR));
999#endif
1000
1001  return 1;
1002}
1003
1004static unsigned GTeth_txq_done(struct GTeth_softc *sc)
1005{
1006  if (GTeth_debug>0) printk("Txdone(" );
1007
1008  while (sc->txq_nactive > 0) {
1009    /* next to be returned to the CPU */
1010    volatile struct GTeth_desc *txd = &sc->txq_desc[sc->txq_fi];
1011    unsigned cmdsts;
1012
1013    /* if GT64260 still owns it ....... */
1014    if ((cmdsts = txd->ed_cmdsts) & TX_CMD_O) {
1015       int nextin;
1016
1017       /* Someone quoted :
1018        * "Sometimes the Discovery forgets to update the
1019        * ownership bit in the descriptor."
1020        * <skf> More correctly, the last descriptor of each
1021        * transmitted frame is returned to CPU ownership and
1022        * status is updated only after the actual transmission
1023        * of the packet is completed.  Also, if there is an error
1024        * during transmission, we want to continue the
1025        * transmission of the next descriptor, in additions to
1026        * reporting the error.
1027        */
1028       /* The last descriptor */
1029       if (sc->txq_nactive == 1) return(0);
1030
1031       /*
1032        * Sometimes the Discovery forgets to update the
1033        * ownership bit in the descriptor.  See if CPU owned
1034        * the descriptor after it (since we know we've turned
1035        * that to the Discovery and if CPU owned it now then the
1036        * Discovery gave it back).  If we do, we know the
1037        * Discovery gave back this one but forgot to mark it
1038        * back to CPU.
1039        */
1040       nextin = (sc->txq_fi + 1) % TX_RING_SIZE;
1041
1042       if (sc->txq_desc[nextin].ed_cmdsts & TX_CMD_O) return(0); 
1043       printk("Txq%d forgot\n",sc->txq_fi);
1044    } /* end checking GT64260eth owner */
1045    GTeth_txq_free(sc, cmdsts);   
1046  }  /* end while */
1047  if (GTeth_debug>0) printk(")\n");
1048  return(1);
1049}
1050
1051static void GTeth_tx_start(struct GTeth_softc *sc)
1052{
1053  int i;
1054  volatile struct GTeth_desc *txd;
1055  unsigned nxtaddr;
1056
1057#ifdef GT_DEBUG
1058  printk("GTeth_tx_start(");
1059#endif
1060  sc->sc_intrmask &= ~(ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh|
1061                             ETH_IR_TxEndLow |ETH_IR_TxBufferLow);
1062
1063  txd = &sc->txq_desc[0];
1064  sc->txq_desc_busaddr = (unsigned long) &sc->txq_desc[0];
1065#ifdef GT_DEBUG
1066  printk("txq_desc_busaddr %x, &sc->txq_desc[0] %x \n",
1067         sc->txq_desc_busaddr,&sc->txq_desc[0]);
1068#endif
1069
1070  nxtaddr = sc->txq_desc_busaddr + sizeof(*txd);
1071
1072  sc->txq_pendq.ifq_maxlen = 10;
1073  sc->txq_pendq.ifq_head= NULL;
1074  sc->txq_pendq.ifq_tail= NULL;
1075  sc->txq_nactive = 0;
1076  sc->txq_fi = 0;
1077  sc->txq_lo = 0;
1078  sc->txq_inptr = PKT_BUF_SZ;
1079  sc->txq_outptr = 0;
1080  sc->txq_free = TX_RING_SIZE;
1081
1082  for (i = 0; i < TX_RING_SIZE;
1083       i++, txd++,  nxtaddr += sizeof(*txd)) {
1084      sc->txq_mbuf[i]=0;
1085      txd->ed_bufptr = 0;
1086
1087      /*
1088       * update the nxtptr to point to the next txd.
1089       */
1090      txd->ed_cmdsts = 0;
1091      if ( i== TX_RING_SIZE-1) nxtaddr = sc->txq_desc_busaddr;
1092      txd->ed_nxtptr =  nxtaddr;
1093#ifdef GT_DEBUG
1094      printk("next desc. @ 0x%x\n",txd->ed_nxtptr);
1095#endif
1096  }
1097 
1098  sc->txq_intrbits = ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh;
1099  sc->txq_esdcmrbits = ETH_ESDCMR_TXDH; /* Start Tx high */
1100  sc->txq_epsrbits = ETH_EPSR_TxHigh;
1101  /* offset to current tx desc ptr reg */
1102  sc->txq_ectdp = (caddr_t)ETH0_ECTDP1;
1103  /* Current Tx Desc Pointer 1 */
1104  outl(sc->txq_desc_busaddr,ETH0_ECTDP1);
1105
1106#ifdef GT_DEBUG
1107  printk(")\n");
1108#endif
1109}
1110
1111static void GTeth_tx_cleanup(struct GTeth_softc *sc)
1112{
1113  int i;
1114
1115  for (i=0; i< TX_RING_SIZE; i++) {
1116    if (sc->txq_mbuf[i]) {
1117      m_freem(sc->txq_mbuf[i]);
1118      sc->txq_mbuf[i]=0;
1119    }
1120  }
1121}
1122
1123static void GTeth_tx_stop(struct GTeth_softc *sc)
1124{
1125  /* SDMA command register : stop Tx high and low */
1126  outl(ETH_ESDCMR_STDH|ETH_ESDCMR_STDL, ETH0_ESDCMR);
1127
1128  GTeth_txq_done(sc);
1129  sc->sc_intrmask &= ~(ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh|
1130                             ETH_IR_TxEndLow |ETH_IR_TxBufferLow);
1131  GTeth_tx_cleanup(sc);
1132
1133  sc->arpcom.ac_if.if_timer = 0;
1134}
1135
1136/* TOCHECK : Should it be about rx or tx ? */
1137static void GTeth_ifchange(struct GTeth_softc *sc)
1138{
1139  if (GTeth_debug>0) printk("GTeth_ifchange(");
1140  if (GTeth_debug>5) printk("(pcr=%#x,imr=%#x)",inl(ETH0_EPCR),inl(ETH0_EIMR));
1141  printk("SIOCADDMULTI (SIOCDELMULTI): is it about rx or tx ?\n");
1142  outl(sc->sc_pcr | ETH_EPCR_EN, ETH0_EPCR);
1143  outl(sc->sc_intrmask, ETH0_EIMR);
1144  GTeth_ifstart(&sc->arpcom.ac_if);
1145  /* Current Tx Desc Pointer 0 and 1 */
1146  if (GTeth_debug>5) printk("(ectdp0=%#x, ectdp1=%#x)",
1147            inl(ETH0_ECTDP0), inl(ETH0_ECTDP1));
1148  if (GTeth_debug>0) printk(")");
1149}
1150
1151static int GTeth_hash_compute(struct GTeth_softc *sc,unsigned char eaddr[ETHER_ADDR_LEN])
1152{
1153  unsigned w0, add0, add1;
1154  unsigned result;
1155
1156  if (GTeth_debug>0) printk("GTeth_hash_compute(");
1157  add0 = ((unsigned) eaddr[5] <<  0) |
1158         ((unsigned) eaddr[4] <<  8) |
1159         ((unsigned) eaddr[3] << 16);
1160
1161  add0 = ((add0 & 0x00f0f0f0) >> 4) | ((add0 & 0x000f0f0f) << 4);
1162  add0 = ((add0 & 0x00cccccc) >> 2) | ((add0 & 0x00333333) << 2);
1163  add0 = ((add0 & 0x00aaaaaa) >> 1) | ((add0 & 0x00555555) << 1);
1164
1165  add1 = ((unsigned) eaddr[2] <<  0) |
1166         ((unsigned) eaddr[1] <<  8) |
1167         ((unsigned) eaddr[0] << 16);
1168
1169  add1 = ((add1 & 0x00f0f0f0) >> 4) | ((add1 & 0x000f0f0f) << 4);
1170  add1 = ((add1 & 0x00cccccc) >> 2) | ((add1 & 0x00333333) << 2);
1171  add1 = ((add1 & 0x00aaaaaa) >> 1) | ((add1 & 0x00555555) << 1);
1172
1173#ifdef GT_DEBUG
1174  printk("eaddr= %s add1:%x add0:%x\n", ether_sprintf1(eaddr), add1, add0);
1175#endif
1176   
1177  /*
1178   * hashResult is the 15 bits Hash entry address.
1179   * ethernetADD is a 48 bit number, which is derived from the Ethernet
1180   * MAC address, by nibble swapping in every byte (i.e MAC address
1181   * of 0x123456789abc translates to ethernetADD of 0x21436587a9cb).
1182   */
1183  if ((sc->sc_pcr & ETH_EPCR_HM) == 0) {
1184     /*
1185      * hashResult[14:0] = hashFunc0(ethernetADD[47:0])
1186      *
1187      * hashFunc0 calculates the hashResult in the following manner:
1188      * hashResult[ 8:0] = ethernetADD[14:8,1,0]
1189      * XOR ethernetADD[23:15] XOR ethernetADD[32:24]
1190      */
1191     result = (add0 & 3) | ((add0 >> 6) & ~3);
1192     result ^= (add0 >> 15) ^ (add1 >>  0);
1193     result &= 0x1ff;
1194     /*
1195      *   hashResult[14:9] = ethernetADD[7:2]
1196      */
1197     result |= (add0 & ~3) << 7;        /* excess bits will be masked */
1198#ifdef GT_DEBUG
1199     printk("hash result %x  ", result & 0x7fff);
1200#endif
1201  } else {
1202#define TRIBITFLIP      073516240       /* yes its in octal */
1203     /*
1204      * hashResult[14:0] = hashFunc1(ethernetADD[47:0])
1205      *
1206      * hashFunc1 calculates the hashResult in the following manner:
1207      * hashResult[08:00] = ethernetADD[06:14]
1208      * XOR ethernetADD[15:23] XOR ethernetADD[24:32]
1209      */
1210     w0 = ((add0 >> 6) ^ (add0 >> 15) ^ (add1)) & 0x1ff;
1211     /*
1212      * Now bitswap those 9 bits
1213      */
1214     result = 0;
1215     result |= ((TRIBITFLIP >> (((w0 >> 0) & 7) * 3)) & 7) << 6;
1216     result |= ((TRIBITFLIP >> (((w0 >> 3) & 7) * 3)) & 7) << 3;
1217     result |= ((TRIBITFLIP >> (((w0 >> 6) & 7) * 3)) & 7) << 0;
1218
1219     /*
1220      *   hashResult[14:09] = ethernetADD[00:05]
1221      */
1222     result |= ((TRIBITFLIP >> (((add0 >> 0) & 7) * 3)) & 7) << 12;
1223     result |= ((TRIBITFLIP >> (((add0 >> 3) & 7) * 3)) & 7) << 9;
1224#ifdef GT_DEBUG
1225     printk("1(%#x)", result);
1226#endif
1227  }
1228#ifdef GT_DEBUG
1229  printk(")");
1230#endif
1231
1232  /* 1/2K address filtering (MOTLoad default )? ->16KB memory required
1233   * or 8k address filtering ? -> 256KB memory required
1234   */
1235  return result & ((sc->sc_pcr & ETH_EPCR_HS_512) ? 0x7ff : 0x7fff);
1236}
1237
1238static int GTeth_hash_entry_op(struct GTeth_softc *sc, enum GTeth_hash_op op,
1239        enum GTeth_rxprio prio,unsigned char eaddr[ETHER_ADDR_LEN])
1240{
1241  unsigned long long he;
1242  unsigned long long *maybe_he_p = NULL;
1243  int limit;
1244  int hash;
1245  int maybe_hash = 0;
1246
1247#ifdef GT_DEBUG
1248  printk("GTeth_hash_entry_op(prio %d ", prio);
1249#endif
1250
1251  hash = GTeth_hash_compute(sc, eaddr);
1252
1253  if (sc->sc_hashtable == NULL) {
1254        rtems_panic("hashtable == NULL!");
1255  }
1256#ifdef GT_DEBUG
1257  printk("Hash computed %x eaddr %s\n", hash,ether_sprintf1(eaddr));
1258#endif
1259
1260  /*
1261   * Assume we are going to insert so create the hash entry we
1262   * are going to insert.  We also use it to match entries we
1263   * will be removing.  The datasheet is wrong for this.
1264   */
1265  he = (((unsigned long long) eaddr[5]) << 43) |
1266       (((unsigned long long) eaddr[4]) << 35) |
1267       (((unsigned long long) eaddr[3]) << 27) |
1268       (((unsigned long long) eaddr[2]) << 19) |
1269       (((unsigned long long) eaddr[1]) << 11) |
1270       (((unsigned long long) eaddr[0]) <<  3) |
1271       ((unsigned long long) HSH_PRIO_INS(prio) | HSH_V | HSH_R);
1272  /*   he = 0x1b1acd87d08005;*/
1273  /*
1274   * The GT will search upto 12 entries for a hit, so we must mimic that.
1275   */
1276  hash &= (sc->sc_hashmask / sizeof(he));
1277
1278#ifdef GT_DEBUG
1279  if (GTeth_debug>0) {
1280    unsigned val1, val2;
1281
1282    val1= he & 0xffffffff;
1283    val2= (he >>32) & 0xffffffff;
1284    printk("Hash addr value %x%x, entry %x\n",val2,val1, hash);
1285  }
1286#endif
1287
1288  for (limit = HSH_LIMIT; limit > 0 ; --limit) {
1289      /*
1290       * Does the GT wrap at the end, stop at the, or overrun the
1291       * end?  Assume it wraps for now.  Stash a copy of the
1292       * current hash entry.
1293       */
1294      unsigned long long *he_p = &sc->sc_hashtable[hash];
1295      unsigned long long thishe = *he_p;
1296
1297      /*
1298       * If the hash entry isn't valid, that break the chain.  And
1299       * this entry a good candidate for reuse.
1300       */
1301      if ((thishe & HSH_V) == 0) {
1302         maybe_he_p = he_p;
1303         break;
1304      }
1305
1306      /*
1307       * If the hash entry has the same address we are looking for
1308       * then ...  if we are removing and the skip bit is set, its
1309       * already been removed.  if are adding and the skip bit is
1310       * clear, then its already added.  In either return EBUSY
1311       * indicating the op has already been done.  Otherwise flip
1312       * the skip bit and return 0.
1313       */
1314      if (((he ^ thishe) & HSH_ADDR_MASK) == 0) {
1315         if (((op == GE_HASH_REMOVE) && (thishe & HSH_S)) ||
1316            ((op == GE_HASH_ADD) && (thishe & HSH_S) == 0))
1317            return EBUSY;
1318          *he_p = thishe ^ HSH_S;
1319
1320          if (GTeth_debug>0) {
1321             unsigned val1, val2;
1322
1323             val1= *he_p & 0xffffffff;
1324             val2= (*he_p >>32) & 0xffffffff;
1325             printk("flip skip bit result %x%x entry %x ",val2,val1, hash);
1326          }
1327          return 0;
1328       }
1329
1330       /*
1331        * If we haven't found a slot for the entry and this entry
1332        * is currently being skipped, return this entry.
1333        */
1334       if (maybe_he_p == NULL && (thishe & HSH_S)) {
1335          maybe_he_p = he_p;
1336          maybe_hash = hash;
1337       }               
1338       hash = (hash + 1) & (sc->sc_hashmask / sizeof(he));
1339  }
1340
1341  /*
1342   * If we got here, then there was no entry to remove.
1343   */
1344  if (op == GE_HASH_REMOVE) {
1345     printk("GT64260eth : No entry to remove\n");
1346     return ENOENT;
1347  }
1348
1349  /*
1350   * If we couldn't find a slot, return an error.
1351   */
1352  if (maybe_he_p == NULL) {
1353     rtems_panic("GT64260eth : No slot found");
1354     return ENOSPC;
1355  }
1356
1357  /* Update the entry.*/
1358  *maybe_he_p = he;
1359  if (GTeth_debug>0) {
1360    unsigned val1, val2;
1361#if 0
1362    unsigned long *pt= sc->sc_hashtable;
1363    int i, loop;
1364
1365  for (loop= 0; loop< 256; loop++) {
1366    printk("%d)", loop);
1367    for (i=0; i< 16; i++, pt++) printk("%x ",*pt);
1368    printk("\n");
1369  }
1370#endif
1371    val1= he & 0xffffffff;
1372    val2= (he >>32) & 0xffffffff;
1373    printk("Update Hash result %x%x, table addr %x entry %x )\n",val2, val1, maybe_he_p, hash);
1374  }
1375  return 0;
1376}
1377
1378static int GTeth_hash_fill(struct GTeth_softc *sc)
1379{
1380  struct ether_multistep step;
1381  struct ether_multi *enm;
1382  int error;
1383
1384#ifdef GT_DEBUG
1385  printk( "GTeth_hash_fill(");
1386#endif
1387  error = GTeth_hash_entry_op(sc,GE_HASH_ADD,GE_RXPRIO_HI,sc->arpcom.ac_enaddr);
1388
1389  if (error) {
1390     if (GTeth_debug>0) printk("!");
1391     return error;
1392  }
1393
1394  sc->sc_flags &= ~GE_ALLMULTI;
1395  if ((sc->arpcom.ac_if.if_flags & IFF_PROMISC) == 0)
1396     sc->sc_pcr &= ~ETH_EPCR_PM;
1397  /* see lib/include/netinet/if_ether.h */
1398  ETHER_FIRST_MULTI(step, &sc->arpcom, enm);
1399  while (enm != NULL) {
1400    if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
1401      /* Frames are received regardless of their destinatin address */
1402       sc->sc_flags |= GE_ALLMULTI;
1403       sc->sc_pcr |= ETH_EPCR_PM;
1404    } else {
1405      /* Frames are only received if the destinatin address is found
1406       * in the hash table
1407       */
1408       error = GTeth_hash_entry_op(sc, GE_HASH_ADD,
1409             GE_RXPRIO_MEDLO, enm->enm_addrlo);
1410       if (error == ENOSPC) break;
1411    }
1412    ETHER_NEXT_MULTI(step, enm);
1413  }
1414#ifdef GT_DEBUG
1415  printk(")\n");
1416#endif
1417  return error;
1418}
1419
1420static void GTeth_hash_init(struct GTeth_softc *sc)
1421{
1422  void *hash_mem;
1423
1424  if (GTeth_debug>0) printk("GTeth_hash_init(");
1425  /* MOTLoad defualt : 512 bytes of address filtering, which
1426   * requires 16KB of memory
1427   */
1428#if 1
1429  hash_mem = rtems_bsdnet_malloc(HASH_DRAM_SIZE + HASH_ALIGN, M_FREE, M_NOWAIT);
1430  sc->sc_hashtable  =(void *)(((long)hash_mem+ HASH_ALIGN) & ~HASH_ALIGN);
1431#else
1432  /* only for test */
1433  hash_mem = 0x68F000;
1434  sc->sc_hashtable  =(unsigned long long *)hash_mem;
1435#endif
1436  sc->sc_hashmask = HASH_DRAM_SIZE - 1;
1437
1438  memset((void *)sc->sc_hashtable, 0,HASH_DRAM_SIZE);
1439#ifdef GT_DEBUG
1440  printk("hashtable addr:%x, mask %x)\n", sc->sc_hashtable,sc->sc_hashmask);
1441#endif
1442}
1443
1444static void GT64260eth_error(struct GTeth_softc *sc)
1445{
1446  struct ifnet          *ifp = &sc->arpcom.ac_if;
1447  unsigned int          intr_status= sc->intr_errsts[sc->intr_err_ptr1];
1448
1449  /* read and reset the status; because this is written
1450   * by the ISR, we must disable interrupts here
1451   */
1452  if (intr_status) {
1453    printk("%s%d: ICR = 0x%x ", 
1454           ifp->if_name, ifp->if_unit, intr_status);
1455#if 1
1456    if (intr_status & INTR_RX_ERROR) {
1457       printk("Rxq error, if_ierrors %d\n",
1458              ifp->if_ierrors);
1459    }
1460#endif
1461    /* Rx error is handled in GT64260eth_rx() */
1462    if (intr_status & INTR_TX_ERROR) {
1463       ifp->if_oerrors++;
1464       printk("Txq error,  if_oerrors %d\n",ifp->if_oerrors);
1465    }
1466  }
1467  else 
1468    printk("%s%d: Ghost interrupt ?\n",ifp->if_name,
1469           ifp->if_unit);
1470  sc->intr_errsts[sc->intr_err_ptr1++]=0; 
1471  sc->intr_err_ptr1 %= INTR_ERR_SIZE;   /* Till Straumann */
1472}
1473
1474
1475/* The daemon does all of the work; RX, TX and cleaning up buffers/descriptors */
1476static void GT64260eth_daemon(void *arg)
1477{
1478  struct GTeth_softc *sc = (struct GTeth_softc*)arg;
1479  rtems_event_set       events;
1480  struct mbuf   *m=0;
1481  struct ifnet  *ifp=&sc->arpcom.ac_if;
1482
1483#if 0   
1484  /* see comments in GT64260eth_init(); in newer versions of
1485   * rtems, we hold the network semaphore at this point
1486   */
1487  rtems_semaphore_release(sc->daemonSync);
1488#endif
1489
1490  /* NOTE: our creator possibly holds the bsdnet_semaphore.
1491   *       since that has PRIORITY_INVERSION enabled, our
1492   *       subsequent call to bsdnet_event_receive() will
1493   *       _not_ release it. It's still in posession of our
1494   *       owner.
1495   *       This is different from how killing this task
1496   *       is handled.
1497   */
1498
1499  for (;;) {
1500     /* sleep until there's work to be done */
1501     /* Note: bsdnet_event_receive() acquires
1502      *       the global bsdnet semaphore for
1503      *       mutual exclusion.
1504      */
1505     rtems_bsdnet_event_receive(ALL_EVENTS,
1506                                RTEMS_WAIT | RTEMS_EVENT_ANY,
1507                                RTEMS_NO_TIMEOUT,
1508                                &events);
1509 
1510     if (KILL_EVENT & events) break;
1511
1512#ifndef GE_NORX
1513     if (events & RX_EVENT) GT64260eth_rx(sc);
1514#endif
1515#if 0
1516     printk("%x ", inb(ETH0_EPSR));
1517     if ( ((i++) % 15)==0) printk("\n");
1518#endif
1519
1520     /* clean up and try sending packets */
1521     do { 
1522#if 0
1523        if (gpp_int_error!=0) {
1524           printk("GPP interrupt error %d\n", gpp_int_error);
1525           gpp_int_error=0;
1526        }
1527#endif
1528         if (sc->txq_nactive) GTeth_txq_done(sc);
1529
1530         while (sc->txq_free>0) {
1531           if (sc->txq_free>TXQ_HiLmt_OFF) {
1532              m=0;
1533              IF_DEQUEUE(&ifp->if_snd,m);
1534              if (m==0) break;
1535              GT64260eth_sendpacket(sc, m); 
1536           }
1537           else {
1538              GTeth_txq_done(sc);
1539              break;
1540           }
1541         }
1542         /* we leave this loop
1543          *  - either because there's no free buffer
1544          *    (m=0 initializer && !sc->txq_free)
1545          *  - or there's nothing to send (IF_DEQUEUE
1546          *    returned 0
1547          */
1548       } while (m);
1549
1550       ifp->if_flags &= ~IFF_OACTIVE;
1551
1552       /* Log errors and other uncommon events. */
1553       if (events & ERR_EVENT) GT64260eth_error(sc); 
1554  } /* end for(;;) { rtems_bsdnet_event_receive() .....*/
1555
1556  ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
1557
1558  /* shut down the hardware */
1559  GT64260eth_stop_hw(sc);
1560  /* flush the output queue */
1561  for (;;) {
1562      IF_DEQUEUE(&ifp->if_snd,m);
1563      if (!m) break;
1564      m_freem(m);
1565  }
1566  /* as of 'rtems_bsdnet_event_receive()' we own the
1567   * networking semaphore
1568   */
1569  rtems_bsdnet_semaphore_release();
1570  rtems_semaphore_release(sc->daemonSync);
1571
1572  /* Note that I dont use sc->daemonTid here -
1573   * theoretically, that variable could already
1574   * hold a newly created TID
1575   */
1576  rtems_task_delete(RTEMS_SELF);
1577}
1578
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