source: rtems/c/src/lib/libbsp/powerpc/mvme5500/irq/irq_init.c @ cf599996

4.9
Last change on this file since cf599996 was cf599996, checked in by Joel Sherrill <joel.sherrill@…>, on May 8, 2009 at 6:22:51 PM

2009-05-08 Kate Feng <feng1@…>

PR1395/bsps

  • Updated the changes from RTEMS-4.8.0, which were made since Oct. 2007.
  • network/if_1GHz/if_wm.c: fixed some bugs in the 1GHz driver.
  • pci/pci_interface.c: + Enabled PCI "Read", "Read Line", and "Read Multiple" + Agressive Prefetch to improve the performance of the PCI based

applications (e.g. 1GHz NIC).

  • irq/BSP_irq.c : Replaced the irq/irq.c, and used GT_GPP_Value register to monitor the cause of the level sensitive interrupts. This unique solution solves various bugs in the 1GHz network drivers Fixed bugs in compute_pic_masks_from_prio()
  • pci/pci.c : Updated it to be consistent with the original pci.c
  • written by Eric Valette. There is no change in its function.
  • irq/irq_init.c : set defaultIrq->next_handler to be 0
  • for BSP_SHARED_HANDLER_SUPPORT.
  • Property mode set to 100644
File size: 4.5 KB
Line 
1/* irq_init.c
2 *
3 * This file contains the implementation of rtems initialization
4 * related to interrupt handling.
5 *
6 * CopyRight (C) 1999 valette@crf.canon.fr
7 *
8 * Modified and added support for the MVME5500.
9 * Copyright 2003, 2004, 2005, Brookhaven National Laboratory and
10 *                 Shuchen Kate Feng <feng1@bnl.gov>
11 *
12 * The license and distribution terms for this file may be
13 * found in the file LICENSE in this distribution or at
14 * http://www.rtems.com/license/LICENSE
15 *
16 */
17#include <libcpu/io.h>
18#include <libcpu/spr.h>
19#include <bsp/irq.h>
20#include <bsp.h>
21#include <libcpu/raw_exception.h>  /* ASM_EXT_VECTOR, ASM_DEC_VECTOR ... */
22/*#define  TRACE_IRQ_INIT*/
23
24/*
25 * default on/off function
26 */
27static void nop_func(void){}
28/*
29 * default isOn function
30 */
31static int not_connected(void) {return 0;}
32/*
33 * default possible isOn function
34 */
35static int connected(void) {return 1;}
36
37static rtems_irq_connect_data           rtemsIrq[BSP_IRQ_NUMBER];
38static rtems_irq_global_settings        initial_config;
39
40#ifdef BSP_SHARED_HANDLER_SUPPORT
41static rtems_irq_connect_data           defaultIrq = {
42  /* vectorIdex,  hdl       ,handle  , on       , off      , isOn      ,next_handler, */
43  0,              nop_func  , NULL   , nop_func , nop_func , not_connected, 0
44};
45#else
46static rtems_irq_connect_data           defaultIrq = {
47  /* vectorIdex,         hdl      , handle      , on            , off           , isOn */
48  0,                     nop_func  , NULL       , nop_func      , nop_func      , not_connected
49};
50#endif
51
52rtems_irq_prio BSPirqPrioTable[BSP_PIC_IRQ_NUMBER]={
53  /*
54   * This table is where the developers can change the levels of priority
55   * based on the need of their applications.
56   *
57   * actual priorities for CPU MAIN and GPP interrupts (0-95)
58   *
59   *    0   means that only current interrupt is masked (lowest priority)
60   *    255 is only used by bits 24, 25, 26 and 27 of the CPU high
61   *        interrupt Mask: (e.g. GPP7_0, GPP15_8, GPP23_16, GPP31_24).
62   *        The IRQs of those four bits are always enabled. When it's used,
63   *        the IRQ number is never listed in the dynamic picIsrTable[96].
64   *
65   *        The priorities of GPP interrupts were decided by their own
66   *        value set at  BSPirqPrioTable.
67   *           
68   */
69  /* CPU Main cause low interrupt */
70  /* 0-15 */
71  0, 0, 0, 0, 0, 0, 0, 0, 64/*Timer*/, 0, 0, 0, 0, 0, 0, 0,
72   /* 16-31 */
73  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
74  /* CPU Main cause high interrupt */
75  /* 32-47 */
76  2/*10/100MHZ*/, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
77  /* 48-63 */
78  0, 0, 0, 0, 0, 0, 0, 0, 
79  255 /*GPP0-7*/, 255/*GPP8-15*/, 255/*GPP16-23*/, 255/*GPP24-31*/, 0, 0, 0, 0,
80  /* GPP interrupts */
81  /* GPP0-7 */
82  1/*serial*/,0, 0, 0, 0, 0, 0, 0,
83  /* GPP8-15 */
84  47/*PMC1A*/,46/*PMC1B*/,45/*PMC1C*/,44/*PMC1D*/,30/*VME0*/, 29/*VME1*/,3,1,
85  /* GPP16-23 */
86  37/*PMC2A*/,36/*PMC2B*/,35/*PMC2C*/,34/*PMC2D*/,23/*1GHZ*/, 0,0,0, 
87  /* GPP24-31 */
88  7/*watchdog*/, 0,0,0,0,0,0,0
89};
90
91/*
92 * This code assumes the exceptions management setup has already
93 * been done. We just need to replace the exceptions that will
94 * be handled like interrupt. On MPC7455 and many PPC processors
95 * this means the decrementer exception and the external exception.
96 */
97void BSP_rtems_irq_mng_init(unsigned cpuId)
98{
99  int                   i;
100  rtems_interrupt_level l;
101
102  /*
103   * First initialize the Interrupt management hardware
104   */
105#ifdef TRACE_IRQ_INIT 
106  printk("Initializing the interrupt controller of the GT64260\n");
107#endif       
108
109#ifdef TRACE_IRQ_INIT 
110  printk("Going to re-initialize the rtemsIrq table %d\n",BSP_IRQ_NUMBER);
111#endif       
112  /*
113   * Initialize Rtems management interrupt table
114   */
115  /*
116   * re-init the rtemsIrq table
117   */
118  for (i = 0; i < BSP_IRQ_NUMBER; i++) {
119    rtemsIrq[i]      = defaultIrq;   
120    rtemsIrq[i].name = i;
121  }
122
123  /*
124   * Init initial Interrupt management config
125   */
126  initial_config.irqNb  = BSP_IRQ_NUMBER;
127  initial_config.defaultEntry   = defaultIrq;
128  initial_config.irqHdlTbl      = rtemsIrq;
129  initial_config.irqBase        = BSP_LOWEST_OFFSET;
130  initial_config.irqPrioTbl     = BSPirqPrioTable;
131
132#ifdef TRACE_IRQ_INIT 
133  printk("Going to setup irq mngt configuration\n");
134#endif       
135
136  rtems_interrupt_disable(l);
137  if (!BSP_rtems_irq_mngt_set(&initial_config)) {
138      /*
139       * put something here that will show the failure...
140       */
141      BSP_panic("Unable to initialize RTEMS interrupt Management!!! System locked\n");
142  }
143#ifdef TRACE_IRQ_INIT 
144  printk("Done setup irq mngt configuration\n");
145#endif
146
147#ifdef TRACE_IRQ_INIT 
148  printk("RTEMS IRQ management is now operationnal\n");
149#endif
150}
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