source: rtems/c/src/lib/libbsp/powerpc/mvme5500/irq/irq_init.c @ 7a6a9a7

4.104.114.84.95
Last change on this file since 7a6a9a7 was 7a6a9a7, checked in by Eric Norum <WENorum@…>, on 11/15/04 at 01:24:57

Updated version of previous patch.
  • Property mode set to 100644
File size: 8.4 KB
Line 
1/* irq_init.c
2 *
3 * This file contains the implementation of rtems initialization
4 * related to interrupt handling.
5 *
6 * CopyRight (C) 1999 valette@crf.canon.fr
7 *
8 * Special acknowledgement to Till Straumann <strauman@slac.stanford.edu>
9 * for providing inputs to the IRQ optimization.
10 *
11 * Modified and added support for the MVME5500.
12 * Copyright 2003, 2004, Brookhaven National Laboratory and
13 *                 Shuchen Kate Feng <feng1@bnl.gov>
14 *
15 * The license and distribution terms for this file may be
16 * found in the file LICENSE in this distribution or at
17 * http://www.OARcorp.com/rtems/license.html.
18 *
19 */
20#include <libcpu/io.h>
21#include <libcpu/spr.h>
22#include <bsp/irq.h>
23#include <bsp.h>
24#include <libcpu/raw_exception.h>  /* ASM_EXT_VECTOR, ASM_DEC_VECTOR ... */
25
26extern unsigned int external_exception_vector_prolog_code_size[];
27extern void external_exception_vector_prolog_code();
28extern unsigned int decrementer_exception_vector_prolog_code_size[];
29extern void decrementer_exception_vector_prolog_code();
30extern void GT_GPP_IntHandler0(), GT_GPP_IntHandler1();
31extern void GT_GPP_IntHandler2(), GT_GPP_IntHandler3();
32extern void BSP_GT64260INT_init();
33
34/*
35 * default on/off function
36 */
37static void nop_func(){}
38/*
39 * default isOn function
40 */
41static int not_connected() {return 0;}
42/*
43 * default possible isOn function
44 */
45static int connected() {return 1;}
46
47static rtems_irq_connect_data           rtemsIrq[BSP_IRQ_NUMBER];
48static rtems_irq_global_settings        initial_config;
49static rtems_irq_connect_data           defaultIrq = {
50  /* vectorIdex,         hdl            , on            , off           , isOn */
51  0,                     nop_func       , nop_func      , nop_func      , not_connected
52};
53
54rtems_irq_prio BSPirqPrioTable[BSP_MAIN_IRQ_NUMBER]={
55  /*
56   * This table is where the developers can change the levels of priority
57   * based on the need of their applications.
58   *
59   * actual priorities for CPU MAIN interrupts 0-63:
60   *    0   means that only current interrupt is masked (lowest priority)
61   *    255 means all other interrupts are masked
62   */
63  /* CPU Main cause low interrupt */
64  /* 0-15 */
65  0, 0, 0, 0, 0, 0, 0, 0, 4/*Timer*/, 0, 0, 0, 0, 0, 0, 0,
66   /* 16-31 */
67  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
68  /* CPU Main cause high interrupt */
69  /* 32-47 */
70  1/*10/100MHZ*/, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
71  /* 48-63 */
72  0, 0, 0, 0, 0, 0, 0, 0, 0/*serial*/, 3/*VME*/, 2/*1GHZ*/, 5/*WD*/, 0, 0, 0, 0
73};
74
75/* The mainIrqTbl[64] lists the enabled CPU main interrupt
76 * numbers [0-63] starting from the highest priority one
77 * to the lowest priority one.
78 *
79 * The highest priority interrupt is located at mainIrqTbl[0], and
80 * the lowest priority interrupt is located at
81 * mainIrqTbl[MainIrqTblPtr-1].
82 */
83
84#if DynamicIrqTbl
85/* The mainIrqTbl[64] is updated dynamically based on the priority
86 * levels set at BSPirqPrioTable[64], as the BSP_enable_main_irq() and
87 * BSP_disable_main_irq() commands are invoked.
88 *
89 * Caveat: The eight GPP IRQs for each BSP_MAIN_GPPx_y_IRQ group are set
90 * at the same main priority in the BSPirqPrioTable, while the
91 * sub-priority levels for the eight GPP in each group  are sorted
92 * statically by developers in the GPPx_yIrqTbl[8] from the highest
93 * priority to the lowest one.
94 */
95int MainIrqTblPtr=0;
96unsigned long long MainIrqInTbl=0;
97unsigned char GPPinMainIrqTbl[4]={0,0,0,0};
98/* BitNums for Main Interrupt Lo/High Cause, -1 means invalid bit */
99unsigned int mainIrqTbl[BSP_MAIN_IRQ_NUMBER]={ 
100                               -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
101                               -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
102                               -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
103                               -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
104                               -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
105                               -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
106                               -1, -1, -1, -1};
107#else
108/* Pre-sorted for IRQ optimization, and prioritization
109 * The interrupts sorted are :
110
111 1. Watchdog timer      (GPP #25)
112 2. Timers 0-1          (Main interrupt low cause, bit 8)
113 3. VME interrupt       (GPP #12)
114 4. 1 GHZ ethernet      (GPP #20)
115 5. 10/100 MHZ ethernet (Main interrupt high cause, bit 0)
116 6. COM1/COM2           (GPP #0)
117
118*/
119/* BitNums for Main Interrupt Lo/High Cause, -1 means invalid bit */
120unsigned int mainIrqTbl[64]={ BSP_MAIN_GPP31_24_IRQ, /* 59:watchdog timer */
121                               BSP_MAIN_TIMER0_1_IRQ, /* 8:Timers 0-1 */
122                               BSP_MAIN_GPP15_8_IRQ,  /* 57:VME interrupt */
123                               BSP_MAIN_GPP23_16_IRQ, /* 58: 1 GHZ ethernet */
124                               BSP_MAIN_ETH0_IRQ,  /* 32:10/100 MHZ ethernet */
125                               BSP_MAIN_GPP7_0_IRQ, /* 56:COM1/COM2 */
126                               -1, -1, -1, -1,
127                               -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
128                               -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
129                               -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
130                               -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
131                               -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
132                               -1, -1, -1, -1};
133#endif
134
135unsigned int GPP7_0IrqTbl[8]={0, /* COM1/COM2 */
136                               -1, -1, -1, -1, -1, -1, -1};
137unsigned int GPP15_8IrqTbl[8]={ 4, 5, 6, 7,  /* VME interrupt 0-3 */
138                                0, 1, 2, 3   /* PMC1 INT A, B, C, D */};
139unsigned int GPP23_16IrqTbl[8]={4, /* 82544 1GHZ ethernet (20-16=4)*/
140                                0, 1, 2, 3, /* PMC2 INT A, B, C, D */
141                                -1, -1, -1};
142unsigned int GPP31_24IrqTbl[8]={1, /* watchdog timer (25-24=1) */
143                                -1, -1, -1, -1, -1, -1, -1};
144
145static int
146doit(unsigned intNum, rtems_irq_hdl handler, int (*p)(const rtems_irq_connect_data*))
147{
148        rtems_irq_connect_data d={0};
149        d.name = intNum;
150        d.isOn = connected;
151        d.hdl  = handler;
152        return p(&d);
153}
154
155int BSP_GT64260_install_isr(unsigned intNum,rtems_irq_hdl handler)
156{
157  return doit(intNum, handler, BSP_install_rtems_irq_handler);
158}
159
160/*
161 * This code assumes the exceptions management setup has already
162 * been done. We just need to replace the exceptions that will
163 * be handled like interrupt. On MPC7455 and many PPC processors
164 * this means the decrementer exception and the external exception.
165 */
166void BSP_rtems_irq_mng_init(unsigned cpuId)
167{
168  rtems_raw_except_connect_data vectorDesc;
169  int i;
170
171  /*
172   * First initialize the Interrupt management hardware
173   */
174#ifdef TRACE_IRQ_INIT 
175  printk("Initializing the interrupt controller of the GT64260\n");
176#endif       
177  BSP_GT64260INT_init();
178
179#ifdef TRACE_IRQ_INIT 
180  printk("Going to re-initialize the rtemsIrq table %d\n",BSP_IRQ_NUMBER);
181#endif       
182  /*
183   * Initialize Rtems management interrupt table
184   */
185  /*
186   * re-init the rtemsIrq table
187   */
188  for (i = 0; i < BSP_IRQ_NUMBER; i++) {
189      rtemsIrq[i]      = defaultIrq;
190      rtemsIrq[i].name = i;
191  }
192
193  /*
194   * Init initial Interrupt management config
195   */
196  initial_config.irqNb  = BSP_IRQ_NUMBER;
197  initial_config.defaultEntry   = defaultIrq;
198  initial_config.irqHdlTbl      = rtemsIrq;
199  initial_config.irqBase        = BSP_ASM_IRQ_VECTOR_BASE;
200  initial_config.irqPrioTbl     = BSPirqPrioTable;
201
202#ifdef TRACE_IRQ_INIT 
203  printk("Going to setup irq mngt configuration\n");
204#endif       
205
206  if (!BSP_rtems_irq_mngt_set(&initial_config)) {
207      /*
208       * put something here that will show the failure...
209       */
210      BSP_panic("Unable to initialize RTEMS interrupt Management!!! System locked\n");
211  }
212
213  /* Connect the GPP int handler to each of the associated main cause bits */
214  BSP_GT64260_install_isr(BSP_MAIN_GPP7_0_IRQ, GT_GPP_IntHandler0); /* COM1 & COM2, .... */
215  BSP_GT64260_install_isr(BSP_MAIN_GPP15_8_IRQ, GT_GPP_IntHandler1);
216  BSP_GT64260_install_isr(BSP_MAIN_GPP23_16_IRQ, GT_GPP_IntHandler2);
217  BSP_GT64260_install_isr(BSP_MAIN_GPP31_24_IRQ, GT_GPP_IntHandler3);
218 
219  /*
220   * We must connect the raw irq handler for the two
221   * expected interrupt sources : decrementer and external interrupts.
222   */
223  vectorDesc.exceptIndex        = ASM_DEC_VECTOR;
224  vectorDesc.hdl.vector = ASM_DEC_VECTOR;
225  vectorDesc.hdl.raw_hdl        = decrementer_exception_vector_prolog_code;
226  vectorDesc.hdl.raw_hdl_size   = (unsigned) decrementer_exception_vector_prolog_code_size;
227  vectorDesc.on         = nop_func;
228  vectorDesc.off                = nop_func;
229  vectorDesc.isOn               = connected;
230  if (!mpc60x_set_exception (&vectorDesc)) {
231      BSP_panic("Unable to initialize RTEMS decrementer raw exception\n");
232  }
233  vectorDesc.exceptIndex        = ASM_EXT_VECTOR;
234  vectorDesc.hdl.vector = ASM_EXT_VECTOR;
235  vectorDesc.hdl.raw_hdl        = external_exception_vector_prolog_code;
236  vectorDesc.hdl.raw_hdl_size   = (unsigned) external_exception_vector_prolog_code_size;
237  if (!mpc60x_set_exception (&vectorDesc)) {
238      BSP_panic("Unable to initialize RTEMS external raw exception\n");
239    }
240#ifdef TRACE_IRQ_INIT 
241  printk("RTEMS IRQ management is now operationnal\n");
242#endif
243}
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