[7be6ad9] | 1 | /* irq_init.c |
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| 2 | * |
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| 3 | * This file contains the implementation of rtems initialization |
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| 4 | * related to interrupt handling. |
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| 5 | * |
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| 6 | * CopyRight (C) 1999 valette@crf.canon.fr |
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| 7 | * |
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| 8 | * Special acknowledgement to Till Straumann <strauman@slac.stanford.edu> |
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| 9 | * for providing inputs to the IRQ optimization. |
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| 10 | * |
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| 11 | * Modified and added support for the MVME5500. |
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| 12 | * Copyright 2003, 2004, Brookhaven National Laboratory and |
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| 13 | * Shuchen Kate Feng <feng1@bnl.gov> |
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| 14 | * |
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| 15 | * The license and distribution terms for this file may be |
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| 16 | * found in the file LICENSE in this distribution or at |
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[7ef0876] | 17 | * http://www.rtems.com/license/LICENSE. |
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[7a6a9a7] | 18 | * |
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[7be6ad9] | 19 | */ |
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| 20 | #include <libcpu/io.h> |
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| 21 | #include <libcpu/spr.h> |
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| 22 | #include <bsp/irq.h> |
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| 23 | #include <bsp.h> |
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| 24 | #include <libcpu/raw_exception.h> /* ASM_EXT_VECTOR, ASM_DEC_VECTOR ... */ |
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| 25 | |
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| 26 | extern unsigned int external_exception_vector_prolog_code_size[]; |
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| 27 | extern void external_exception_vector_prolog_code(); |
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| 28 | extern unsigned int decrementer_exception_vector_prolog_code_size[]; |
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| 29 | extern void decrementer_exception_vector_prolog_code(); |
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| 30 | extern void GT_GPP_IntHandler0(), GT_GPP_IntHandler1(); |
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| 31 | extern void GT_GPP_IntHandler2(), GT_GPP_IntHandler3(); |
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| 32 | extern void BSP_GT64260INT_init(); |
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| 33 | |
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| 34 | /* |
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| 35 | * default on/off function |
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| 36 | */ |
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| 37 | static void nop_func(){} |
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| 38 | /* |
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| 39 | * default isOn function |
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| 40 | */ |
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| 41 | static int not_connected() {return 0;} |
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| 42 | /* |
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| 43 | * default possible isOn function |
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| 44 | */ |
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| 45 | static int connected() {return 1;} |
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| 46 | |
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| 47 | static rtems_irq_connect_data rtemsIrq[BSP_IRQ_NUMBER]; |
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| 48 | static rtems_irq_global_settings initial_config; |
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| 49 | static rtems_irq_connect_data defaultIrq = { |
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[4953659b] | 50 | /* vectorIdex, hdl , handle , on , off , isOn */ |
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| 51 | 0, nop_func , NULL , nop_func , nop_func , not_connected |
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[7be6ad9] | 52 | }; |
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| 53 | |
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| 54 | rtems_irq_prio BSPirqPrioTable[BSP_MAIN_IRQ_NUMBER]={ |
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| 55 | /* |
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| 56 | * This table is where the developers can change the levels of priority |
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| 57 | * based on the need of their applications. |
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| 58 | * |
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| 59 | * actual priorities for CPU MAIN interrupts 0-63: |
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| 60 | * 0 means that only current interrupt is masked (lowest priority) |
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| 61 | * 255 means all other interrupts are masked |
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| 62 | */ |
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| 63 | /* CPU Main cause low interrupt */ |
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| 64 | /* 0-15 */ |
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| 65 | 0, 0, 0, 0, 0, 0, 0, 0, 4/*Timer*/, 0, 0, 0, 0, 0, 0, 0, |
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| 66 | /* 16-31 */ |
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| 67 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
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| 68 | /* CPU Main cause high interrupt */ |
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| 69 | /* 32-47 */ |
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| 70 | 1/*10/100MHZ*/, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
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| 71 | /* 48-63 */ |
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| 72 | 0, 0, 0, 0, 0, 0, 0, 0, 0/*serial*/, 3/*VME*/, 2/*1GHZ*/, 5/*WD*/, 0, 0, 0, 0 |
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| 73 | }; |
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| 74 | |
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| 75 | /* The mainIrqTbl[64] lists the enabled CPU main interrupt |
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| 76 | * numbers [0-63] starting from the highest priority one |
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| 77 | * to the lowest priority one. |
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| 78 | * |
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| 79 | * The highest priority interrupt is located at mainIrqTbl[0], and |
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| 80 | * the lowest priority interrupt is located at |
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| 81 | * mainIrqTbl[MainIrqTblPtr-1]. |
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| 82 | */ |
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| 83 | |
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| 84 | #if DynamicIrqTbl |
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| 85 | /* The mainIrqTbl[64] is updated dynamically based on the priority |
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| 86 | * levels set at BSPirqPrioTable[64], as the BSP_enable_main_irq() and |
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| 87 | * BSP_disable_main_irq() commands are invoked. |
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| 88 | * |
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| 89 | * Caveat: The eight GPP IRQs for each BSP_MAIN_GPPx_y_IRQ group are set |
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| 90 | * at the same main priority in the BSPirqPrioTable, while the |
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| 91 | * sub-priority levels for the eight GPP in each group are sorted |
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| 92 | * statically by developers in the GPPx_yIrqTbl[8] from the highest |
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| 93 | * priority to the lowest one. |
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| 94 | */ |
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| 95 | int MainIrqTblPtr=0; |
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| 96 | unsigned long long MainIrqInTbl=0; |
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| 97 | unsigned char GPPinMainIrqTbl[4]={0,0,0,0}; |
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| 98 | /* BitNums for Main Interrupt Lo/High Cause, -1 means invalid bit */ |
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| 99 | unsigned int mainIrqTbl[BSP_MAIN_IRQ_NUMBER]={ |
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| 100 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
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| 101 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
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| 102 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
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| 103 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
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| 104 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
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| 105 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
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| 106 | -1, -1, -1, -1}; |
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| 107 | #else |
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| 108 | /* Pre-sorted for IRQ optimization, and prioritization |
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| 109 | * The interrupts sorted are : |
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| 110 | |
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| 111 | 1. Watchdog timer (GPP #25) |
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| 112 | 2. Timers 0-1 (Main interrupt low cause, bit 8) |
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| 113 | 3. VME interrupt (GPP #12) |
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| 114 | 4. 1 GHZ ethernet (GPP #20) |
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| 115 | 5. 10/100 MHZ ethernet (Main interrupt high cause, bit 0) |
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| 116 | 6. COM1/COM2 (GPP #0) |
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| 117 | |
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| 118 | */ |
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| 119 | /* BitNums for Main Interrupt Lo/High Cause, -1 means invalid bit */ |
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| 120 | unsigned int mainIrqTbl[64]={ BSP_MAIN_GPP31_24_IRQ, /* 59:watchdog timer */ |
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| 121 | BSP_MAIN_TIMER0_1_IRQ, /* 8:Timers 0-1 */ |
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| 122 | BSP_MAIN_GPP15_8_IRQ, /* 57:VME interrupt */ |
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| 123 | BSP_MAIN_GPP23_16_IRQ, /* 58: 1 GHZ ethernet */ |
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| 124 | BSP_MAIN_ETH0_IRQ, /* 32:10/100 MHZ ethernet */ |
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| 125 | BSP_MAIN_GPP7_0_IRQ, /* 56:COM1/COM2 */ |
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| 126 | -1, -1, -1, -1, |
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| 127 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
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| 128 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
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| 129 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
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| 130 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
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| 131 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
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| 132 | -1, -1, -1, -1}; |
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| 133 | #endif |
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| 134 | |
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| 135 | unsigned int GPP7_0IrqTbl[8]={0, /* COM1/COM2 */ |
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| 136 | -1, -1, -1, -1, -1, -1, -1}; |
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[7a6a9a7] | 137 | unsigned int GPP15_8IrqTbl[8]={ 4, 5, 6, 7, /* VME interrupt 0-3 */ |
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| 138 | 0, 1, 2, 3 /* PMC1 INT A, B, C, D */}; |
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| 139 | unsigned int GPP23_16IrqTbl[8]={4, /* 82544 1GHZ ethernet (20-16=4)*/ |
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| 140 | 0, 1, 2, 3, /* PMC2 INT A, B, C, D */ |
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| 141 | -1, -1, -1}; |
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[7be6ad9] | 142 | unsigned int GPP31_24IrqTbl[8]={1, /* watchdog timer (25-24=1) */ |
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| 143 | -1, -1, -1, -1, -1, -1, -1}; |
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| 144 | |
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| 145 | static int |
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| 146 | doit(unsigned intNum, rtems_irq_hdl handler, int (*p)(const rtems_irq_connect_data*)) |
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| 147 | { |
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| 148 | rtems_irq_connect_data d={0}; |
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| 149 | d.name = intNum; |
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| 150 | d.isOn = connected; |
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| 151 | d.hdl = handler; |
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| 152 | return p(&d); |
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| 153 | } |
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| 154 | |
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| 155 | int BSP_GT64260_install_isr(unsigned intNum,rtems_irq_hdl handler) |
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| 156 | { |
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| 157 | return doit(intNum, handler, BSP_install_rtems_irq_handler); |
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| 158 | } |
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| 159 | |
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| 160 | /* |
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| 161 | * This code assumes the exceptions management setup has already |
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| 162 | * been done. We just need to replace the exceptions that will |
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| 163 | * be handled like interrupt. On MPC7455 and many PPC processors |
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| 164 | * this means the decrementer exception and the external exception. |
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| 165 | */ |
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| 166 | void BSP_rtems_irq_mng_init(unsigned cpuId) |
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| 167 | { |
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| 168 | rtems_raw_except_connect_data vectorDesc; |
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| 169 | int i; |
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| 170 | |
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| 171 | /* |
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| 172 | * First initialize the Interrupt management hardware |
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| 173 | */ |
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| 174 | #ifdef TRACE_IRQ_INIT |
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| 175 | printk("Initializing the interrupt controller of the GT64260\n"); |
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| 176 | #endif |
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| 177 | BSP_GT64260INT_init(); |
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| 178 | |
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| 179 | #ifdef TRACE_IRQ_INIT |
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| 180 | printk("Going to re-initialize the rtemsIrq table %d\n",BSP_IRQ_NUMBER); |
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| 181 | #endif |
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| 182 | /* |
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| 183 | * Initialize Rtems management interrupt table |
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| 184 | */ |
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| 185 | /* |
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| 186 | * re-init the rtemsIrq table |
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| 187 | */ |
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| 188 | for (i = 0; i < BSP_IRQ_NUMBER; i++) { |
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| 189 | rtemsIrq[i] = defaultIrq; |
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| 190 | rtemsIrq[i].name = i; |
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| 191 | } |
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| 192 | |
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| 193 | /* |
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| 194 | * Init initial Interrupt management config |
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| 195 | */ |
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| 196 | initial_config.irqNb = BSP_IRQ_NUMBER; |
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| 197 | initial_config.defaultEntry = defaultIrq; |
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| 198 | initial_config.irqHdlTbl = rtemsIrq; |
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| 199 | initial_config.irqBase = BSP_ASM_IRQ_VECTOR_BASE; |
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| 200 | initial_config.irqPrioTbl = BSPirqPrioTable; |
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| 201 | |
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| 202 | #ifdef TRACE_IRQ_INIT |
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| 203 | printk("Going to setup irq mngt configuration\n"); |
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| 204 | #endif |
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| 205 | |
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| 206 | if (!BSP_rtems_irq_mngt_set(&initial_config)) { |
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| 207 | /* |
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| 208 | * put something here that will show the failure... |
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| 209 | */ |
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| 210 | BSP_panic("Unable to initialize RTEMS interrupt Management!!! System locked\n"); |
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| 211 | } |
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| 212 | |
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| 213 | /* Connect the GPP int handler to each of the associated main cause bits */ |
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| 214 | BSP_GT64260_install_isr(BSP_MAIN_GPP7_0_IRQ, GT_GPP_IntHandler0); /* COM1 & COM2, .... */ |
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| 215 | BSP_GT64260_install_isr(BSP_MAIN_GPP15_8_IRQ, GT_GPP_IntHandler1); |
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| 216 | BSP_GT64260_install_isr(BSP_MAIN_GPP23_16_IRQ, GT_GPP_IntHandler2); |
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| 217 | BSP_GT64260_install_isr(BSP_MAIN_GPP31_24_IRQ, GT_GPP_IntHandler3); |
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| 218 | |
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| 219 | /* |
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| 220 | * We must connect the raw irq handler for the two |
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| 221 | * expected interrupt sources : decrementer and external interrupts. |
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| 222 | */ |
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| 223 | vectorDesc.exceptIndex = ASM_DEC_VECTOR; |
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| 224 | vectorDesc.hdl.vector = ASM_DEC_VECTOR; |
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| 225 | vectorDesc.hdl.raw_hdl = decrementer_exception_vector_prolog_code; |
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| 226 | vectorDesc.hdl.raw_hdl_size = (unsigned) decrementer_exception_vector_prolog_code_size; |
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| 227 | vectorDesc.on = nop_func; |
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| 228 | vectorDesc.off = nop_func; |
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| 229 | vectorDesc.isOn = connected; |
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| 230 | if (!mpc60x_set_exception (&vectorDesc)) { |
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| 231 | BSP_panic("Unable to initialize RTEMS decrementer raw exception\n"); |
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| 232 | } |
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| 233 | vectorDesc.exceptIndex = ASM_EXT_VECTOR; |
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| 234 | vectorDesc.hdl.vector = ASM_EXT_VECTOR; |
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| 235 | vectorDesc.hdl.raw_hdl = external_exception_vector_prolog_code; |
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| 236 | vectorDesc.hdl.raw_hdl_size = (unsigned) external_exception_vector_prolog_code_size; |
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| 237 | if (!mpc60x_set_exception (&vectorDesc)) { |
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| 238 | BSP_panic("Unable to initialize RTEMS external raw exception\n"); |
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| 239 | } |
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| 240 | #ifdef TRACE_IRQ_INIT |
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| 241 | printk("RTEMS IRQ management is now operationnal\n"); |
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| 242 | #endif |
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| 243 | } |
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