source: rtems/c/src/lib/libbsp/powerpc/mvme5500/irq/irq.h @ d7196bf

4.8
Last change on this file since d7196bf was d7196bf, checked in by Joel Sherrill <joel.sherrill@…>, on 05/04/09 at 20:06:43

2009-04-20 Kate Feng <feng1@…>

1396/bsps

  • pci/pci.c : Updated it to be consistent with the original pci.c
  • written by Eric Valette. There is no change in its function.
  • irq/irq_init.c : set defaultIrq->next_handler to be 0
  • for BSP_SHARED_HANDLER_SUPPORT.
  • network/if_1GHz/if_wm.c : fixed some bugs in the 1GHz driver.
  • irq/BSP_irq.c : added supports for shared IRQ.
  • pci/pci_interface.c : Enabled PCI "Read", "Read Line", and "Read Multiple"
  • Agressive Prefetch to improve the performance of the PCI based
  • applications (e.g. 1GHz NIC).
  • irq/BSP_irq.c : Replaced the irq/irq.c, and used GT_GPP_Value
  • register to monitor the cause of the level sensitive interrupts.
  • This unique solution solves various bugs in the 1GHz network drivers
  • Fixed bugs in compute_pic_masks_from_prio()
  • Property mode set to 100644
File size: 5.5 KB
Line 
1/* irq.h
2 *
3 *  This include file describe the data structure and the functions implemented
4 *  by rtems to write interrupt handlers.
5 *
6 *  CopyRight (C) 1999 valette@crf.canon.fr
7 *
8 *  This code is heavilly inspired by the public specification of STREAM V2
9 *  that can be found at :
10 *
11 *      <http://www.chorus.com/Documentation/index.html> by following
12 *  the STREAM API Specification Document link.
13 *
14 *  The license and distribution terms for this file may be
15 *  found in found in the file LICENSE in this distribution or at
16 *  http://www.rtems.com/license/LICENSE.
17 *
18 * Copyright 2004, 2005 Brookhaven National Laboratory and
19 *                 Shuchen Kate Feng <feng1@bnl.gov>
20 *
21 *    - modified shared/irq/irq.h for Mvme5500 (no ISA devices/PIC)
22 *    - Discovery GT64260 interrupt controller instead of 8259.
23 *    - Added support for software IRQ priority levels.
24 *    - modified to optimize the IRQ latency and handling
25 *
26 *  $Id$
27 */
28
29#ifndef LIBBSP_POWERPC_MVME5500_IRQ_IRQ_H
30#define LIBBSP_POWERPC_MVME5500_IRQ_IRQ_H
31
32#define BSP_SHARED_HANDLER_SUPPORT      1
33
34#include <rtems/irq.h>
35
36#define BSP_ASM_IRQ_VECTOR_BASE 0x0
37
38#ifndef ASM
39
40#define OneTierIrqPrioTbl 1
41
42/*
43 * Symbolic IRQ names and related definitions.
44 */
45
46/* leave the ISA symbols in there, so we can reuse shared/irq.c
47 * Also, we start numbering PCI irqs at 16 because the OPENPIC
48 * driver relies on this when mapping irq number <-> vectors
49 * (OPENPIC_VEC_SOURCE in openpic.h)
50 */
51
52  /* See section 25.2 , Table 734 of GT64260 controller
53   * Main Interrupt Cause Low register
54   */
55#define BSP_MICL_IRQ_NUMBER           (32)
56#define BSP_MICL_IRQ_LOWEST_OFFSET    (0)
57#define BSP_MICL_IRQ_MAX_OFFSET       (BSP_MICL_IRQ_LOWEST_OFFSET + BSP_MICL_IRQ_NUMBER -1)
58  /*
59   * Main Interrupt Cause High register
60   */
61#define BSP_MICH_IRQ_NUMBER           (32)
62#define BSP_MICH_IRQ_LOWEST_OFFSET    (BSP_MICL_IRQ_MAX_OFFSET+1)
63#define BSP_MICH_IRQ_MAX_OFFSET       (BSP_MICH_IRQ_LOWEST_OFFSET + BSP_MICH_IRQ_NUMBER -1)
64 /* External GPP Interrupt assignements
65  */
66#define BSP_GPP_IRQ_NUMBER              (32)
67#define BSP_GPP_IRQ_LOWEST_OFFSET       (BSP_MICH_IRQ_MAX_OFFSET+1)
68#define BSP_GPP_IRQ_MAX_OFFSET          (BSP_GPP_IRQ_LOWEST_OFFSET + BSP_GPP_IRQ_NUMBER - 1)
69
70 /*
71  * PowerPc exceptions handled as interrupt where a rtems managed interrupt
72  * handler might be connected
73  */
74#define BSP_PROCESSOR_IRQ_NUMBER         (1)
75#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_GPP_IRQ_MAX_OFFSET + 1)
76#define BSP_PROCESSOR_IRQ_MAX_OFFSET    (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1)
77
78  /* allow a couple of vectors for VME and counter/timer irq sources etc.
79   * This is probably not needed any more.
80   */
81#define BSP_MISC_IRQ_NUMBER             (30)
82#define BSP_MISC_IRQ_LOWEST_OFFSET      (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1)
83#define BSP_MISC_IRQ_MAX_OFFSET (BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1)
84
85  /*
86   * Summary
87   */
88#define BSP_IRQ_NUMBER                  (BSP_PIC_IRQ_NUMBER + BSP_PROCESSOR_IRQ_NUMBER)
89#define BSP_MAIN_IRQ_NUMBER             (64)
90#define BSP_PIC_IRQ_NUMBER              (96)
91#define BSP_LOWEST_OFFSET               (0)
92#define BSP_MAX_OFFSET                  (BSP_LOWEST_OFFSET + BSP_IRQ_NUMBER - 1)
93
94  /* Main CPU interrupt cause (Low) */
95#define BSP_MAIN_TIMER0_1_IRQ         (BSP_MICL_IRQ_LOWEST_OFFSET+8)
96#define BSP_MAIN_PCI0_7_0             (BSP_MICL_IRQ_LOWEST_OFFSET+12)
97#define BSP_MAIN_PCI0_15_8            (BSP_MICL_IRQ_LOWEST_OFFSET+13)
98#define BSP_MAIN_PCI0_23_16           (BSP_MICL_IRQ_LOWEST_OFFSET+14)
99#define BSP_MAIN_PCI0_31_24           (BSP_MICL_IRQ_LOWEST_OFFSET+15)
100#define BSP_MAIN_PCI1_7_0             (BSP_MICL_IRQ_LOWEST_OFFSET+16)
101#define BSP_MAIN_PCI1_15_8            (BSP_MICL_IRQ_LOWEST_OFFSET+18)
102#define BSP_MAIN_PCI1_23_16           (BSP_MICL_IRQ_LOWEST_OFFSET+19)
103#define BSP_MAIN_PCI1_31_24           (BSP_MICL_IRQ_LOWEST_OFFSET+20)
104
105
106  /* Main CPU interrupt cause (High) */
107#define BSP_MAIN_ETH0_IRQ             (BSP_MICH_IRQ_LOWEST_OFFSET)
108#define BSP_MAIN_ETH1_IRQ             (BSP_MICH_IRQ_LOWEST_OFFSET+1)
109#define BSP_MAIN_ETH2_IRQ             (BSP_MICH_IRQ_LOWEST_OFFSET+2)
110#define BSP_MAIN_GPP7_0_IRQ           (BSP_MICH_IRQ_LOWEST_OFFSET+24)
111#define BSP_MAIN_GPP15_8_IRQ          (BSP_MICH_IRQ_LOWEST_OFFSET+25)
112#define BSP_MAIN_GPP23_16_IRQ         (BSP_MICH_IRQ_LOWEST_OFFSET+26)
113#define BSP_MAIN_GPP31_24_IRQ         (BSP_MICH_IRQ_LOWEST_OFFSET+27)
114
115  /* on the MVME5500, these are the GT64260B external GPP0 interrupt */
116#define BSP_PCI_IRQ_LOWEST_OFFSET       (BSP_GPP_IRQ_LOWEST_OFFSET)
117#define BSP_UART_COM2_IRQ               (BSP_GPP_IRQ_LOWEST_OFFSET)
118#define BSP_UART_COM1_IRQ               (BSP_GPP_IRQ_LOWEST_OFFSET)
119#define BSP_GPP8_IRQ_OFFSET             (BSP_GPP_IRQ_LOWEST_OFFSET+8)
120#define BSP_GPP_PMC1_INTA               (BSP_GPP8_IRQ_OFFSET)
121#define BSP_GPP16_IRQ_OFFSET          (BSP_GPP_IRQ_LOWEST_OFFSET+16)
122#define BSP_GPP24_IRQ_OFFSET          (BSP_GPP_IRQ_LOWEST_OFFSET+24)
123#define BSP_GPP_VME_VLINT0            (BSP_GPP_IRQ_LOWEST_OFFSET+12)
124#define BSP_GPP_VME_VLINT1            (BSP_GPP_IRQ_LOWEST_OFFSET+13)
125#define BSP_GPP_VME_VLINT2            (BSP_GPP_IRQ_LOWEST_OFFSET+14)
126#define BSP_GPP_VME_VLINT3            (BSP_GPP_IRQ_LOWEST_OFFSET+15)
127#define BSP_GPP_PMC2_INTA             (BSP_GPP_IRQ_LOWEST_OFFSET+16)
128#define BSP_GPP_82544_IRQ             (BSP_GPP_IRQ_LOWEST_OFFSET+20)
129#define BSP_GPP_WDT_NMI_IRQ           (BSP_GPP_IRQ_LOWEST_OFFSET+24)
130#define BSP_GPP_WDT_EXP_IRQ           (BSP_GPP_IRQ_LOWEST_OFFSET+25)
131
132 /*
133   * Some Processor execption handled as rtems IRQ symbolic name definition
134   */
135#define BSP_DECREMENTER         (BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
136
137extern void BSP_rtems_irq_mng_init(unsigned cpuId);
138
139#endif
140#endif
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