1 | /* irq.c |
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2 | * |
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3 | * This file contains the implementation of the function described in irq.h |
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4 | * |
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5 | * Copyright (C) 1998, 1999 valette@crf.canon.fr |
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6 | * |
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7 | * The license and distribution terms for this file may be |
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8 | * found in the file LICENSE in this distribution or at |
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9 | * http://www.OARcorp.com/rtems/license.html. |
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10 | * |
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11 | * Acknowledgement May 2004 : to Till Straumann <strauman@slac.stanford.edu> |
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12 | * for some inputs. |
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13 | * |
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14 | * Copyright 2003, 2004, 2005, 2007 Shuchen Kate Feng <feng1@bnl.gov>, |
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15 | * NSLS,Brookhaven National Laboratory |
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16 | * 1) Modified and added support for the MVME5500 board. |
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17 | * 2) The implementation of picIsrTable[] is an original work by the |
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18 | * author to optimize the software IRQ priority scheduling because |
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19 | * Discovery controller does not provide H/W IRQ priority schedule. |
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20 | * It ensures the fastest/faster interrupt service to the |
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21 | * highest/higher priority IRQ, if pendig. |
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22 | * 3) _CPU_MSR_SET() needs RTEMS_COMPILER_MEMORY_BARRIER() |
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23 | * |
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24 | */ |
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25 | |
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26 | #include <rtems/system.h> |
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27 | #include <bsp.h> |
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28 | #include <bsp/irq.h> |
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29 | #include <rtems/score/thread.h> |
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30 | #include <rtems/score/apiext.h> |
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31 | #include <libcpu/raw_exception.h> |
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32 | #include <rtems/rtems/intr.h> |
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33 | #include <libcpu/io.h> |
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34 | #include <libcpu/byteorder.h> |
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35 | #include <bsp/vectors.h> |
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36 | |
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37 | #include <rtems/bspIo.h> /* for printk */ |
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38 | #include "bsp/gtreg.h" |
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39 | |
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40 | #define HI_INT_CAUSE 0x40000000 |
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41 | |
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42 | #define MAX_IRQ_LOOP 30 |
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43 | |
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44 | #define EDGE_TRIGGER |
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45 | |
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46 | /* #define DEBUG_IRQ*/ |
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47 | |
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48 | /* |
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49 | * pointer to the mask representing the additionnal irq vectors |
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50 | * that must be disabled when a particular entry is activated. |
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51 | * They will be dynamically computed from the table given |
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52 | * in BSP_rtems_irq_mngt_set(); |
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53 | * CAUTION : this table is accessed directly by interrupt routine |
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54 | * prologue. |
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55 | */ |
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56 | static unsigned int BSP_irq_prio_mask_tbl[3][BSP_PIC_IRQ_NUMBER]; |
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57 | |
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58 | /* |
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59 | * location used to store initial tables used for interrupt |
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60 | * management. |
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61 | */ |
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62 | static rtems_irq_global_settings* internal_config; |
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63 | /* handler table (cached copy ) */ |
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64 | static rtems_irq_connect_data* rtems_hdl_tbl; |
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65 | /* |
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66 | * default handler connected on each irq after bsp initialization |
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67 | * (locally cached copy) |
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68 | */ |
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69 | void (*default_rtems_hdl)(rtems_irq_hdl_param) = (void(*)(rtems_irq_hdl_param)) -1; |
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70 | |
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71 | |
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72 | static volatile unsigned *BSP_irqMask_reg[3]; |
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73 | static volatile unsigned *BSP_irqCause_reg[3]; |
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74 | static volatile unsigned BSP_irqMask_cache[3]={0,0,0}; |
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75 | |
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76 | |
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77 | static int picIsrTblPtr=0; |
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78 | static unsigned int GPPIrqInTbl=0; |
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79 | static unsigned long long MainIrqInTbl=0; |
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80 | |
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81 | /* |
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82 | * The software developers are forbidden to setup picIsrTable[], |
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83 | * as it is a powerful engine for the BSP to find the pending |
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84 | * highest priority IRQ at run time. It ensures the fastest/faster |
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85 | * interrupt service to the highest/higher priority IRQ, if pendig. |
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86 | * |
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87 | * The picIsrTable[96] is updated dynamically at run time |
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88 | * based on the priority levels set at BSPirqPrioTable[96], |
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89 | * while the BSP_enable_pic_irq(), and BSP_disable_pic_irq() |
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90 | * commands are invoked. |
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91 | * |
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92 | * The picIsrTable[96] lists the enabled CPU main and GPP external interrupt |
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93 | * numbers [0 (lowest)- 95 (highest)] starting from the highest priority |
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94 | * one to the lowest priority one. The highest priority interrupt is |
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95 | * located at picIsrTable[0], and the lowest priority interrupt is located |
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96 | * at picIsrTable[picIsrTblPtr-1]. |
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97 | * |
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98 | * |
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99 | */ |
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100 | /* BitNums for Main Interrupt Lo/High Cause and GPP, -1 means invalid bit */ |
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101 | static unsigned int picIsrTable[BSP_PIC_IRQ_NUMBER]={ |
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102 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
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103 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
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104 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
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105 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
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106 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
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107 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
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108 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
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109 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
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110 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
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111 | -1, -1, -1, -1, -1, -1 }; |
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112 | |
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113 | |
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114 | /* |
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115 | * Check if IRQ is a MAIN CPU internal IRQ or GPP external IRQ |
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116 | */ |
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117 | static inline int is_pic_irq(const rtems_irq_number irqLine) |
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118 | { |
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119 | return (((int) irqLine <= BSP_GPP_IRQ_MAX_OFFSET) & |
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120 | ((int) irqLine >= BSP_MICL_IRQ_LOWEST_OFFSET) |
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121 | ); |
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122 | } |
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123 | |
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124 | /* |
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125 | * Check if IRQ is a Porcessor IRQ |
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126 | */ |
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127 | static inline int is_processor_irq(const rtems_irq_number irqLine) |
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128 | { |
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129 | return (((int) irqLine <= BSP_PROCESSOR_IRQ_MAX_OFFSET) & |
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130 | ((int) irqLine >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) |
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131 | ); |
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132 | } |
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133 | |
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134 | static inline unsigned int divIrq32(unsigned irq) |
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135 | { |
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136 | return(irq/32); |
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137 | } |
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138 | |
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139 | static inline unsigned int modIrq32(unsigned irq) |
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140 | { |
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141 | return(irq%32); |
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142 | } |
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143 | |
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144 | /* |
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145 | * ------------------------ RTEMS Irq helper functions ---------------- |
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146 | */ |
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147 | |
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148 | /* |
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149 | * Caution : this function assumes the variable "internal_config" |
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150 | * is already set and that the tables it contains are still valid |
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151 | * and accessible. |
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152 | */ |
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153 | static void compute_pic_masks_from_prio(rtems_irq_global_settings *config) |
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154 | { |
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155 | int i,j, k; |
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156 | unsigned long long irq_prio_mask=0; |
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157 | |
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158 | /* |
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159 | * Always mask at least current interrupt to prevent re-entrance |
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160 | */ |
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161 | for (i=0; i <BSP_PIC_IRQ_NUMBER; i++) { |
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162 | switch(i) { |
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163 | case BSP_MAIN_GPP7_0_IRQ: |
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164 | case BSP_MAIN_GPP15_8_IRQ: |
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165 | case BSP_MAIN_GPP23_16_IRQ: |
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166 | case BSP_MAIN_GPP31_24_IRQ: |
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167 | for (k=0; k< 3; k++) |
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168 | BSP_irq_prio_mask_tbl[k][i]=0; |
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169 | |
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170 | irq_prio_mask =0; |
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171 | break; |
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172 | default : |
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173 | irq_prio_mask = (unsigned long long) (1LLU << i); |
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174 | break; |
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175 | } |
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176 | |
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177 | if (irq_prio_mask) { |
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178 | for (j = 0; j <BSP_MAIN_IRQ_NUMBER; j++) { |
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179 | /* |
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180 | * Mask interrupts at PIC level that have a lower priority |
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181 | * or <Till Straumann> a equal priority. |
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182 | */ |
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183 | if (config->irqPrioTbl [i] >= config->irqPrioTbl [j]) |
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184 | irq_prio_mask |= (unsigned long long)(1LLU << j); |
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185 | } |
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186 | |
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187 | |
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188 | BSP_irq_prio_mask_tbl[0][i] = irq_prio_mask & 0xffffffff; |
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189 | BSP_irq_prio_mask_tbl[1][i] = (irq_prio_mask>>32) & 0xffffffff; |
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190 | #ifdef DEBUG |
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191 | printk("irq_mask_prio_tbl[%d]:0x%8x%8x\n",i,BSP_irq_prio_mask_tbl[1][i], |
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192 | BSP_irq_prio_mask_tbl[0][i]); |
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193 | #endif |
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194 | |
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195 | BSP_irq_prio_mask_tbl[2][i] = 1<<i; |
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196 | /* Compute for the GPP priority interrupt mask */ |
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197 | for (j=BSP_GPP_IRQ_LOWEST_OFFSET; j <BSP_PROCESSOR_IRQ_LOWEST_OFFSET; j++) { |
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198 | if (config->irqPrioTbl [i] >= config->irqPrioTbl [j]) |
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199 | BSP_irq_prio_mask_tbl[2][i] |= 1 << (j-BSP_GPP_IRQ_LOWEST_OFFSET); |
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200 | } |
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201 | } |
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202 | } |
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203 | } |
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204 | |
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205 | |
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206 | static void UpdateMainIrqTbl(int irqNum) |
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207 | { |
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208 | int i=0, j, shifted=0; |
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209 | |
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210 | switch (irqNum) { |
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211 | case BSP_MAIN_GPP7_0_IRQ: |
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212 | case BSP_MAIN_GPP15_8_IRQ: |
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213 | case BSP_MAIN_GPP23_16_IRQ: |
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214 | case BSP_MAIN_GPP31_24_IRQ: |
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215 | return; /* Do nothing, let GPP take care of it */ |
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216 | break; |
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217 | } |
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218 | #ifdef SHOW_MORE_INIT_SETTINGS |
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219 | unsigned long val2, val1; |
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220 | #endif |
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221 | |
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222 | /* If entry not in table*/ |
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223 | if ( ((irqNum<BSP_GPP_IRQ_LOWEST_OFFSET) && |
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224 | (!((unsigned long long)(1LLU << irqNum) & MainIrqInTbl))) || |
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225 | ((irqNum>BSP_MICH_IRQ_MAX_OFFSET) && |
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226 | (!(( 1 << (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET)) & GPPIrqInTbl)))) |
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227 | { |
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228 | while ( picIsrTable[i]!=-1) { |
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229 | if (internal_config->irqPrioTbl[irqNum]>internal_config->irqPrioTbl[picIsrTable[i]]) { |
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230 | /* all other lower priority entries shifted right */ |
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231 | for (j=picIsrTblPtr;j>i; j--) |
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232 | picIsrTable[j]=picIsrTable[j-1]; |
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233 | picIsrTable[i]=irqNum; |
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234 | shifted=1; |
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235 | break; |
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236 | } |
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237 | i++; |
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238 | } |
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239 | if (!shifted) picIsrTable[picIsrTblPtr]=irqNum; |
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240 | if (irqNum >BSP_MICH_IRQ_MAX_OFFSET) |
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241 | GPPIrqInTbl |= (1<< (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET)); |
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242 | else |
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243 | MainIrqInTbl |= (unsigned long long)(1LLU << irqNum); |
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244 | picIsrTblPtr++; |
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245 | } |
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246 | #ifdef SHOW_MORE_INIT_SETTINGS |
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247 | val2 = (MainIrqInTbl>>32) & 0xffffffff; |
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248 | val1 = MainIrqInTbl&0xffffffff; |
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249 | printk("irqNum %d, MainIrqInTbl 0x%x%x\n", irqNum, val2, val1); |
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250 | BSP_printPicIsrTbl(); |
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251 | #endif |
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252 | |
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253 | } |
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254 | |
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255 | |
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256 | static void CleanMainIrqTbl(int irqNum) |
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257 | { |
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258 | int i, j; |
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259 | |
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260 | switch (irqNum) { |
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261 | case BSP_MAIN_GPP7_0_IRQ: |
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262 | case BSP_MAIN_GPP15_8_IRQ: |
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263 | case BSP_MAIN_GPP23_16_IRQ: |
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264 | case BSP_MAIN_GPP31_24_IRQ: |
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265 | return; /* Do nothing, let GPP take care of it */ |
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266 | break; |
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267 | } |
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268 | if ( ((irqNum<BSP_GPP_IRQ_LOWEST_OFFSET) && |
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269 | ((unsigned long long)(1LLU << irqNum) & MainIrqInTbl)) || |
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270 | ((irqNum>BSP_MICH_IRQ_MAX_OFFSET) && |
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271 | (( 1 << (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET)) & GPPIrqInTbl))) |
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272 | { /* If entry in table*/ |
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273 | for (i=0; i<64; i++) { |
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274 | if (picIsrTable[i]==irqNum) {/*remove it from the entry */ |
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275 | /* all other lower priority entries shifted left */ |
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276 | for (j=i;j<picIsrTblPtr; j++) |
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277 | picIsrTable[j]=picIsrTable[j+1]; |
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278 | if (irqNum >BSP_MICH_IRQ_MAX_OFFSET) |
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279 | GPPIrqInTbl &= ~(1<< (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET)); |
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280 | else |
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281 | MainIrqInTbl &= ~(1LLU << irqNum); |
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282 | picIsrTblPtr--; |
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283 | break; |
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284 | } |
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285 | } |
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286 | } |
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287 | } |
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288 | |
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289 | void BSP_enable_pic_irq(const rtems_irq_number irqNum) |
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290 | { |
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291 | unsigned bitNum, regNum; |
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292 | unsigned int level; |
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293 | |
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294 | if ( !is_pic_irq(irqNum) ) |
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295 | return; |
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296 | |
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297 | bitNum = modIrq32(((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET); |
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298 | regNum = divIrq32(((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET); |
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299 | |
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300 | rtems_interrupt_disable(level); |
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301 | |
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302 | UpdateMainIrqTbl((int) irqNum); |
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303 | BSP_irqMask_cache[regNum] |= (1 << bitNum); |
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304 | |
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305 | out_le32(BSP_irqMask_reg[regNum], BSP_irqMask_cache[regNum]); |
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306 | while (in_le32(BSP_irqMask_reg[regNum]) != BSP_irqMask_cache[regNum]); |
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307 | |
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308 | rtems_interrupt_enable(level); |
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309 | } |
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310 | |
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311 | void BSP_enable_irq_at_pic(const rtems_irq_number irqNum) |
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312 | { |
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313 | BSP_enable_pic_irq(irqNum); |
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314 | } |
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315 | |
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316 | int BSP_disable_irq_at_pic(const rtems_irq_number irqNum) |
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317 | { |
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318 | int rval; |
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319 | unsigned bitNum, regNum; |
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320 | unsigned int level; |
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321 | |
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322 | if ( ! is_pic_irq(irqNum) ) |
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323 | return -1; |
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324 | |
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325 | bitNum = modIrq32(((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET); |
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326 | regNum = divIrq32(((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET); |
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327 | |
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328 | rtems_interrupt_disable(level); |
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329 | |
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330 | CleanMainIrqTbl((int) irqNum); |
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331 | |
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332 | rval = BSP_irqMask_cache[regNum] & (1<<bitNum); |
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333 | |
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334 | BSP_irqMask_cache[regNum] &= ~(1 << bitNum); |
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335 | |
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336 | out_le32(BSP_irqMask_reg[regNum], BSP_irqMask_cache[regNum]); |
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337 | while (in_le32(BSP_irqMask_reg[regNum]) != BSP_irqMask_cache[regNum]); |
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338 | |
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339 | rtems_interrupt_enable(level); |
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340 | |
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341 | return rval ? 1 : 0; |
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342 | } |
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343 | |
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344 | void BSP_disable_pic_irq(const rtems_irq_number irqNum) |
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345 | { |
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346 | (void)BSP_disable_irq_at_pic(irqNum); |
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347 | } |
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348 | |
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349 | int BSP_setup_the_pic(rtems_irq_global_settings *config) /* adapt the same name as shared/irq */ |
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350 | { |
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351 | int i; |
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352 | |
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353 | internal_config = config; |
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354 | default_rtems_hdl = config->defaultEntry.hdl; |
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355 | rtems_hdl_tbl = config->irqHdlTbl; |
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356 | |
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357 | /* Get ready for discovery BSP */ |
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358 | BSP_irqMask_reg[0]= (volatile unsigned int *) (GT64260_REG_BASE + GT_CPU_INT_MASK_LO); |
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359 | BSP_irqMask_reg[1]= (volatile unsigned int *) (GT64260_REG_BASE + GT_CPU_INT_MASK_HI); |
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360 | BSP_irqMask_reg[2]= (volatile unsigned int *) (GT64260_REG_BASE + GT_GPP_Interrupt_Mask); |
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361 | |
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362 | BSP_irqCause_reg[0]= (volatile unsigned int *) (GT64260_REG_BASE + GT_MAIN_INT_CAUSE_LO); |
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363 | BSP_irqCause_reg[1]= (volatile unsigned int *) (GT64260_REG_BASE + GT_MAIN_INT_CAUSE_HI); |
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364 | BSP_irqCause_reg[2]= (volatile unsigned int *) (GT64260_REG_BASE + GT_GPP_Interrupt_Cause); |
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365 | |
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366 | #ifdef EDGE_TRIGGER |
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367 | |
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368 | /* Page 401, Table 598: |
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369 | * Comm Unit Arbiter Control register : |
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370 | * bit 10:GPP interrupts as level sensitive(1) or edge sensitive(0). |
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371 | * We set the GPP interrupts to be edge sensitive. |
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372 | * MOTload default is set as level sensitive(1). |
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373 | */ |
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374 | outl((inl(GT_CommUnitArb_Ctrl)& (~(1<<10))), GT_CommUnitArb_Ctrl); |
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375 | #else |
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376 | outl((inl(GT_CommUnitArb_Ctrl)| (1<<10)), GT_CommUnitArb_Ctrl); |
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377 | #endif |
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378 | |
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379 | #if 0 |
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380 | printk("BSP_irqMask_reg[0] = 0x%x, BSP_irqCause_reg[0] 0x%x\n", |
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381 | in_le32(BSP_irqMask_reg[0]), |
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382 | in_le32(BSP_irqCause_reg[0])); |
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383 | printk("BSP_irqMask_reg[1] = 0x%x, BSP_irqCause_reg[1] 0x%x\n", |
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384 | in_le32(BSP_irqMask_reg[1]), |
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385 | in_le32(BSP_irqCause_reg[1])); |
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386 | printk("BSP_irqMask_reg[2] = 0x%x, BSP_irqCause_reg[2] 0x%x\n", |
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387 | in_le32(BSP_irqMask_reg[2]), |
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388 | in_le32(BSP_irqCause_reg[2])); |
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389 | #endif |
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390 | |
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391 | /* Initialize the interrupt related GT64260 registers */ |
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392 | for (i=0; i<3; i++) { |
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393 | out_le32(BSP_irqCause_reg[i], 0); |
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394 | out_le32(BSP_irqMask_reg[i], 0); |
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395 | } |
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396 | in_le32(BSP_irqMask_reg[2]); |
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397 | compute_pic_masks_from_prio(config); |
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398 | |
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399 | #if 0 |
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400 | printk("BSP_irqMask_reg[0] = 0x%x, BSP_irqCause_reg[0] 0x%x\n", |
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401 | in_le32(BSP_irqMask_reg[0]), |
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402 | in_le32(BSP_irqCause_reg[0])); |
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403 | printk("BSP_irqMask_reg[1] = 0x%x, BSP_irqCause_reg[1] 0x%x\n", |
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404 | in_le32(BSP_irqMask_reg[1]), |
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405 | in_le32(BSP_irqCause_reg[1])); |
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406 | printk("BSP_irqMask_reg[2] = 0x%x, BSP_irqCause_reg[2] 0x%x\n", |
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407 | in_le32(BSP_irqMask_reg[2]), |
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408 | in_le32(BSP_irqCause_reg[2])); |
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409 | #endif |
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410 | |
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411 | return(1); |
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412 | } |
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413 | |
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414 | /* |
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415 | * This function check that the value given for the irq line |
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416 | * is valid. |
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417 | */ |
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418 | |
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419 | /* |
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420 | * High level IRQ handler called from shared_raw_irq_code_entry |
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421 | */ |
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422 | |
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423 | int C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned int excNum) |
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424 | { |
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425 | unsigned long irqCause[3]={0, 0,0}; |
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426 | register unsigned long selectCause; |
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427 | unsigned oldMask[3]={0,0,0}; |
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428 | register unsigned i=0, j, irq=0, bitmask=0, group=0; |
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429 | |
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430 | if (excNum == ASM_DEC_VECTOR) { |
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431 | |
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432 | bsp_irq_dispatch_list( rtems_hdl_tbl, BSP_DECREMENTER, default_rtems_hdl); |
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433 | |
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434 | return 0; |
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435 | |
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436 | } |
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437 | |
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438 | for (j=0; j<3; j++ ) oldMask[j] = BSP_irqMask_cache[j]; |
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439 | |
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440 | if ((selectCause= in_le32((volatile unsigned *)0xf1000c70)) & HI_INT_CAUSE ){ |
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441 | irqCause[1] = (selectCause & BSP_irqMask_cache[1]); |
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442 | irqCause[2] = in_le32(BSP_irqCause_reg[2]) & BSP_irqMask_cache[2]; |
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443 | } |
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444 | else { |
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445 | irqCause[0] = (selectCause & BSP_irqMask_cache[0]); |
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446 | if ((irqCause[1] =(in_le32((volatile unsigned *)0xf1000c68)&BSP_irqMask_cache[1]))) |
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447 | irqCause[2] = in_le32(BSP_irqCause_reg[2]) & BSP_irqMask_cache[2]; |
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448 | } |
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449 | |
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450 | while ((irq = picIsrTable[i++])!=-1) |
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451 | { |
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452 | if (irqCause[group=(irq/32)] && (irqCause[group]&(bitmask=(1<<(irq % 32))))) { |
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453 | for (j=0; j<3; j++) |
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454 | BSP_irqMask_cache[j] &= (~ BSP_irq_prio_mask_tbl[j][irq]); |
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455 | |
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456 | RTEMS_COMPILER_MEMORY_BARRIER(); |
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457 | out_le32((volatile unsigned *)0xf1000c1c, BSP_irqMask_cache[0]); |
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458 | out_le32((volatile unsigned *)0xf1000c6c, BSP_irqMask_cache[1]); |
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459 | out_le32((volatile unsigned *)0xf100f10c, BSP_irqMask_cache[2]); |
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460 | in_le32((volatile unsigned *)0xf100f10c); |
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461 | |
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462 | #ifdef EDGE_TRIGGER |
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463 | if (irq > BSP_MICH_IRQ_MAX_OFFSET) |
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464 | out_le32(BSP_irqCause_reg[2], ~bitmask);/* Till Straumann: Ack the edge triggered GPP IRQ */ |
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465 | #endif |
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466 | |
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467 | bsp_irq_dispatch_list( rtems_hdl_tbl, irq, default_rtems_hdl); |
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468 | |
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469 | for (j=0; j<3; j++ ) BSP_irqMask_cache[j] = oldMask[j]; |
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470 | break; |
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471 | } |
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472 | } |
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473 | |
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474 | out_le32((volatile unsigned *)0xf1000c1c, oldMask[0]); |
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475 | out_le32((volatile unsigned *)0xf1000c6c, oldMask[1]); |
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476 | out_le32((volatile unsigned *)0xf100f10c, oldMask[2]); |
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477 | in_le32((volatile unsigned *)0xf100f10c); |
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478 | |
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479 | return 0; |
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480 | } |
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481 | |
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482 | /* Only print part of the entries for now */ |
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483 | void BSP_printPicIsrTbl() |
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484 | { |
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485 | int i; |
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486 | |
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487 | printk("picIsrTable[12]={"); |
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488 | for (i=0; i<12; i++) |
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489 | printk("%d,", picIsrTable[i]); |
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490 | printk("}\n"); |
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491 | |
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492 | printk("GPPIrqInTbl: 0x%x :\n", GPPIrqInTbl); |
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493 | } |
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