source: rtems/c/src/lib/libbsp/powerpc/mvme5500/irq/GT64260Int.c @ 7be6ad9

4.104.114.84.9
Last change on this file since 7be6ad9 was 7be6ad9, checked in by Eric Norum <WENorum@…>, on Oct 20, 2004 at 3:21:05 PM

Add MVME550 BSP

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File size: 6.4 KB
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1/* GT64260Int.c - GT64260 Interrupt controller support functions
2 *
3 * Copyright 2003, 2004, Brookhaven National Laboratory and
4 *                 Shuchen Kate Feng <feng1@bnl.gov>
5 *
6 * The license and distribution terms for this file may be
7 * found in the file LICENSE in this distribution.
8 *
9 */
10#include <libcpu/io.h>
11#include <rtems/bspIo.h> /* for printk */
12
13#include "bsp/gtreg.h"
14#include "bsp/irq.h"
15
16extern rtems_irq_prio BSPirqPrioTable[BSP_MAIN_IRQ_NUMBER];
17
18rtems_GTirq_masks GT_GPPirq_cache=0; 
19rtems_GTirq_masks GT_MAINirqLO_cache=0, GT_MAINirqHI_cache=0;
20
21void BSP_GT64260INT_init()
22{
23
24    /* Page 401, Table 598:
25     * Comm Unit Arbiter Control register :
26     * bit 10:GPP interrupts as level sensitive(1) or edge sensitive(0).
27     * We set the GPP interrupts to be edge sensitive.
28     * MOTload default is set as level sensitive(1).
29     */
30    outl((inl(GT_CommUnitArb_Ctrl)& (~(1<<10))), GT_CommUnitArb_Ctrl);
31
32    /* Initialize the interrupt related GT64260 registers */
33    outl( 0, GT_CPU_INT_MASK_LO);
34    outl( 0, GT_CPU_INT_MASK_HI);
35
36    outl( 0, GT_PCI0_INT_MASK_LO);
37    outl( 0, GT_PCI0_INT_MASK_HI);
38
39
40    outl( 0, GT_PCI1_INT_MASK_LO);
41    outl( 0, GT_PCI1_INT_MASK_HI);
42 
43    outl( 0, GT_CPU_INT0_MASK);
44    outl( 0, GT_CPU_INT1_MASK);
45    outl( 0, GT_CPU_INT2_MASK);
46    outl( 0, GT_CPU_INT3_MASK);
47    outl(0, GT_GPP_Interrupt_Mask);
48    outl( 0, GT_GPP_Value);
49    outl( 0, GT_GPP_Interrupt_Cause);
50#if 0
51    printk("watchdog timer 0x%x\n",inl(0xb410));
52#endif
53}
54
55static void UpdateMainIrqTbl(int irqNum)
56{
57  int i=0, j, shifted=0, found=0;
58
59#ifdef SHOW_MORE_INIT_SETTINGS
60  unsigned long val2, val1;
61
62  val2 = (MainIrqInTbl>>32) & 0xffffffff;
63  val1 = MainIrqInTbl&0xffffffff;
64  printk("irqNum %d, MainIrqInTbl 0x%x%x\n", irqNum, val2, val1); 
65  printMainIrqTbl();
66#endif
67
68  /* If entry not in table*/
69  if ( !((unsigned long long)(1LLU << irqNum) & MainIrqInTbl)) { 
70      while ( mainIrqTbl[i]!=-1) {
71        if (BSPirqPrioTable[irqNum]>BSPirqPrioTable[mainIrqTbl[i]]) {
72          /* all other lower priority entries shifted right */
73          for (j=MainIrqTblPtr;j>i; j--) 
74              mainIrqTbl[j]=mainIrqTbl[j-1];
75          mainIrqTbl[i]=irqNum;
76          shifted=1;
77          break;
78       }
79       i++;
80     }
81     if (!shifted) mainIrqTbl[MainIrqTblPtr]=irqNum;
82     MainIrqInTbl |= (unsigned long long)(1LLU << irqNum);
83     MainIrqTblPtr++;
84  }
85}
86
87static void CleanMainIrqTbl(int irqNum)
88{
89  int i, j;
90
91  if (((1LLU << irqNum) & MainIrqInTbl)) { /* If entry in table*/
92     for (i=0; i<64; i++) {
93       if (mainIrqTbl[i]==irqNum) {/*remove it from the entry */
94          /* all other lower priority entries shifted left */
95          for (j=i;j<MainIrqTblPtr; j++) 
96              mainIrqTbl[j]=mainIrqTbl[j+1];
97          MainIrqInTbl &= ~(1LLU << irqNum);
98          MainIrqTblPtr--;
99          break;
100       }
101     }
102  }
103}
104
105/***************************************************************************
106*
107* BSP_enable_main_irq enables the corresponding bit in the low or high
108* "main cause cpu int mask register". 
109*
110*/
111void BSP_enable_main_irq(const rtems_irq_symbolic_name irqNum) 
112{
113  unsigned bitNum, mask;
114  unsigned int level;
115
116  bitNum = ((int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET;
117
118  _CPU_ISR_Disable(level); 
119
120#if DynamicIrqTbl
121  UpdateMainIrqTbl((int) irqNum);
122#endif       
123  if (bitNum <32) {
124     GT_MAINirqLO_cache |= (1 << bitNum);
125     outl(GT_MAINirqLO_cache, GT_CPU_INT_MASK_LO);
126  }
127  else {
128     bitNum-=32;
129     GT_MAINirqHI_cache |= (1 << bitNum);
130     outl(GT_MAINirqHI_cache, GT_CPU_INT_MASK_HI);
131  }
132  _CPU_ISR_Enable (level);
133}
134
135/***************************************************************************
136*
137* BSP_disable_main_irq disables the corresponding bit in the low or high
138* main cause cpu int mask register.
139*
140*/
141void BSP_disable_main_irq(const rtems_irq_symbolic_name irqNum) 
142{
143  unsigned bitNum;
144  unsigned int mask, level;
145
146  bitNum = ((int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET;
147
148  _CPU_ISR_Disable(level);
149
150#if DynamicIrqTbl
151  CleanMainIrqTbl((int) irqNum);
152#endif
153  if (bitNum <32) {
154     GT_MAINirqLO_cache &= ~(1 << bitNum);
155     outl(GT_MAINirqLO_cache, GT_CPU_INT_MASK_LO);
156  }
157  else  {
158     bitNum-=32;
159     GT_MAINirqHI_cache &= ~(1 << bitNum);
160     outl(GT_MAINirqHI_cache, GT_CPU_INT_MASK_HI);
161  }
162  _CPU_ISR_Enable (level);
163}
164
165/******************************************************************************
166*
167* BSP_enable_gpp_irq enables the corresponding bit in the GPP interrupt
168* mask register.  The interrupt level is numerically equivalent to the
169* corresponding interrupt vector.
170*
171*/
172void BSP_enable_gpp_irq(const rtems_irq_symbolic_name irqNum) 
173{
174  unsigned bitNum;
175  unsigned int mask, level;
176  int group, bit;
177
178  bitNum = ((int)irqNum) - BSP_GPP_IRQ_LOWEST_OFFSET;
179
180  _CPU_ISR_Disable(level);
181
182#if DynamicIrqTbl
183  group = bitNum/8;
184  if ( !GPPinMainIrqTbl[group])  /* avoid duplicated entry */
185     UpdateMainIrqTbl(BSP_MAIN_GPP7_0_IRQ+group);
186  bit = bitNum%8;
187  GPPinMainIrqTbl[group] |= (1<<bit);
188#endif
189 
190  mask = 1 << bitNum;
191  GT_GPPirq_cache |= mask;
192  outl(GT_GPPirq_cache, GT_GPP_Interrupt_Mask);
193#ifdef SHOW_MORE_INIT_SETTINGS
194  printk("enable irqNum %d, bitnum %d \n", irqNum, bitNum);
195  printk("GPP mask %d \n", inl(GT_GPP_Interrupt_Mask)); 
196#endif
197
198  _CPU_ISR_Enable (level);
199}
200
201/******************************************************************************
202*
203* BSP_disable_gpp_irq disables the corresponding bit in the General Purpose
204* Port Interrupt.  The interrupt level is numerically equivalent to the
205* corresponding interrupt vector.
206*
207*/
208void BSP_disable_gpp_irq(const rtems_irq_symbolic_name irqNum) 
209{
210  unsigned bitNum;
211  unsigned int mask, level;
212  int group, bit;
213
214  bitNum = ((int)irqNum) - BSP_GPP_IRQ_LOWEST_OFFSET;
215
216  _CPU_ISR_Disable(level);
217#if DynamicIrqTbl
218  group = bitNum/8;
219  bit = bitNum%8;
220  GPPinMainIrqTbl[group] &= ~(1<<bit);
221  if ( !GPPinMainIrqTbl[group])/* If it's really the last one */
222     CleanMainIrqTbl(BSP_MAIN_GPP7_0_IRQ+group);
223#endif
224#ifdef SHOW_MORE_INIT_SETTINGS
225  printk("disable irqNum %d, bitnum %d \n", irqNum, bitNum);
226#endif
227  mask = ~ (1 << bitNum);
228  GT_GPPirq_cache &= mask;
229  outl(GT_GPPirq_cache, GT_GPP_Interrupt_Mask);
230  _CPU_ISR_Enable (level);
231}
232
233/* Only print ten entries for now */
234void BSP_printMainIrqTbl()
235{
236  int i;
237
238  printk("mainIrqTbl[10]={");
239  for (i=0; i<10; i++)
240    printk("%d,", mainIrqTbl[i]);
241  printk("}\n");
242  printk("GPPinMainIrqTbl 0x%x 0x%x 0x%x 0x%x\n",
243         GPPinMainIrqTbl[0], GPPinMainIrqTbl[1],
244         GPPinMainIrqTbl[2], GPPinMainIrqTbl[3]);
245}
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