source: rtems/c/src/lib/libbsp/powerpc/mvme5500/README @ e4f98f1

4.104.11
Last change on this file since e4f98f1 was e4f98f1, checked in by Joel Sherrill <joel.sherrill@…>, on Nov 20, 2008 at 4:24:29 PM

2008-11-20 Joel Sherrill <joel.sherrill@…>

  • README: Fix typo.
  • Property mode set to 100644
File size: 4.0 KB
Line 
1#
2#  $Id$
3#
4
5Please reference README.booting for the boot/load process.
6
7For the priority setting of the Interrupt Requests (IRQs), please
8reference README.irq
9
10The BSP is built and tested on the 4.7.1 and 4.7.99.2 CVS RTEMS release.
11
12I believe in valuable real-time programming, where technical neatness,
13performance and truth are.  I hope I still believe. Any suggestion,
14bug reports, or even bug fixes (great!) would be highly appreciated
15so that I still believe what I believe.
16
17
18ACKNOWLEDGEMENTS
19----------------
20Acknowledgements:
21
22Valuable information was obtained from the following:
231) Marvell NDA document for the discovery system controller.
24Other related documents are listed at :
25http://www.aps.anl.gov/epics/meetings/2006-06/RTEMS_Primer_SIG/RTEMS_BSP_MVME5500.pdf
262) netBSD: For the two NICS and some headers :
27           Allegro Networks, Inc., Wasabi Systems, Inc. 
283) RTEMS:  This BSP also builds on top of the work of others who have
29 contributed to similar RTEMS powerpc shared and motorola_powerpc BSPs, most
30 notably Eric Valette, Till Straumann (SVGM1 BSP, too), Eric Norum and others.
31
32LICENSE
33-------
34See ./LICENSE file.
35
36BSP NAME:           mvme5500
37BOARD:              MVME5500 by Motorola
38BUS:                PCI
39CPU FAMILY:         ppc
40CPU:                MPC7455 @ 1GHZ
41COPROCESSORS:       N/A
42MODE:               32/64 bit mode (support 32 bit for now)
43DEBUG MONITOR:      MOTLoad
44SYSTEM CONTROLLER:  GT64260B
45
46PERIPHERALS
47===========
48TIMERS:             Eight, 32 bit programmable
49SERIAL PORTS:       2 NS 16550 on GT64260B
50REAL-TIME CLOCK:    MK48T37V
5132K NVSRAM:         MK48T37V
52WATCHDOG TIMER:     use the one in GT-64260B
53DMA:                8 channel DMA controller (GT-64260B)
54VIDEO:              none
55NETWORKING:         Port 1: Intel 82544EI Gigabit Ethernet Controller
56                    10/100/1000Mb/s routed to front panel RJ-45
57                    Port 2: 10/100 Mb ethernet unit integrated on the
58                    Marvell's GT64260 system controller
59
60DRIVER INFORMATION
61==================
62CLOCK DRIVER:       PPC internal
63IOSUPP DRIVER:      N/A
64SHMSUPP:            N/A
65TIMER DRIVER:       PPC internal
66TTY DRIVER:         PPC internal
67
68STDIO
69=====
70PORT:               Console port 0
71ELECTRICAL:         na
72BAUD:               na
73BITS PER CHARACTER: na
74PARITY:             na
75STOP BITS:          na
76
77
78Jumpers
79=======
80
811) The BSP is tested with the 60x bus mode instead of the MPX bus mode.
82   ( No jumper or a jumper across pins 1-2 on J19 selects the 60x bus mode)
83
842) On the mvme5500 board, Ethernet 1 is the Gigabit Ethernet port and is
85   front panel only. Ethernet 2 is 10/100 BaseT Ethernet. For front-panel
86   Ethernet2, install jumpers across pins 1-2 on all J6, J7, J100 and
87   J101 headers.
88
893) Enable SROM initialization at startup. (No jumper or a jumper across
90   pins 1-2 on J17)
91
92In fact, (if I did not miss anything) the mvme5500 board should function
93properly if one keeps all the jumpers at factory configuration.
94One can leave out the jumper on J30 to disable EEPROM programming.
95
96Notes
97=====
98
99BSP BAT usage
100----------------------
101DBAT0 and IBAT0
1020x00000000
1030x0fffffff  1st 256M, for MEMORY access (caching enabled)
104
105DBAT1 and IBAT1
1060x00000000
1070x0fffffff  2nd 256M, for MEMORY access (caching enabled)
108
109UPDATE: (2004/5).
110The BSP now uses page tables for mapping the entire 512MB
111of RAM. DBAT0 and DBAT1 is hence free for use by the
112application. A simple 1:1 (virt<->phys) mapping is employed.
113The BSP write-protects the text and read-only data
114areas of the application.  Special acknowledgement to Till
115Straumann <strauman@slac.stanford.edu> for providing inputs in
116porting the memory protection software he wrote (BSP_pgtbl_xxx())
117to MVME5500.
118
119
120The default VME configuration uses DBAT0 to map
121more PCI memory space for use by the universe VME
122bridge:
123
124DBAT0
1250x90000000      PCI memory space <-> VME
1260x9fffffff
127
128Port  VME-Addr   Size       PCI-Adrs   Mode:
1290:    0x20000000 0x0F000000 0x90000000 A32, Dat, Sup
1301:    0x00000000 0x00FF0000 0x9F000000 A24, Dat, Sup
1312:    0x00000000 0x00010000 0x9FFF0000 A16, Dat, Sup
132
133
Note: See TracBrowser for help on using the repository browser.