1 | # |
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2 | # $Id: README,v 1.3.1 Shuchen Kate Feng, NSLS, BNL (08/27/07) |
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3 | # |
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4 | |
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5 | Please reference README.booting for the boot/load process. |
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6 | |
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7 | For the priority setting of the Interrupt Requests (IRQs), please |
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8 | reference README.irq |
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9 | |
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10 | The BSP is built and tested on the 4.7.1 and 4.7.99.2 CVS RTEMS release. |
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11 | |
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12 | I believe in valuable real-time programming, where technical neatness, |
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13 | performance and truth are. Any suggestion, bug reports, or even bug |
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14 | fixes (great!) are welcome so that I still believe what I believe. |
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15 | |
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16 | |
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17 | ACKNOWLEDGEMENTS |
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18 | ---------------- |
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19 | Acknowledgements: |
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20 | |
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21 | Valuable information was obtained from the following: |
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22 | 1) Marvell NDA document for the discovery system controller. |
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23 | Other related documents are listed at : |
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24 | http://www.aps.anl.gov/epics/meetings/2006-06/RTEMS_Primer_SIG/RTEMS_BSP_MVME5500.pdf |
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25 | 2) netBSD: For the two NICS and some headers : |
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26 | Allegro Networks, Inc., Wasabi Systems, Inc. |
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27 | 3) RTEMS: For the SVGM5 BSP |
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28 | Stanford Linear Accelerator Center, Till Straumann |
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29 | |
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30 | This BSP also builds on top of the work of others who have contributed |
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31 | to similar RTEMS powerpc shared and motorola_powerpc BSPs, most notably |
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32 | Eric Valette, Till Straumann, Eric Norum and others. |
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33 | |
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34 | LICENSE |
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35 | ------- |
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36 | See ./LICENSE file. |
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37 | |
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38 | BSP NAME: mvme5500 |
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39 | BOARD: MVME5500 by Motorola |
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40 | BUS: PCI |
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41 | CPU FAMILY: ppc |
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42 | CPU: MPC7455 @ 1GHZ |
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43 | COPROCESSORS: N/A |
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44 | MODE: 32/64 bit mode (support 32 bit for now) |
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45 | DEBUG MONITOR: MOTLoad |
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46 | SYSTEM CONTROLLER: GT64260B |
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47 | |
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48 | PERIPHERALS |
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49 | =========== |
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50 | TIMERS: Eight, 32 bit programmable |
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51 | SERIAL PORTS: 2 NS 16550 on GT64260B |
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52 | REAL-TIME CLOCK: MK48T37V |
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53 | 32K NVSRAM: MK48T37V |
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54 | WATCHDOG TIMER: use the one in GT-64260B |
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55 | DMA: 8 channel DMA controller (GT-64260B) |
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56 | VIDEO: none |
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57 | NETWORKING: Port 1: Intel 82544EI Gigabit Ethernet Controller |
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58 | 10/100/1000Mb/s routed to front panel RJ-45 |
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59 | Port 2: 10/100 Mb ethernet unit integrated on the |
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60 | Marvell's GT64260 system controller |
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61 | |
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62 | DRIVER INFORMATION |
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63 | ================== |
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64 | CLOCK DRIVER: PPC internal |
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65 | IOSUPP DRIVER: N/A |
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66 | SHMSUPP: N/A |
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67 | TIMER DRIVER: PPC internal |
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68 | TTY DRIVER: PPC internal |
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69 | |
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70 | STDIO |
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71 | ===== |
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72 | PORT: Console port 0 |
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73 | ELECTRICAL: na |
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74 | BAUD: na |
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75 | BITS PER CHARACTER: na |
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76 | PARITY: na |
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77 | STOP BITS: na |
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78 | |
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79 | |
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80 | Jumpers |
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81 | ======= |
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82 | |
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83 | 1) The BSP is tested with the 60x bus mode instead of the MPX bus mode. |
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84 | ( No jumper or a jumper across pins 1-2 on J19 selects the 60x bus mode) |
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85 | |
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86 | 2) On the mvme5500 board, Ethernet 1 is the Gigabit Ethernet port and is |
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87 | front panel only. Ethernet 2 is 10/100 BaseT Ethernet. For front-panel |
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88 | Ethernet2, install jumpers across pins 1-2 on all J6, J7, J100 and |
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89 | J101 headers. |
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90 | |
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91 | 3) Enable SROM initialization at startup. (No jumper or a jumper across |
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92 | pins 1-2 on J17) |
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93 | |
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94 | In fact, (if I did not miss anything) the mvme5500 board should function |
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95 | properly if one keeps all the jumpers at factory configuration. |
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96 | One can leave out the jumper on J30 to disable EEPROM programming. |
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97 | |
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98 | Notes |
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99 | ===== |
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100 | |
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101 | BSP BAT usage |
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102 | ---------------------- |
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103 | DBAT0 and IBAT0 |
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104 | 0x00000000 |
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105 | 0x0fffffff 1st 256M, for MEMORY access (caching enabled) |
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106 | |
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107 | DBAT1 and IBAT1 |
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108 | 0x00000000 |
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109 | 0x0fffffff 2nd 256M, for MEMORY access (caching enabled) |
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110 | |
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111 | UPDATE: (2004/5). |
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112 | The BSP now uses page tables for mapping the entire 512MB |
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113 | of RAM. DBAT0 and DBAT1 is hence free for use by the |
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114 | application. A simple 1:1 (virt<->phys) mapping is employed. |
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115 | The BSP write-protects the text and read-only data |
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116 | areas of the application. Special acknowledgement to Till |
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117 | Straumann <strauman@slac.stanford.edu> for providing inputs in |
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118 | porting the memory protection software he wrote (BSP_pgtbl_xxx()) |
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119 | to MVME5500. |
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120 | |
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121 | |
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122 | The default VME configuration uses DBAT0 to map |
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123 | more PCI memory space for use by the universe VME |
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124 | bridge: |
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125 | |
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126 | DBAT0 |
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127 | 0x90000000 PCI memory space <-> VME |
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128 | 0x9fffffff |
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129 | |
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130 | Port VME-Addr Size PCI-Adrs Mode: |
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131 | 0: 0x20000000 0x0F000000 0x90000000 A32, Dat, Sup |
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132 | 1: 0x00000000 0x00FF0000 0x9F000000 A24, Dat, Sup |
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133 | 2: 0x00000000 0x00010000 0x9FFF0000 A16, Dat, Sup |
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134 | |
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135 | |
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