source: rtems/c/src/lib/libbsp/powerpc/mvme5500/README @ b047186

Last change on this file since b047186 was b047186, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 14, 2007 at 3:43:37 PM

2007-09-14 Kate Feng <feng1@…>

  • Makefile.am, README, README.booting, README.irq, preinstall.am, GT64260/MVME5500I2C.c, include/bsp.h, irq/irq.c, irq/irq.h, irq/irq_init.c, pci/pci.c, pci/pci_interface.c, pci/pcifinddevice.c, start/preload.S, startup/bspclean.c, startup/bspstart.c, startup/pgtbl_activate.c, startup/reboot.c: Merge my improvements in this BSP including a new network driver for the 1GHz NIC.
  • network/if_100MHz/GT64260eth.c, network/if_100MHz/GT64260eth.h, network/if_100MHz/GT64260ethreg.h, network/if_100MHz/Makefile.am, network/if_1GHz/Makefile.am, network/if_1GHz/POSSIBLEBUG, network/if_1GHz/if_wm.c, network/if_1GHz/if_wmreg.h, network/if_1GHz/pci_map.c, network/if_1GHz/pcireg.h: New files.
  • Property mode set to 100644
File size: 4.0 KB
Line 
1#
2#  $Id: README,v 1.3.1  Shuchen Kate Feng, NSLS, BNL (08/27/07)
3#
4
5Please reference README.booting for the boot/load process.
6
7For the priority setting of the Interrupt Requests (IRQs), please
8reference README.irq
9
10The BSP is built and tested on the 4.7.1 and 4.7.99.2 CVS RTEMS release.
11
12I believe in valuable real-time programming, where technical neatness,
13performance and truth are.  Any suggestion, bug reports, or even bug
14fixes (great!) are welcome so that I still believe what I believe.
15
16
17ACKNOWLEDGEMENTS
18----------------
19Acknowledgements:
20
21Valuable information was obtained from the following:
221) Marvell NDA document for the discovery system controller.
23Other related documents are listed at :
24http://www.aps.anl.gov/epics/meetings/2006-06/RTEMS_Primer_SIG/RTEMS_BSP_MVME5500.pdf
252) netBSD: For the two NICS and some headers :
26           Allegro Networks, Inc., Wasabi Systems, Inc. 
273) RTEMS: For the SVGM5 BSP
28          Stanford Linear Accelerator Center, Till Straumann
29
30 This BSP also builds on top of the work of others who have contributed
31 to similar RTEMS powerpc shared and motorola_powerpc BSPs, most notably
32 Eric Valette, Till Straumann, Eric Norum and others.
33
34LICENSE
35-------
36See ./LICENSE file.
37
38BSP NAME:           mvme5500
39BOARD:              MVME5500 by Motorola
40BUS:                PCI
41CPU FAMILY:         ppc
42CPU:                MPC7455 @ 1GHZ
43COPROCESSORS:       N/A
44MODE:               32/64 bit mode (support 32 bit for now)
45DEBUG MONITOR:      MOTLoad
46SYSTEM CONTROLLER:  GT64260B
47
48PERIPHERALS
49===========
50TIMERS:             Eight, 32 bit programmable
51SERIAL PORTS:       2 NS 16550 on GT64260B
52REAL-TIME CLOCK:    MK48T37V
5332K NVSRAM:         MK48T37V
54WATCHDOG TIMER:     use the one in GT-64260B
55DMA:                8 channel DMA controller (GT-64260B)
56VIDEO:              none
57NETWORKING:         Port 1: Intel 82544EI Gigabit Ethernet Controller
58                    10/100/1000Mb/s routed to front panel RJ-45
59                    Port 2: 10/100 Mb ethernet unit integrated on the
60                    Marvell's GT64260 system controller
61
62DRIVER INFORMATION
63==================
64CLOCK DRIVER:       PPC internal
65IOSUPP DRIVER:      N/A
66SHMSUPP:            N/A
67TIMER DRIVER:       PPC internal
68TTY DRIVER:         PPC internal
69
70STDIO
71=====
72PORT:               Console port 0
73ELECTRICAL:         na
74BAUD:               na
75BITS PER CHARACTER: na
76PARITY:             na
77STOP BITS:          na
78
79
80Jumpers
81=======
82
831) The BSP is tested with the 60x bus mode instead of the MPX bus mode.
84   ( No jumper or a jumper across pins 1-2 on J19 selects the 60x bus mode)
85
862) On the mvme5500 board, Ethernet 1 is the Gigabit Ethernet port and is
87   front panel only. Ethernet 2 is 10/100 BaseT Ethernet. For front-panel
88   Ethernet2, install jumpers across pins 1-2 on all J6, J7, J100 and
89   J101 headers.
90
913) Enable SROM initialization at startup. (No jumper or a jumper across
92   pins 1-2 on J17)
93
94In fact, (if I did not miss anything) the mvme5500 board should function
95properly if one keeps all the jumpers at factory configuration.
96One can leave out the jumper on J30 to disable EEPROM programming.
97
98Notes
99=====
100
101BSP BAT usage
102----------------------
103DBAT0 and IBAT0
1040x00000000
1050x0fffffff  1st 256M, for MEMORY access (caching enabled)
106
107DBAT1 and IBAT1
1080x00000000
1090x0fffffff  2nd 256M, for MEMORY access (caching enabled)
110
111UPDATE: (2004/5).
112The BSP now uses page tables for mapping the entire 512MB
113of RAM. DBAT0 and DBAT1 is hence free for use by the
114application. A simple 1:1 (virt<->phys) mapping is employed.
115The BSP write-protects the text and read-only data
116areas of the application.  Special acknowledgement to Till
117Straumann <strauman@slac.stanford.edu> for providing inputs in
118porting the memory protection software he wrote (BSP_pgtbl_xxx())
119to MVME5500.
120
121
122The default VME configuration uses DBAT0 to map
123more PCI memory space for use by the universe VME
124bridge:
125
126DBAT0
1270x90000000      PCI memory space <-> VME
1280x9fffffff
129
130Port  VME-Addr   Size       PCI-Adrs   Mode:
1310:    0x20000000 0x0F000000 0x90000000 A32, Dat, Sup
1321:    0x00000000 0x00FF0000 0x9F000000 A24, Dat, Sup
1332:    0x00000000 0x00010000 0x9FFF0000 A16, Dat, Sup
134
135
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