source: rtems/c/src/lib/libbsp/powerpc/mvme5500/README @ 2fd2786

4.104.114.84.95
Last change on this file since 2fd2786 was 7be6ad9, checked in by Eric Norum <WENorum@…>, on 10/20/04 at 15:21:05

Add MVME550 BSP

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1#
2#  $Id: README,v 1.1  Shuchen Kate Feng, NSLS, BNL (10/10/04)
3#
4
5BSP NAME:           mvme5500
6BOARD:              MVME5500 by Motorola
7BUS:                PCI
8CPU FAMILY:         ppc
9CPU:                MPC7455 @ 1GHZ
10COPROCESSORS:       N/A
11MODE:               32/64 bit mode (support 32 bit for now)
12DEBUG MONITOR:      MOTLoad
13SYSTEM CONTROLLER:  GT64260B
14
15OTHER README FILES: README.booting,README.rtems-4.6.0-patch,README.VME,
16                    README.irq
17
18PERIPHERALS
19===========
20TIMERS:             Eight, 32 bit programmable
21SERIAL PORTS:       2 NS 16550 on GT64260B
22REAL-TIME CLOCK:    MK48T37V
2332K NVSRAM:         MK48T37V
24WATCHDOG TIMER:     use the one in GT-64260B
25DMA:                8 channel DMA controller (GT-64260B)
26VIDEO:              none
27NETWORKING:         Port 1: Intel 82544EI Gigabit Ethernet Controller
28                    10/100/1000Mb/s routed to front panel RJ-45
29                    Port 2: 10/100 Mb ethernet unit integrated on the
30                    Marvell's GT64260 system controller
31
32DRIVER INFORMATION
33==================
34CLOCK DRIVER:       PPC internal
35IOSUPP DRIVER:      N/A
36SHMSUPP:            N/A
37TIMER DRIVER:       PPC internal
38TTY DRIVER:         PPC internal
39
40STDIO
41=====
42PORT:               Console port 0
43ELECTRICAL:         na
44BAUD:               na
45BITS PER CHARACTER: na
46PARITY:             na
47STOP BITS:          na
48
49
50Jumpers
51=======
52
531) The BSP is tested with the 60x bus mode instead of the MPX bus mode.
54   ( No jumper or a jumper across pins 1-2 on J19 selects the 60x bus mode)
55
562) On the mvme5500 board, Ethernet 1 is the Gigabit Ethernet port and is
57   front panel only. Ethernet 2 is 10/100 BaseT Ethernet. For front-panel
58   Ethernet2, install jumpers across pins 1-2 on all J6, J7, J100 and
59   J101 headers.
60
613) Enable SROM initialization at startup. (No jumper or a jumper across
62   pins 1-2 on J17)
63
64In fact, (if I did not miss anything) the mvme5500 board should function
65properly if one keeps all the jumpers at factory configuration.
66One can leave out the jumper on J30 to disable EEPROM programming.
67
68Notes
69=====
70
71BSP BAT usage
72----------------------
73DBAT0 and IBAT0
740x00000000
750x0fffffff  1st 256M, for MEMORY access (caching enabled)
76
77DBAT1 and IBAT1
780x00000000
790x0fffffff  2nd 256M, for MEMORY access (caching enabled)
80
81UPDATE: (2004/5).
82The BSP now uses page tables for mapping the entire 512MB
83of RAM. DBAT0 and DBAT1 is hence free for use by the
84application. A simple 1:1 (virt<->phys) mapping is employed.
85The BSP write-protects the text and read-only data
86areas of the application.  Special acknowledgement to Till
87Straumann <strauman@slac.stanford.edu> for providing inputs in
88porting the memory protection software he wrote (BSP_pgtbl_xxx())
89to MVME5500.
90
91
92The default VME configuration uses DBAT0 to map
93more PCI memory space for use by the universe VME
94bridge:
95
96DBAT0
970x90000000      PCI memory space <-> VME
980x9fffffff
99
100Port  VME-Addr   Size       PCI-Adrs   Mode:
1010:    0x20000000 0x0F000000 0x90000000 A32, Dat, Sup
1021:    0x00000000 0x00FF0000 0x9F000000 A24, Dat, Sup
1032:    0x00000000 0x00010000 0x9FFF0000 A16, Dat, Sup
104
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