| 1 | # |
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| 2 | # $Id: README,v 1.3.1 Shuchen Kate Feng, NSLS, BNL (08/27/07) |
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| 3 | # |
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| 4 | |
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| 5 | Please reference README.booting for the boot/load process. |
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| 6 | |
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| 7 | For the priority setting of the Interrupt Requests (IRQs), please |
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| 8 | reference README.irq |
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| 9 | |
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| 10 | The BSP is built and tested on the 4.7.1 and 4.7.99.2 CVS RTEMS release. |
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| 11 | |
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| 12 | I believe in valuable real-time programming, where technical neatness, |
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| 13 | performance and truth are. Any suggestion, bug reports, or even bug |
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| 14 | fixes (great!) would be highly appreciated so that I still believe |
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| 15 | what I believe. |
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| 16 | |
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| 17 | |
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| 18 | ACKNOWLEDGEMENTS |
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| 19 | ---------------- |
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| 20 | Acknowledgements: |
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| 21 | |
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| 22 | Valuable information was obtained from the following: |
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| 23 | 1) Marvell NDA document for the discovery system controller. |
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| 24 | Other related documents are listed at : |
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| 25 | http://www.aps.anl.gov/epics/meetings/2006-06/RTEMS_Primer_SIG/RTEMS_BSP_MVME5500.pdf |
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| 26 | 2) netBSD: For the two NICS and some headers : |
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| 27 | Allegro Networks, Inc., Wasabi Systems, Inc. |
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| 28 | 3) RTEMS: For the SVGM5 BSP |
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| 29 | Stanford Linear Accelerator Center, Till Straumann |
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| 30 | |
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| 31 | This BSP also builds on top of the work of others who have contributed |
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| 32 | to similar RTEMS powerpc shared and motorola_powerpc BSPs, most notably |
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| 33 | Eric Valette, Till Straumann, Eric Norum and others. |
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| 34 | |
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| 35 | LICENSE |
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| 36 | ------- |
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| 37 | See ./LICENSE file. |
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| 38 | |
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| 39 | BSP NAME: mvme5500 |
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| 40 | BOARD: MVME5500 by Motorola |
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| 41 | BUS: PCI |
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| 42 | CPU FAMILY: ppc |
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| 43 | CPU: MPC7455 @ 1GHZ |
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| 44 | COPROCESSORS: N/A |
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| 45 | MODE: 32/64 bit mode (support 32 bit for now) |
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| 46 | DEBUG MONITOR: MOTLoad |
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| 47 | SYSTEM CONTROLLER: GT64260B |
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| 48 | |
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| 49 | PERIPHERALS |
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| 50 | =========== |
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| 51 | TIMERS: Eight, 32 bit programmable |
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| 52 | SERIAL PORTS: 2 NS 16550 on GT64260B |
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| 53 | REAL-TIME CLOCK: MK48T37V |
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| 54 | 32K NVSRAM: MK48T37V |
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| 55 | WATCHDOG TIMER: use the one in GT-64260B |
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| 56 | DMA: 8 channel DMA controller (GT-64260B) |
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| 57 | VIDEO: none |
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| 58 | NETWORKING: Port 1: Intel 82544EI Gigabit Ethernet Controller |
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| 59 | 10/100/1000Mb/s routed to front panel RJ-45 |
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| 60 | Port 2: 10/100 Mb ethernet unit integrated on the |
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| 61 | Marvell's GT64260 system controller |
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| 62 | |
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| 63 | DRIVER INFORMATION |
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| 64 | ================== |
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| 65 | CLOCK DRIVER: PPC internal |
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| 66 | IOSUPP DRIVER: N/A |
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| 67 | SHMSUPP: N/A |
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| 68 | TIMER DRIVER: PPC internal |
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| 69 | TTY DRIVER: PPC internal |
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| 70 | |
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| 71 | STDIO |
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| 72 | ===== |
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| 73 | PORT: Console port 0 |
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| 74 | ELECTRICAL: na |
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| 75 | BAUD: na |
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| 76 | BITS PER CHARACTER: na |
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| 77 | PARITY: na |
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| 78 | STOP BITS: na |
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| 79 | |
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| 80 | |
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| 81 | Jumpers |
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| 82 | ======= |
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| 83 | |
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| 84 | 1) The BSP is tested with the 60x bus mode instead of the MPX bus mode. |
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| 85 | ( No jumper or a jumper across pins 1-2 on J19 selects the 60x bus mode) |
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| 86 | |
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| 87 | 2) On the mvme5500 board, Ethernet 1 is the Gigabit Ethernet port and is |
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| 88 | front panel only. Ethernet 2 is 10/100 BaseT Ethernet. For front-panel |
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| 89 | Ethernet2, install jumpers across pins 1-2 on all J6, J7, J100 and |
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| 90 | J101 headers. |
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| 91 | |
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| 92 | 3) Enable SROM initialization at startup. (No jumper or a jumper across |
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| 93 | pins 1-2 on J17) |
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| 94 | |
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| 95 | In fact, (if I did not miss anything) the mvme5500 board should function |
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| 96 | properly if one keeps all the jumpers at factory configuration. |
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| 97 | One can leave out the jumper on J30 to disable EEPROM programming. |
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| 98 | |
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| 99 | Notes |
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| 100 | ===== |
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| 101 | |
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| 102 | BSP BAT usage |
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| 103 | ---------------------- |
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| 104 | DBAT0 and IBAT0 |
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| 105 | 0x00000000 |
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| 106 | 0x0fffffff 1st 256M, for MEMORY access (caching enabled) |
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| 107 | |
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| 108 | DBAT1 and IBAT1 |
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| 109 | 0x00000000 |
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| 110 | 0x0fffffff 2nd 256M, for MEMORY access (caching enabled) |
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| 111 | |
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| 112 | UPDATE: (2004/5). |
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| 113 | The BSP now uses page tables for mapping the entire 512MB |
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| 114 | of RAM. DBAT0 and DBAT1 is hence free for use by the |
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| 115 | application. A simple 1:1 (virt<->phys) mapping is employed. |
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| 116 | The BSP write-protects the text and read-only data |
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| 117 | areas of the application. Special acknowledgement to Till |
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| 118 | Straumann <strauman@slac.stanford.edu> for providing inputs in |
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| 119 | porting the memory protection software he wrote (BSP_pgtbl_xxx()) |
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| 120 | to MVME5500. |
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| 121 | |
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| 122 | |
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| 123 | The default VME configuration uses DBAT0 to map |
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| 124 | more PCI memory space for use by the universe VME |
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| 125 | bridge: |
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| 126 | |
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| 127 | DBAT0 |
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| 128 | 0x90000000 PCI memory space <-> VME |
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| 129 | 0x9fffffff |
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| 130 | |
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| 131 | Port VME-Addr Size PCI-Adrs Mode: |
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| 132 | 0: 0x20000000 0x0F000000 0x90000000 A32, Dat, Sup |
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| 133 | 1: 0x00000000 0x00FF0000 0x9F000000 A24, Dat, Sup |
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| 134 | 2: 0x00000000 0x00010000 0x9FFF0000 A16, Dat, Sup |
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| 135 | |
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| 136 | |
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