1 | README.irq : Shuchen Kate Feng <feng1@bnl.gov>, 10/10/04 |
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2 | |
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3 | |
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4 | The BSPirqPrioTable[] listed in irq_init.c is where the |
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5 | software developers can change the levels of priority |
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6 | for main interrupts based on the need of their |
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7 | applications. |
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8 | |
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9 | |
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10 | Presently, a dynamic IRQ table (e.g. mainIrqTbl[64]), which is |
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11 | arranged dynamically based on the priority levels of enabled |
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12 | main interrupts, is used in C_dispatch_irq_handler() to |
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13 | incorporate the handling of the software priority levels. |
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14 | |
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15 | |
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16 | The valid entries listed in mainIrqTbl[64] by the BSP are: |
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17 | |
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18 | 1. Main interrupt 59 (GPP31_24 : no enabled IRQ yet, |
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19 | to enable 'watchdog timer' if needed) |
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20 | 2. Main interrupt 57 (GPP15_8 : VME interrupt enabled, |
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21 | to enable 'PMC1' if needed) |
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22 | 3. Main interrupt 58 (GPP23_16 : no enabled IRQ yet, |
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23 | to enable '1 GHZ ethernet' or 'PMC2' |
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24 | if needed) |
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25 | 4. Main interrupt 32 (10/100 MHZ ethernet) |
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26 | 5. Main interrupt 56 (GPP7_0 : presently only COM1/COM2 enabled) |
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27 | |
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28 | |
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29 | The main IRQs can be added to the mainIrqTbl[] dynamically |
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30 | via the BSP_enable_main_irq(), or removed from the mainIrqTbl[] |
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31 | dynamically via the BSP_disable_main_irq(). |
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32 | |
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33 | |
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34 | Regarding other GPP interrupts not listed in the GPP7_0IrqTbl[8], |
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35 | GPP15_8IrqTbl[8], GPP23_16IrqTbl[8], or GPP31_24IrqTbl[8], they |
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36 | could be enabled by being added to the correspondent of |
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37 | the four aforementioned tables listed in the irq_init.c. |
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38 | |
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39 | |
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40 | Caveat: Presently, the eight GPP IRQs for each BSP_MAIN_GPPx_y_IRQ group |
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41 | are set at the same main priority in the BSPirqPrioTable[], while the |
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42 | sub-priority levels for the eight GPP in each group are sorted |
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43 | statically by developers in the GPPx_yIrqTbl[8] from the highest |
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44 | priority to the lowest one. |
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45 | |
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46 | |
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47 | Note : |
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48 | 1. GPP7-0 (Main interrupt high cause, bit 24) |
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49 | 2. GPP15-8 (Main interrupt high cause, bit 25) |
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50 | 3. GPP23-16 (Main interrupt high cause, bit 26) |
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51 | 4. GPP31-24 (Main interrupt high cause, bit 27) |
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52 | |
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