source: rtems/c/src/lib/libbsp/powerpc/mvme5500/GT64260/gtreg.h @ 7be6ad9

4.104.114.84.9
Last change on this file since 7be6ad9 was 7be6ad9, checked in by Eric Norum <WENorum@…>, on Oct 20, 2004 at 3:21:05 PM

Add MVME550 BSP

  • Property mode set to 100644
File size: 29.8 KB
Line 
1/*      $NetBSD: gtreg.h,v 1.1 2003/03/05 22:08:22 matt Exp $   */
2
3/*
4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 *    must display the following acknowledgement:
17 *      This product includes software developed for the NetBSD Project by
18 *      Allegro Networks, Inc., and Wasabi Systems, Inc.
19 * 4. The name of Allegro Networks, Inc. may not be used to endorse
20 *    or promote products derived from this software without specific prior
21 *    written permission.
22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse
23 *    or promote products derived from this software without specific prior
24 *    written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND
27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC.
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 */
39
40#ifndef _DISCOVERY_DEV_GTREG_H_
41#define _DISCOVERY_DEV_GTREG_H_
42
43#define GT__BIT(bit)                    (1U << (bit))
44#define GT__MASK(bit)                   (GT__BIT(bit) - 1)
45#define GT__EXT(data, bit, len)         (((data) >> (bit)) & GT__MASK(len))
46#define GT__CLR(data, bit, len)         ((data) &= ~(GT__MASK(len) << (bit)))
47#define GT__INS(new, bit)               ((new) << (bit))
48
49
50/*
51 * Table 30: CPU Address Decode Register Map
52 */
53#define GT_SCS0_Low_Decode              0x0008
54#define GT_SCS0_High_Decode             0x0010
55#define GT_SCS1_Low_Decode              0x0208
56#define GT_SCS1_High_Decode             0x0210
57#define GT_SCS2_Low_Decode              0x0018
58#define GT_SCS2_High_Decode             0x0020
59#define GT_SCS3_Low_Decode              0x0218
60#define GT_SCS3_High_Decode             0x0220
61#define GT_CS0_Low_Decode               0x0028
62#define GT_CS0_High_Decode              0x0030
63#define GT_CS1_Low_Decode               0x0228
64#define GT_CS1_High_Decode              0x0230
65#define GT_CS2_Low_Decode               0x0248
66#define GT_CS2_High_Decode              0x0250
67#define GT_CS3_Low_Decode               0x0038
68#define GT_CS3_High_Decode              0x0040
69#define GT_BootCS_Low_Decode            0x0238
70#define GT_BootCS_High_Decode           0x0240
71#define GT_PCI0_IO_Low_Decode           0x0048
72#define GT_PCI0_IO_High_Decode          0x0050
73#define GT_PCI0_Mem0_Low_Decode         0x0058
74#define GT_PCI0_Mem0_High_Decode        0x0060
75#define GT_PCI0_Mem1_Low_Decode         0x0080
76#define GT_PCI0_Mem1_High_Decode        0x0088
77#define GT_PCI0_Mem2_Low_Decode         0x0258
78#define GT_PCI0_Mem2_High_Decode        0x0260
79#define GT_PCI0_Mem3_Low_Decode         0x0280
80#define GT_PCI0_Mem3_High_Decode        0x0288
81#define GT_PCI1_IO_Low_Decode           0x0090
82#define GT_PCI1_IO_High_Decode          0x0098
83#define GT_PCI1_Mem0_Low_Decode         0x00a0
84#define GT_PCI1_Mem0_High_Decode        0x00a8
85#define GT_PCI1_Mem1_Low_Decode         0x00b0
86#define GT_PCI1_Mem1_High_Decode        0x00b8
87#define GT_PCI1_Mem2_Low_Decode         0x02a0
88#define GT_PCI1_Mem2_High_Decode        0x02a8
89#define GT_PCI1_Mem3_Low_Decode         0x02b0
90#define GT_PCI1_Mem3_High_Decode        0x02b8
91#define GT_Internal_Decode              0x0068
92#define GT_CPU0_Low_Decode              0x0290
93#define GT_CPU0_High_Decode             0x0298
94#define GT_CPU1_Low_Decode              0x02c0
95#define GT_CPU1_High_Decode             0x02c8
96#define GT_PCI0_IO_Remap                0x00f0
97#define GT_PCI0_Mem0_Remap_Low          0x00f8
98#define GT_PCI0_Mem0_Remap_High         0x0320
99#define GT_PCI0_Mem1_Remap_Low          0x0100
100#define GT_PCI0_Mem1_Remap_High         0x0328
101#define GT_PCI0_Mem2_Remap_Low          0x02f8
102#define GT_PCI0_Mem2_Remap_High         0x0330
103#define GT_PCI0_Mem3_Remap_Low          0x0300
104#define GT_PCI0_Mem3_Remap_High         0x0338
105#define GT_PCI1_IO_Remap                0x0108
106#define GT_PCI1_Mem0_Remap_Low          0x0110
107#define GT_PCI1_Mem0_Remap_High         0x0340
108#define GT_PCI1_Mem1_Remap_Low          0x0118
109#define GT_PCI1_Mem1_Remap_High         0x0348
110#define GT_PCI1_Mem2_Remap_Low          0x0310
111#define GT_PCI1_Mem2_Remap_High         0x0350
112#define GT_PCI1_Mem3_Remap_Low          0x0318
113#define GT_PCI1_Mem3_Remap_High         0x0358
114
115
116/*
117 * Table 31: CPU Control Register Map
118 */
119#define GT_CPU_Cfg                      0x0000
120#define GT_CPU_Mode                     0x0120
121#define GT_CPU_Master_Ctl               0x0160
122#define GT_CPU_If_Xbar_Ctl_Low          0x0150
123#define GT_CPU_If_Xbar_Ctl_High         0x0158
124#define GT_CPU_If_Xbar_Timeout          0x0168
125#define GT_CPU_Rd_Rsp_Xbar_Ctl_Low      0x0170
126#define GT_CPU_Rd_Rsp_Xbar_Ctl_High     0x0178
127
128/*
129 * Table 32: CPU Sync Barrier Register Map
130 */
131#define GT_PCI_Sync_Barrier(bus)        (0x00c0 | ((bus) << 3))
132#define GT_PCI0_Sync_Barrier            0x00c0
133#define GT_PCI1_Sync_Barrier            0x00c8
134
135/*
136 * Table 33: CPU Access Protection Register Map
137 */
138#define GT_Protect_Low_0                0x0180
139#define GT_Protect_High_0               0x0188
140#define GT_Protect_Low_1                0x0190
141#define GT_Protect_High_1               0x0198
142#define GT_Protect_Low_2                0x01a0
143#define GT_Protect_High_2               0x01a8
144#define GT_Protect_Low_3                0x01b0
145#define GT_Protect_High_3               0x01b8
146#define GT_Protect_Low_4                0x01c0
147#define GT_Protect_High_4               0x01c8
148#define GT_Protect_Low_5                0x01d0
149#define GT_Protect_High_5               0x01d8
150#define GT_Protect_Low_6                0x01e0
151#define GT_Protect_High_6               0x01e8
152#define GT_Protect_Low_7                0x01f0
153#define GT_Protect_High_7               0x01f8
154
155/*
156 * Table 34: Snoop Control Register Map
157 */
158#define GT_Snoop_Base_0                 0x0380
159#define GT_Snoop_Top_0                  0x0388
160#define GT_Snoop_Base_1                 0x0390
161#define GT_Snoop_Top_1                  0x0398
162#define GT_Snoop_Base_2                 0x03a0
163#define GT_Snoop_Top_2                  0x03a8
164#define GT_Snoop_Base_3                 0x03b0
165#define GT_Snoop_Top_3                  0x03b8
166
167/*
168 * Table 35: CPU Error Report Register Map
169 */
170#define GT_CPU_Error_Address_Low        0x0070
171#define GT_CPU_Error_Address_High       0x0078
172#define GT_CPU_Error_Data_Low           0x0128
173#define GT_CPU_Error_Data_High          0x0130
174#define GT_CPU_Error_Parity             0x0138
175#define GT_CPU_Error_Cause              0x0140
176#define GT_CPU_Error_Mask               0x0148
177
178#define GT_DecodeAddr_SET(g, r, v)                                      \
179        do {                                                            \
180                gt_read((g), GT_Internal_Decode);                       \
181                gt_write((g), (r), ((v) & 0xfff00000) >> 20);           \
182                while ((gt_read((g), (r)) & 0xfff) != ((v) >> 20));     \
183        } while (0)
184
185#define GT_LowAddr_GET(v)                (GT__EXT((v), 0, 12) << 20)
186#define GT_HighAddr_GET(v)              ((GT__EXT((v), 0, 12) << 20) | 0xfffff)
187
188#define GT_MPP_Control0                 0xf000
189#define GT_MPP_Control1                 0xf004
190#define GT_MPP_Control2                 0xf008
191#define GT_MPP_Control3                 0xf00c
192
193/* <skf> added */
194#define GT_MPP_SerialPortMultiplex      0xf010
195
196#define GT_GPP_IO_Control               0xf100
197#define GT_GPP_Level_Control            0xf110
198#define GT_GPP_Value                    0xf104
199#define GT_GPP_Interrupt_Cause          0xf108
200#define GT_GPP_Interrupt_Mask           0xf10c
201/*
202 * Table 36: SCS[0]* Low Decode Address, Offset: 0x008
203 * Table 38: SCS[1]* Low Decode Address, Offset: 0x208
204 * Table 40: SCS[2]* Low Decode Address, Offset: 0x018
205 * Table 42: SCS[3]* Low Decode Address, Offset: 0x218
206 * Table 44: CS[0]*  Low Decode Address, Offset: 0x028
207 * Table 46: CS[1]*  Low Decode Address, Offset: 0x228
208 * Table 48: CS[2]*  Low Decode Address, Offset: 0x248
209 * Table 50: CS[3]*  Low Decode Address, Offset: 0x038
210 * Table 52: BootCS* Low Decode Address, Offset: 0x238
211 * Table 75: CPU 0   Low Decode Address, Offset: 0x290
212 * Table 77: CPU 1   Low Decode Address, Offset: 0x2c0
213 *
214 * 11:00 LowAddr                SCS[0] Base Address
215 * 31:12 Reserved               Must be 0.
216 */
217
218/*
219 * Table 37: SCS[0]* High Decode Address, Offset: 0x010
220 * Table 39: SCS[1]* High Decode Address, Offset: 0x210
221 * Table 41: SCS[2]* High Decode Address, Offset: 0x020
222 * Table 43: SCS[3]* High Decode Address, Offset: 0x220
223 * Table 45: CS[0]*  High Decode Address, Offset: 0x030
224 * Table 47: CS[1]*  High Decode Address, Offset: 0x230
225 * Table 49: CS[2]*  High Decode Address, Offset: 0x250
226 * Table 51: CS[3]*  High Decode Address, Offset: 0x040
227 * Table 53: BootCS* High Decode Address, Offset: 0x240
228 * Table 76: CPU 0   High Decode Address, Offset: 0x298
229 * Table 78: CPU 1   High Decode Address, Offset: 0x2c8
230 *
231 * 11:00 HighAddr               SCS[0] Top Address
232 * 31:12 Reserved
233 */
234
235/*
236 * Table 54: PCI_0 I/O Low Decode Address,      Offset: 0x048
237 * Table 56: PCI_0 Memory 0 Low Decode Address, Offset: 0x058
238 * Table 58: PCI_0 Memory 1 Low Decode Address, Offset: 0x080
239 * Table 60: PCI_0 Memory 2 Low Decode Address, Offset: 0x258
240 * Table 62: PCI_0 Memory 3 Low Decode Address, Offset: 0x280
241 * Table 64: PCI_1 I/O Low Decode Address,      Offset: 0x090
242 * Table 66: PCI_1 Memory 0 Low Decode Address, Offset: 0x0a0
243 * Table 68: PCI_1 Memory 1 Low Decode Address, Offset: 0x0b0
244 * Table 70: PCI_1 Memory 2 Low Decode Address, Offset: 0x2a0
245 * Table 72: PCI_1 Memory 3 Low Decode Address, Offset: 0x2b0
246 *
247 * 11:00 LowAddr                PCI IO/Memory Space Base Address
248 * 23:12 Reserved
249 * 26:24 PCISwap                PCI Master Data Swap Control (0: Byte Swap;
250 *                              1: No swapping; 2: Both byte and word swap;
251 *                              3: Word swap; 4..7: Reserved)
252 * 27:27 PCIReq64               PCI master REQ64* policy (Relevant only when
253 *                              configured to 64-bit PCI bus and not I/O)
254 *                              0: Assert s REQ64* only when transaction
255 *                                 is longer than 64-bits.
256 *                              1: Always assert REQ64*.
257 * 31:28 Reserved
258 */
259#define GT_PCISwap_GET(v)               GT__EXT((v), 24, 3)
260#define GT_PCISwap_ByteSwap             0
261#define GT_PCISwap_NoSwap               1
262#define GT_PCISwap_ByteWordSwap         2
263#define GT_PCISwap_WordSwap             3
264#define GT_PCI_LowDecode_PCIReq64       GT__BIT(27)
265
266/*
267 * Table 55: PCI_0 I/O High Decode Address,      Offset: 0x050
268 * Table 57: PCI_0 Memory 0 High Decode Address, Offset: 0x060
269 * Table 59: PCI_0 Memory 1 High Decode Address, Offset: 0x088
270 * Table 61: PCI_0 Memory 2 High Decode Address, Offset: 0x260
271 * Table 63: PCI_0 Memory 3 High Decode Address, Offset: 0x288
272 * Table 65: PCI_1 I/O High Decode Address,      Offset: 0x098
273 * Table 67: PCI_1 Memory 0 High Decode Address, Offset: 0x0a8
274 * Table 69: PCI_1 Memory 1 High Decode Address, Offset: 0x0b8
275 * Table 71: PCI_1 Memory 2 High Decode Address, Offset: 0x2a8
276 * Table 73: PCI_1 Memory 3 High Decode Address, Offset: 0x2b8
277 *
278 * 11:00 HighAddr               PCI_0 I/O Space Top Address
279 * 31:12 Reserved
280 */
281
282/*
283 * Table 74: Internal Space Decode, Offset: 0x068
284 * 15:00 IntDecode              GT64260 Internal Space Base Address
285 * 23:16 Reserved
286 * 26:24 PCISwap                Same as PCI_0 Memory 0 Low Decode Address.
287 *                              NOTE: Reserved for Galileo Technology usage.
288 *                              Relevant only for PCI master configuration
289 *                              transactions on the PCI bus.
290 * 31:27 Reserved
291 */
292
293/*
294 * Table 79: PCI_0 I/O Address Remap,          Offset: 0x0f0
295 * Table 80: PCI_0 Memory 0 Address Remap Low, Offset: 0x0f8
296 * Table 82: PCI_0 Memory 1 Address Remap Low, Offset: 0x100
297 * Table 84: PCI_0 Memory 2 Address Remap Low, Offset: 0x2f8
298 * Table 86: PCI_0 Memory 3 Address Remap Low, Offset: 0x300
299 * Table 88: PCI_1 I/O Address Remap,          Offset: 0x108
300 * Table 89: PCI_1 Memory 0 Address Remap Low, Offset: 0x110
301 * Table 91: PCI_1 Memory 1 Address Remap Low, Offset: 0x118
302 * Table 93: PCI_1 Memory 2 Address Remap Low, Offset: 0x310
303 * Table 95: PCI_1 Memory 3 Address Remap Low, Offset: 0x318
304 *
305 * 11:00 Remap                  PCI IO/Memory Space Address Remap (31:20)
306 * 31:12 Reserved
307 */
308
309/*
310 * Table 81: PCI_0 Memory 0 Address Remap High, Offset: 0x320
311 * Table 83: PCI_0 Memory 1 Address Remap High, Offset: 0x328
312 * Table 85: PCI_0 Memory 2 Address Remap High, Offset: 0x330
313 * Table 87: PCI_0 Memory 3 Address Remap High, Offset: 0x338
314 * Table 90: PCI_1 Memory 0 Address Remap High, Offset: 0x340
315 * Table 92: PCI_1 Memory 1 Address Remap High, Offset: 0x348
316 * Table 94: PCI_1 Memory 2 Address Remap High, Offset: 0x350
317 * Table 96: PCI_1 Memory 3 Address Remap High, Offset: 0x358
318 *
319 * 31:00 Remap                  PCI Memory Address Remap (high 32 bits)
320 */
321
322/*
323 * Table 97: CPU Configuration, Offset: 0x000
324 * 07:00 NoMatchCnt             CPU Address Miss Counter
325 * 08:08 NoMatchCntEn           CPU Address Miss Counter Enable
326 *                              NOTE: Relevant only if multi-GT is enabled.
327 *                              (0: Disabled; 1: Enabled)
328 * 09:09 NoMatchCntExt          CPU address miss counter MSB
329 * 10:10 Reserved
330 * 11:11 AACKDelay              Address Acknowledge Delay
331 *                              0: AACK* is asserted one cycle after TS*.
332 *                              1: AACK* is asserted two cycles after TS*.
333 * 12:12 Endianess              Must be 0
334 *                              NOTE: The GT64260 does not support the PowerPC
335 *                                    Little Endian convention
336 * 13:13 Pipeline               Pipeline Enable
337 *                              0: Disabled. The GT64260 will not respond with
338 *                                 AACK* to a new CPU transaction, before the
339 *                                 previous transaction data phase completes.
340 *                              1: Enabled.
341 * 14:14 Reserved
342 * 15:15 TADelay                Transfer Acknowledge Delay
343 *                              0: TA* is asserted one cycle after AACK*
344 *                              1: TA* is asserted two cycles after AACK*
345 * 16:16 RdOOO                  Read Out of Order Completion
346 *                              0: Not Supported, Data is always returned in
347 *                                 order (DTI[0-2] is always driven
348 *                              1: Supported
349 * 17:17 StopRetry              Relevant only if PCI Retry is enabled
350 *                              0: Keep Retry all PCI transactions targeted
351 *                                 to the GT64260.
352 *                              1: Stop Retry of PCI transactions.
353 * 18:18 MultiGTDec             Multi-GT Address Decode
354 *                              0: Normal address decoding
355 *                              1: Multi-GT address decoding
356 * 19:19 DPValid                CPU DP[0-7] Connection.  CPU write parity ...
357 *                              0: is not checked. (Not connected)
358 *                              1: is checked (Connected)
359 * 21:20 Reserved
360 * 22:22 PErrProp               Parity Error Propagation
361 *                              0: GT64260 always drives good parity on
362 *                                 DP[0-7] during CPU reads.
363 *                              1: GT64260 drives bad parity on DP[0-7] in case
364 *                                 the read response from the target interface
365 *                                 comes with erroneous data indication
366 *                                 (e.g. ECC error from SDRAM interface).
367 * 25:23 Reserved
368 * 26:26 APValid                CPU AP[0-3] Connection.  CPU address parity ...
369 *                              0: is not checked. (Not connected)
370 *                              1: is checked (Connected)
371 * 27:27 RemapWrDis             Address Remap Registers Write Control
372 *                              0: Write to Low Address decode register.
373 *                                 Results in writing of the corresponding
374 *                                 Remap register.
375 *                              1: Write to Low Address decode register.  No
376 *                                 affect on the corresponding Remap register.
377 * 28:28 ConfSBDis              Configuration Read Sync Barrier Disable
378 *                              0: enabled; 1: disabled
379 * 29:29 IOSBDis                I/O Read Sync Barrier Disable
380 *                              0: enabled; 1: disabled
381 * 30:30 ClkSync                Clocks Synchronization
382 *                              0: The CPU interface is running with SysClk,
383 *                                 which is asynchronous to TClk.
384 *                              1: The CPU interface is running with TClk.
385 * 31:31 Reserved
386 */
387#define GT_CPUCfg_NoMatchCnt_GET(v)     GT__EXT((v), 0, 8)
388#define GT_CPUCfg_NoMatchCntEn          GT__BIT( 9)
389#define GT_CPUCfg_NoMatchCntExt         GT__BIT(10)
390#define GT_CPUCfg_AACKDelay             GT__BIT(11)
391#define GT_CPUCfg_Endianess             GT__BIT(12)
392#define GT_CPUCfg_Pipeline              GT__BIT(13)
393#define GT_CPUCfg_TADelay               GT__BIT(15)
394#define GT_CPUCfg_RdOOO                 GT__BIT(16)
395#define GT_CPUCfg_StopRetry             GT__BIT(17)
396#define GT_CPUCfg_MultiGTDec            GT__BIT(18)
397#define GT_CPUCfg_DPValid               GT__BIT(19)
398#define GT_CPUCfg_PErrProp              GT__BIT(22)
399#define GT_CPUCfg_APValid               GT__BIT(26)
400#define GT_CPUCfg_RemapWrDis            GT__BIT(27)
401#define GT_CPUCfg_ConfSBDis             GT__BIT(28)
402#define GT_CPUCfg_IOSBDis               GT__BIT(29)
403#define GT_CPUCfg_ClkSync               GT__BIT(30)
404
405/*
406 * Table 98: CPU Mode, Offset: 0x120, Read only
407 * 01:00 MultiGTID              Multi-GT ID
408 *                              Represents the ID to which the GT64260 responds
409 *                              to during a multi-GT address decoding period.
410 * 02:02 MultiGT                (0: Single; 1: Multiple) GT configuration
411 * 03:03 RetryEn                (0: Don't; 1: Do) Retry PCI transactions
412 * 07:04 CPUType
413 *                              0x0-0x3: Reserved
414 *                              0x4:     64-bit PowerPC CPU, 60x bus
415 *                              0x5:     64-bit PowerPC CPU, MPX bus
416 *                              0x6-0xf: Reserved
417 * 31:08 Reserved
418 */
419#define GT_CPUMode_MultiGTID_GET(v)     GT__EXT(v, 0, 2)
420#define GT_CPUMode_MultiGT              GT__BIT(2)
421#define GT_CPUMode_RetryEn              GT__BIT(3)
422#define GT_CPUMode_CPUType_GET(v)       GT__EXT(v, 4, 4)
423
424/*
425 * Table 99: CPU Master Control, Offset: 0x160
426 * 07:00 Reserved
427 * 08:08 IntArb                 CPU Bus Internal Arbiter Enable
428 *                              NOTE: Only relevant to 60x bus mode. When
429 *                                    running MPX bus, the GT64260 internal
430 *                                    arbiter must be used.
431 *                              0: Disabled.  External arbiter is required.
432 *                              1: Enabled.  Use the GT64260 CPU bus arbiter.
433 * 09:09 IntBusCtl              CPU Interface Unit Internal Bus Control
434 *                              NOTE: This bit must be set to 1. It is reserved
435 *                                    for Galileo Technology usage.
436 *                              0: Enable internal bus sharing between master
437 *                                 and slave interfaces.
438 *                              1: Disable internal bus sharing between master
439 *                                 and slave interfaces.
440 * 10:10 MWrTrig                Master Write Transaction Trigger
441 *                              0: With first valid write data
442 *                              1: With last valid write data
443 * 11:11 MRdTrig                Master Read Response Trigger
444 *                              0: With first valid read data
445 *                              1: With last valid read data
446 * 12:12 CleanBlock             Clean Block Snoop Transaction Support
447 *                              0: CPU does not support clean block (603e,750)
448 *                              1: CPU supports clean block (604e,G4)
449 * 13:13 FlushBlock             Flush Block Snoop Transaction Support
450 *                              0: CPU does not support flush block (603e,750)
451 *                              1: CPU supports flush block (604e,G4)
452 * 31:14 Reserved
453 */
454#define GT_CPUMstrCtl_IntArb                    GT__BIT(8)
455#define GT_CPUMstrCtl_IntBusCtl                 GT__BIT(9)
456#define GT_CPUMstrCtl_MWrTrig                   GT__BIT(10)
457#define GT_CPUMstrCtl_MRdTrig                   GT__BIT(11)
458#define GT_CPUMstrCtl_CleanBlock                GT__BIT(12)
459#define GT_CPUMstrCtl_FlushBlock                GT__BIT(13)
460
461#define GT_ArbSlice_SDRAM       0x0     /* SDRAM interface snoop request */
462#define GT_ArbSlice_DEVICE      0x1     /* Device request */
463#define GT_ArbSlice_NULL        0x2     /* NULL request */
464#define GT_ArbSlice_PCI0        0x3     /* PCI_0 access */
465#define GT_ArbSlice_PCI1        0x4     /* PCI_1 access */
466#define GT_ArbSlice_COMM        0x5     /* Comm unit access */
467#define GT_ArbSlice_IDMA0123    0x6     /* IDMA channels 0/1/2/3 access */
468#define GT_ArbSlice_IDMA4567    0x7     /* IDMA channels 4/5/6/7 access */
469                                        /* 0x8-0xf: Reserved */
470
471/* Pass in the slice number (from 0..16) as 'n'
472 */
473#define GT_XbarCtl_GET_ArbSlice(v, n)           GT__EXT((v), (((n) & 7)*4, 4)
474
475/*
476 * Table 100: CPU Interface Crossbar Control Low, Offset: 0x150
477 * 03:00 Arb0                   Slice  0 of CPU Master pizza Arbiter
478 * 07:04 Arb1                   Slice  1 of CPU Master pizza Arbiter
479 * 11:08 Arb2                   Slice  2 of CPU Master pizza Arbiter
480 * 15:12 Arb3                   Slice  3 of CPU Master pizza Arbiter
481 * 19:16 Arb4                   Slice  4 of CPU Master pizza Arbiter
482 * 23:20 Arb5                   Slice  5 of CPU Master pizza Arbiter
483 * 27:24 Arb6                   Slice  6 of CPU Master pizza Arbiter
484 * 31:28 Arb7                   Slice  7 of CPU Master pizza Arbiter
485 */
486
487/*
488 * Table 101: CPU Interface Crossbar Control High, Offset: 0x158
489 * 03:00 Arb8                   Slice  8 of CPU Master pizza Arbiter
490 * 07:04 Arb9                   Slice  9 of CPU Master pizza Arbiter
491 * 11:08 Arb10                  Slice 10 of CPU Master pizza Arbiter
492 * 15:12 Arb11                  Slice 11 of CPU Master pizza Arbiter
493 * 19:16 Arb12                  Slice 12 of CPU Master pizza Arbiter
494 * 23:20 Arb13                  Slice 13 of CPU Master pizza Arbiter
495 * 27:24 Arb14                  Slice 14 of CPU Master pizza Arbiter
496 * 31:28 Arb15                  Slice 15 of CPU Master pizza Arbiter
497 */
498
499/*
500 * Table 102: CPU Interface Crossbar Timeout, Offset: 0x168
501 * NOTE: Reserved for Galileo Technology usage.
502 * 07:00 Timeout                Crossbar Arbiter Timeout Preset Value
503 * 15:08 Reserved
504 * 16:16 TimeoutEn              Crossbar Arbiter Timer Enable
505 *                              (0: Enable; 1: Disable)
506 * 31:17 Reserved
507 */
508
509/*
510 * Table 103: CPU Read Response Crossbar Control Low, Offset: 0x170
511 * 03:00 Arb0                   Slice  0 of CPU Slave pizza Arbiter
512 * 07:04 Arb1                   Slice  1 of CPU Slave pizza Arbiter
513 * 11:08 Arb2                   Slice  2 of CPU Slave pizza Arbiter
514 * 15:12 Arb3                   Slice  3 of CPU Slave pizza Arbiter
515 * 19:16 Arb4                   Slice  4 of CPU Slave pizza Arbiter
516 * 23:20 Arb5                   Slice  5 of CPU Slave pizza Arbiter
517 * 27:24 Arb6                   Slice  6 of CPU Slave pizza Arbiter
518 * 31:28 Arb7                   Slice  7 of CPU Slave pizza Arbiter
519 */
520/*
521 * Table 104: CPU Read Response Crossbar Control High, Offset: 0x178
522 * 03:00 Arb8                   Slice  8 of CPU Slave pizza Arbiter
523 * 07:04 Arb9                   Slice  9 of CPU Slave pizza Arbiter
524 * 11:08 Arb10                  Slice 10 of CPU Slave pizza Arbiter
525 * 15:12 Arb11                  Slice 11 of CPU Slave pizza Arbiter
526 * 19:16 Arb12                  Slice 12 of CPU Slave pizza Arbiter
527 * 23:20 Arb13                  Slice 13 of CPU Slave pizza Arbiter
528 * 27:24 Arb14                  Slice 14 of CPU Slave pizza Arbiter
529 * 31:28 Arb15                  Slice 15 of CPU Slave pizza Arbiter
530 */ 
531
532/*
533 * Table 105: PCI_0 Sync Barrier Virtual Register, Offset: 0x0c0
534 * Table 106: PCI_1 Sync Barrier Virtual Register, Offset: 0x0c8
535 *   NOTE: The read data is random and should be ignored.
536 * 31:00 SyncBarrier            A CPU read from this register creates a
537 *                              synchronization barrier cycle.
538 */
539
540/*
541 * Table 107: CPU Protect Address 0 Low, Offset: 0x180
542 * Table 109: CPU Protect Address 1 Low, Offset: 0x190
543 * Table 111: CPU Protect Address 2 Low, Offset: 0x1a0
544 * Table 113: CPU Protect Address 3 Low, Offset: 0x1b0
545 * Table 115: CPU Protect Address 4 Low, Offset: 0x1c0
546 * Table 117: CPU Protect Address 5 Low, Offset: 0x1d0
547 * Table 119: CPU Protect Address 6 Low, Offset: 0x1e0
548 * Table 121: CPU Protect Address 7 Low, Offset: 0x1f0
549 *
550 * 11:00 LowAddr                CPU Protect Region Base Address
551 *                              Corresponds to address bits[31:20].
552 * 15:12 Reserved.              Must be 0
553 * 16:16 AccProtect             CPU Access Protect
554 *                              Access is (0: allowed; 1: forbidden)
555 * 17:17 WrProtect              CPU Write Protect
556 *                              Writes are (0: allowed; 1: forbidden)
557 * 18:18 CacheProtect           CPU caching protect.    Caching (block read)
558 *                              is (0: allowed; 1: forbidden)
559 * 31:19 Reserved
560 */
561#define GT_CPU_AccProtect                       GT__BIT(16)
562#define GT_CPU_WrProtect                        GT__BIT(17)
563#define GT_CPU_CacheProtect                     GT__BIT(18)
564
565/*
566 * Table 108: CPU Protect Address 0 High, Offset: 0x188
567 * Table 110: CPU Protect Address 1 High, Offset: 0x198
568 * Table 112: CPU Protect Address 2 High, Offset: 0x1a8
569 * Table 114: CPU Protect Address 3 High, Offset: 0x1b8
570 * Table 116: CPU Protect Address 4 High, Offset: 0x1c8
571 * Table 118: CPU Protect Address 5 High, Offset: 0x1d8
572 * Table 120: CPU Protect Address 6 High, Offset: 0x1e8
573 * Table 122: CPU Protect Address 7 High, Offset: 0x1f8
574 *
575 * 11:00 HighAddr               CPU Protect Region Top Address
576 *                              Corresponds to address bits[31:20]
577 * 31:12 Reserved
578 */
579
580/*
581 * Table 123: Snoop Base Address 0, Offset: 0x380
582 * Table 125: Snoop Base Address 1, Offset: 0x390
583 * Table 127: Snoop Base Address 2, Offset: 0x3a0
584 * Table 129: Snoop Base Address 3, Offset: 0x3b0
585 *
586 * 11:00 LowAddr                Snoop Region Base Address [31:20]
587 * 15:12 Reserved               Must be 0.
588 * 17:16 Snoop                  Snoop Type
589 *                              0x0: No Snoop
590 *                              0x1: Snoop to WT region
591 *                              0x2: Snoop to WB region
592 *                              0x3: Reserved
593 * 31:18 Reserved
594 */
595#define GT_Snoop_GET(v)                         GT__EXT((v), 16, 2)
596#define GT_Snoop_INS(v)                         GT__INS((v), 16)
597#define GT_Snoop_None                           0
598#define GT_Snoop_WT                             1
599#define GT_Snoop_WB                             2
600
601
602/*
603 * Table 124: Snoop Top Address 0, Offset: 0x388
604 * Table 126: Snoop Top Address 1, Offset: 0x398
605 * Table 128: Snoop Top Address 2, Offset: 0x3a8
606 * Table 130: Snoop Top Address 3, Offset: 0x3b8
607 * 11:00 HighAddr               Snoop Region Top Address [31:20]
608 * 31:12 Reserved
609 */
610
611
612/*
613 * Table 131: CPU Error Address Low, Offset: 0x070, Read Only.
614 *   In case of multiple errors, only the first one is latched.  New error
615 *   report latching is enabled only after the CPU Error Address Low register
616 *   is being read.
617 * 31:00 ErrAddr                Latched address bits [31:0] of a CPU
618 *                              transaction in case of:
619 *                              o illegal address (failed address decoding)
620 *                              o access protection violation
621 *                              o bad data parity
622 *                              o bad address parity
623 *                              Upon address latch, no new address are
624 *                              registered (due to additional error condition),
625 *                              until the register is being read.
626 */
627
628/*
629 * Table 132: CPU Error Address High, Offset: 0x078, Read Only.
630 *   Once data is latched, no new data can be registered (due to additional
631 *   error condition), until CPU Error Low Address is being read (which
632 *   implies, it should be the last being read by the interrupt handler).
633 * 03:00 Reserved
634 * 07:04 ErrPar                 Latched address parity bits in case
635 *                              of bad CPU address parity detection.
636 * 31:08 Reserved
637 */
638#define GT_CPUErrorAddrHigh_ErrPar_GET(v)       GT__EXT((v), 4, 4)
639
640/*
641 * Table 133: CPU Error Data Low, Offset: 0x128, Read only.
642 * 31:00 PErrData               Latched data bits [31:0] in case of bad data
643 *                              parity sampled on write transactions or on
644 *                              master read transactions.
645 */
646
647/*
648 * Table 134: CPU Error Data High, Offset: 0x130, Read only.
649 * 31:00 PErrData               Latched data bits [63:32] in case of bad data
650 *                              parity sampled on write transactions or on
651 *                              master read transactions.
652 */
653
654/*
655 * Table 135: CPU Error Parity, Offset: 0x138, Read only.
656 * 07:00 PErrPar                Latched data parity bus in case of bad data
657 *                              parity sampled on write transactions or on
658 *                              master read transactions.
659 * 31:10 Reserved
660 */
661#define GT_CPUErrorParity_PErrPar_GET(v)        GT__EXT((v), 0, 8)
662
663/*
664 * Table 136: CPU Error Cause, Offset: 0x140
665 *   Bits[7:0] are clear only. A cause bit is set upon an error condition
666 *   occurrence. Write a 0 value to clear the bit.  Writing a 1 value has
667 *   no affect.
668 * 00:00 AddrOut                CPU Address Out of Range
669 * 01:01 AddrPErr               Bad Address Parity Detected
670 * 02:02 TTErr                  Transfer Type Violation.
671 *                              The CPU attempts to burst (read or write) to an
672 *                              internal register.
673 * 03:03 AccErr                 Access to a Protected Region
674 * 04:04 WrErr                  Write to a Write Protected Region
675 * 05:05 CacheErr               Read from a Caching protected region
676 * 06:06 WrDataPErr             Bad Write Data Parity Detected
677 * 07:07 RdDataPErr             Bad Read Data Parity Detected
678 * 26:08 Reserved
679 * 31:27 Sel                    Specifies the error event currently being
680 *                              reported in Error Address, Error Data, and
681 *                              Error Parity registers.
682 *                              0x0: AddrOut
683 *                              0x1: AddrPErr
684 *                              0x2: TTErr
685 *                              0x3: AccErr
686 *                              0x4: WrErr
687 *                              0x5: CacheErr
688 *                              0x6: WrDataPErr
689 *                              0x7: RdDataPErr
690 *                              0x8-0x1f: Reserved
691 */
692#define GT_CPUError_AddrOut             GT__BIT(GT_CPUError_Sel_AddrOut)
693#define GT_CPUError_AddrPErr            GT__BIT(GT_CPUError_Sel_AddrPErr)
694#define GT_CPUError_TTErr               GT__BIT(GT_CPUError_Sel_TTErr)
695#define GT_CPUError_AccErr              GT__BIT(GT_CPUError_Sel_AccErr)
696#define GT_CPUError_WrErr               GT__BIT(GT_CPUError_Sel_WrPErr)
697#define GT_CPUError_CacheErr            GT__BIT(GT_CPUError_Sel_CachePErr)
698#define GT_CPUError_WrDataPErr          GT__BIT(GT_CPUError_Sel_WrDataPErr)
699#define GT_CPUError_RdDataPErr          GT__BIT(GT_CPUError_Sel_RdDataPErr)
700
701#define GT_CPUError_Sel_AddrOut         0
702#define GT_CPUError_Sel_AddrPErr        1
703#define GT_CPUError_Sel_TTErr           2
704#define GT_CPUError_Sel_AccErr          3
705#define GT_CPUError_Sel_WrErr           4
706#define GT_CPUError_Sel_CacheErr        5
707#define GT_CPUError_Sel_WrDataPErr      6
708#define GT_CPUError_Sel_RdDataPErr      7
709
710#define GT_CPUError_Sel_GET(v)          GT__EXT((v), 27, 5)
711
712/*
713 * Table 137: CPU Error Mask, Offset: 0x148
714 * 00:00 AddrOut                If set to 1, enables AddrOut interrupt.
715 * 01:01 AddrPErr               If set to 1, enables AddrPErr interrupt.
716 * 02:02 TTErr                  If set to 1, enables TTErr interrupt.
717 * 03:03 AccErr                 If set to 1, enables AccErr interrupt.
718 * 04:04 WrErr                  If set to 1, enables WrErr interrupt.
719 * 05:05 CacheErr               If set to 1, enables CacheErr interrupt.
720 * 06:06 WrDataPErr             If set to 1, enables WrDataPErr interrupt.
721 * 07:07 RdDataPErr             If set to 1, enables RdDataPErr interrupt.
722 * 31:08 Reserved
723 */
724
725/* Comm Unit Arbiter Control */
726#define GT_CommUnitArb_Ctrl     0xf300    /*<skf>*/
727/*
728 * Comm Unit Interrupt registers
729 */
730#define GT_CommUnitIntr_Cause   0xf310
731#define GT_CommUnitIntr_Mask    0xf314
732#define GT_CommUnitIntr_ErrAddr 0xf318
733
734#define GT_CommUnitIntr_E0      0x00000007
735#define GT_CommUnitIntr_E1      0x00000070
736#define GT_CommUnitIntr_E2      0x00000700
737#define GT_CommUnitIntr_S0      0x00070000
738#define GT_CommUnitIntr_S1      0x00700000
739#define GT_CommUnitIntr_Sel     0x70000000
740
741/*
742 * SDRAM Error Report (ECC) Registers
743 */
744#define GT_ECC_Data_Lo          0x484   /* latched Error Data (low) */
745#define GT_ECC_Data_Hi          0x480   /* latched Error Data (high) */
746#define GT_ECC_Addr             0x490   /* latched Error Address */
747#define GT_ECC_Rec              0x488   /* latched ECC code from SDRAM */
748#define GT_ECC_Calc             0x48c   /* latched ECC code from SDRAM */
749#define GT_ECC_Ctl              0x494   /* ECC Control */
750#define GT_ECC_Count            0x498   /* ECC 1-bit error count */
751
752/*
753 * Watchdog Registers
754 */
755#define GT_WDOG_Config          0xb410
756#define GT_WDOG_Value           0xb414
757#define GT_WDOG_Value_NMI       GT__MASK(24)
758#define GT_WDOG_Config_Preset   GT__MASK(24)
759#define GT_WDOG_Config_Ctl1a    GT__BIT(24)
760#define GT_WDOG_Config_Ctl1b    GT__BIT(25)
761#define GT_WDOG_Config_Ctl2a    GT__BIT(26)
762#define GT_WDOG_Config_Ctl2b    GT__BIT(27)
763#define GT_WDOG_Config_Enb      GT__BIT(31)
764
765#define GT_WDOG_NMI_DFLT        (GT__MASK(24) & GT_WDOG_Value_NMI)
766#define GT_WDOG_Preset_DFLT     (GT__MASK(22) & GT_WDOG_Config_Preset)
767
768/*
769 * Device Bus Interrupts
770 */
771#define GT_DEVBUS_ICAUSE        0x4d0   /* Device Interrupt Cause */
772#define GT_DEVBUS_IMASK         0x4d4   /* Device Interrupt Mask */
773#define GT_DEVBUS_ERR_ADDR      0x4d8   /* Device Error Address */
774
775/*
776 * bit defines for GT_DEVBUS_ICAUSE, GT_DEVBUS_IMASK
777 */
778#define GT_DEVBUS_DBurstErr     GT__BIT(0)
779#define GT_DEVBUS_DRdyErr       GT__BIT(1)
780#define GT_DEVBUS_Sel           GT__BIT(27)
781#define GT_DEVBUS_RES   ~(GT_DEVBUS_DBurstErr|GT_DEVBUS_DRdyErr|GT_DEVBUS_Sel)
782
783/* TWSI Interface - TWSI Interface Registers <skf> */
784#define TWSI_SLV_ADDR           0xc000
785#define TWSI_EXT_SLV_ADDR       0xc010
786#define TWSI_DATA               0xc004
787#define TWSI_CTRL               0xc008
788#define TWSI_STATUS             0xc00c
789#define TWSI_BAUDE_RATE         0xc00c
790#define TWSI_SFT_RST            0xc01c
791
792/* Interrupt Controller - Interrupt Controller Registers */
793/* Section 25.2 : Table 734 <skf> */
794
795#define GT_MAIN_INT_CAUSE_LO    0xc18 /* read Only */
796#define GT_MAIN_INT_CAUSE_HI   0xc68 /* read Only */
797#define GT_CPU_INT_MASK_LO      0xc1c
798#define GT_CPU_INT_MASK_HI      0xc6c
799#define GT_CPU_SEL_CAUSE        0xc70 /* read Only */
800#define GT_PCI0_INT_MASK_LO     0xc24
801#define GT_PCI0_INT_MASK_HI     0xc64
802#define GT_PCI0_SEL_CAUSE       0xc74 /* read Only */
803#define GT_PCI1_INT_MASK_LO     0xca4
804#define GT_PCI1_INT_MASK_HI     0xce4
805#define GT_PCI1_SEL_CAUSE       0xcf4 /* read Only */
806#define GT_CPU_INT0_MASK        0xe60
807#define GT_CPU_INT1_MASK        0xe64
808#define GT_CPU_INT2_MASK        0xe68
809#define GT_CPU_INT3_MASK        0xe6c
810
811#endif /* !_DISCOVERY_DEV_GTREG_H */
Note: See TracBrowser for help on using the repository browser.