source: rtems/c/src/lib/libbsp/powerpc/mvme3100/start/start.S @ 0c875c6a

4.115
Last change on this file since 0c875c6a was 0c875c6a, checked in by Joel Sherrill <joel.sherrill@…>, on 01/28/11 at 20:29:53

2011-01-28 Joel Sherrill <joel.sherrilL@…>

  • beatnik/include/bsp.h, beatnik/irq/irq.h, beatnik/pci/gt_pci_init.c, ep1a/console/polled_io.c, ep1a/irq/openpic_xxx_irq.c, gen5200/include/irq.h, gen5200/irq/irq.c, gen5200/startup/bspstart.c, haleakala/irq/irq.c, mbx8xx/irq/irq.c, mbx8xx/irq/irq.h, motorola_powerpc/include/bsp.h, mpc8260ads/irq/irq.c, mpc8260ads/irq/irq.h, mvme3100/include/bsp.h, mvme3100/irq/irq.h, mvme3100/start/start.S, mvme5500/include/bsp.h, mvme5500/irq/irq.h, psim/include/bsp.h, psim/include/coverhd.h, psim/irq/irq.h, psim/shmsupp/addrconv.c, psim/shmsupp/getcfg.c, psim/startup/linkcmds, psim/tools/psim-gdb-top.in, psim/tools/psim-top.in, psim/tools/runtest-top.in, qemuppc/irq/irq.h, score603e/irq/irq.c, shared/bootloader/bootldr.h, shared/bootloader/em86.c, shared/bootloader/em86real.S, shared/bootloader/exception.S, shared/bootloader/head.S, shared/bootloader/lib.c, shared/bootloader/misc.c, shared/bootloader/mm.c, shared/bootloader/pci.c, shared/console/console.c, shared/console/consoleIo.h, shared/console/inch.c, shared/console/keyboard.h, shared/console/polled_io.c, shared/irq/i8259.c, shared/irq/irq.h, shared/irq/openpic_i8259_irq.c, shared/motorola/motorola.c, shared/motorola/motorola.h, shared/openpic/openpic.c, shared/openpic/openpic.h, shared/pci/pci.c, shared/residual/residual.c, shared/start/start.S, ss555/irq/irq.h: Fix typo where license said found in found in.
  • Property mode set to 100644
File size: 2.3 KB
Line 
1/*
2 *  start.S :     RTEMS entry point
3 *
4 *  Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
5 *
6 *  The license and distribution terms for this file may be
7 *  found in the file LICENSE in this distribution or at
8 *  http://www.rtems.com/license/LICENSE.
9 *
10 *  Modified for mvme3100 by T. Straumann, 2007.
11 *
12 *  $Id$
13 *
14 */
15
16#include <rtems/asm.h>
17#include <rtems/score/cpu.h>
18#include <rtems/powerpc/powerpc.h>
19
20#include <bspopts.h>
21
22#define SYNC \
23        sync; \
24        isync
25
26#define KERNELBASE      0x0
27
28/* cannot include <bsp.h> from assembly :-( */
29#ifndef BSP_8540_CCSR_BASE
30#define BSP_8540_CCSR_BASE 0xe1000000
31#endif
32
33#define ERR_DISABLE_REG (BSP_8540_CCSR_BASE + 0x2e44)
34
35        .text
36        .globl  __rtems_entry_point
37        .type   __rtems_entry_point,@function
38__rtems_entry_point:
39        mr      r31,r3
40        mr      r30,r4
41        mr      r29,r5
42        mr      r28,r6
43        mr      r27,r7
44        /* disable checking for memory-select errors; motload has all TLBs
45         * mapping a possible larger area as memory (not-guarded, caching-enabled)
46         * than actual physical memory is available.
47         * In case of speculative loads this may cause 'memory-select' errors
48         * which seem to raise 'core_fault_in' (found no description in
49         * the manual but I experienced this problem).
50         * Such errors (if HID1[RFXE] is clear) may *stall* execution
51         * leading to mysterious 'hangs'.
52         * Note: enabling HID1[RFXE] at this point makes no sense since
53         *       exceptions are not configured yet. Therefore we disable
54         *       memory-select errors.
55         * Eventually (bspstart.c) we want to delete TLB entries for
56         * which no physical memory is present.
57         */
58        lis r3, ERR_DISABLE_REG@ha
59        lwz r4, ERR_DISABLE_REG@l(r3)
60        /* disable memory-select errors */
61        ori r4, r4, 1
62        stw r4, ERR_DISABLE_REG@l(r3)
63
64        /* Use MotLoad's TLB setup for now; caches are on already */
65        bl  __eabi      /* setup EABI and SYSV environment */
66        bl      zero_bss
67        /*
68         * restore original args
69         */
70        mr      r3,r31
71        mr      r4,r30
72        mr      r5,r29
73        mr      r6,r28
74        mr      r7,r27
75        bl      save_boot_params
76        addis   r9,r0, (__stack-PPC_MINIMUM_STACK_FRAME_SIZE)@ha
77        addi    r9,r9, (__stack-PPC_MINIMUM_STACK_FRAME_SIZE)@l
78        /* align down to 16-bytes */
79        li  r5, (CPU_STACK_ALIGNMENT - 1)
80        andc r1, r9, r5
81        /*
82         * We are now in a environment that is totally independent from
83         * bootloader setup.
84         */
85    /* pass result of 'save_boot_params' to 'boot_card' in R3 */
86        bl      boot_card
87        /* point of no return: reset board here ? */
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