source: rtems/c/src/lib/libbsp/powerpc/mpc8260ads/vectors/vectors.S @ 5edbffe

4.104.114.84.95
Last change on this file since 5edbffe was 5edbffe, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 22, 2001 at 2:46:02 PM

01-10-22 Andy Dachs <a.dachs@…>

  • mpc8260ads added as new BSP. tm27 reported not to run at this time.
  • ChangeLog?, Makefile.am, README, aclocal.m4, bsp_specs, clock/.cvsignore, clock/Makefile.am, clock/p_clock.c, configure.in, console/Makefile.am, console/console.c, include/Makefile.am, include/bsp.h, include/coverhd.h, irq/.cvsignore, irq/Makefile.am, irq/irq.c, irq/irq.h, irq/irq_asm.S, irq/irq_init.c, network/Makefile.am, network/README, network/if_hdlcsubr.c, network/if_hdlcsubr.h, network/network.c, start/Makefile.am, start/start.S, startup/Makefile.am, startup/bspstart.c, startup/cpuinit.c, startup/linkcmds, startup/setvec.c, times, vectors/.cvsignore, vectors/Makefile.am, vectors/vectors.S, vectors/vectors.h, vectors/vectors_init.c, wrapup/Makefile.am: New files.
  • Property mode set to 100644
File size: 2.8 KB
Line 
1/*
2 * (c) 1999, Eric Valette valette@crf.canon.fr
3 *
4 *
5 *  This file contains the assembly code for the PowerPC
6 *  exception veneers for RTEMS.
7 *
8 * $Id$
9 */
10       
11
12
13#include <bsp/vectors.h>
14#include <libcpu/cpu.h>
15#include <rtems/score/targopts.h>
16#include "asm.h"
17       
18
19#define SYNC \
20        sync; \
21        isync
22       
23        .text
24        .p2align 5     
25               
26PUBLIC_VAR(default_exception_vector_code_prolog)
27SYM (default_exception_vector_code_prolog):
28        /*
29         * let room for exception frame
30         */
31        stwu    r1, - (EXCEPTION_FRAME_END)(r1)
32        stw     r3, GPR3_OFFSET(r1)
33        stw     r2, GPR2_OFFSET(r1)
34        mflr    r2
35        stw     r2, EXC_LR_OFFSET(r1)
36        bl      0f
370:      /*
38         * r3 = exception vector entry point
39         * (256 * vector number) + few instructions
40         */
41        mflr    r3
42        /*
43         * r3 = r3 >> 8 = vector
44         */
45        srwi    r3,r3,8
46        ba      push_normalized_frame
47       
48        PUBLIC_VAR (default_exception_vector_code_prolog_size)
49       
50        default_exception_vector_code_prolog_size= . - default_exception_vector_code_prolog
51       
52        .p2align 5
53PUBLIC_VAR (push_normalized_frame)     
54SYM (push_normalized_frame):
55        stw     r3, EXCEPTION_NUMBER_OFFSET(r1)
56        stw     r0, GPR0_OFFSET(r1)
57        mfsrr0  r2
58        stw     r2, SRR0_FRAME_OFFSET(r1)
59        mfsrr1  r3
60        stw     r3, SRR1_FRAME_OFFSET(r1)
61        /*
62         * Save general purpose registers
63         * Already saved in prolog : R1, R2, R3, LR.
64         * Saved a few line above  : R0
65         *
66         * Manual says that "stmw" instruction may be slower than
67         * series of individual "stw" but who cares about performance
68         * for the DEFAULT exception handler?
69         */
70        stmw    r4, GPR4_OFFSET(r1)     /* save R4->R31 */
71
72        mfcr    r31
73        stw     r31,  EXC_CR_OFFSET(r1)
74        mfctr   r30
75        stw     r30,  EXC_CTR_OFFSET(r1)
76        mfxer   r28
77        stw     r28,  EXC_XER_OFFSET(r1)
78        /*
79         * compute SP at exception entry
80         */
81        addi    r2, r1, EXCEPTION_FRAME_END
82        /*
83         * store it at the right place
84         */
85        stw     r2, GPR1_OFFSET(r1)
86
87        /*
88         * Enable data and instruction address translation, exception nesting
89         */
90        mfmsr   r3
91        ori     r3,r3, MSR_RI /*| MSR_IR | MSR_DR*/
92        mtmsr   r3
93        SYNC
94       
95        /*
96         * Call C exception handler
97         */
98        /*
99         * store the execption frame address in r3 (first param)
100         */
101        addi    r3, r1, 0x8
102        /*
103         * globalExceptHdl(r3)
104         */
105        addis   r4, 0, globalExceptHdl@ha
106        lwz     r5, globalExceptHdl@l(r4)
107        mtlr    r5
108        blrl
109        /*
110         * Restore registers status
111         */
112        lwz     r31,  EXC_CR_OFFSET(r1)
113        mtcr    r31
114        lwz     r30,  EXC_CTR_OFFSET(r1)
115        mtctr   r30
116        lwz     r29,  EXC_LR_OFFSET(r1)
117        mtlr    r29
118        lwz     r28,  EXC_XER_OFFSET(r1)
119        mtxer   r28
120
121        lmw     r4, GPR4_OFFSET(r1)
122        lwz     r2, GPR2_OFFSET(r1)
123        lwz     r0, GPR0_OFFSET(r1)
124
125        /*
126         * Disable data and instruction translation. Make path non recoverable...
127         */
128        mfmsr   r3
129        xori    r3, r3, MSR_RI /*| MSR_IR | MSR_DR*/
130        mtmsr   r3
131        SYNC
132       
133        /*
134         * Restore rfi related settings
135         */
136                 
137        lwz     r3, SRR1_FRAME_OFFSET(r1)
138        mtsrr1  r3
139        lwz     r3, SRR0_FRAME_OFFSET(r1)
140        mtsrr0  r3
141       
142        lwz     r3, GPR3_OFFSET(r1)
143        addi    r1,r1, EXCEPTION_FRAME_END
144        SYNC
145        rfi
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