source: rtems/c/src/lib/libbsp/powerpc/mpc8260ads/startup/cpuinit.c @ d089d90

4.104.114.84.95
Last change on this file since d089d90 was 5edbffe, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 22, 2001 at 2:46:02 PM

01-10-22 Andy Dachs <a.dachs@…>

  • mpc8260ads added as new BSP. tm27 reported not to run at this time.
  • ChangeLog?, Makefile.am, README, aclocal.m4, bsp_specs, clock/.cvsignore, clock/Makefile.am, clock/p_clock.c, configure.in, console/Makefile.am, console/console.c, include/Makefile.am, include/bsp.h, include/coverhd.h, irq/.cvsignore, irq/Makefile.am, irq/irq.c, irq/irq.h, irq/irq_asm.S, irq/irq_init.c, network/Makefile.am, network/README, network/if_hdlcsubr.c, network/if_hdlcsubr.h, network/network.c, start/Makefile.am, start/start.S, startup/Makefile.am, startup/bspstart.c, startup/cpuinit.c, startup/linkcmds, startup/setvec.c, times, vectors/.cvsignore, vectors/Makefile.am, vectors/vectors.S, vectors/vectors.h, vectors/vectors_init.c, wrapup/Makefile.am: New files.
  • Property mode set to 100644
File size: 1.1 KB
Line 
1/*
2 *  cpuinit.c - this file contains functions for initializing the CPU
3 *
4 *  Written by Jay Monkman (jmonkman@frasca.com)
5 *
6 *  $Id$
7 */
8
9#include <bsp.h>
10
11/* Macros for handling all the MMU SPRs */
12#define PUT_IC_CST(r)   __asm__ volatile ("mtspr 0x230,%0\n" ::"r"(r))
13#define GET_IC_CST(r)   __asm__ volatile ("mfspr %0,0x230\n" :"=r"(r))
14#define PUT_DC_CST(r)   __asm__ volatile ("mtspr 0x238,%0\n" ::"r"(r))
15#define GET_DC_CST(r)   __asm__ volatile ("mfspr %0,0x238\n" :"=r"(r))
16
17void cpu_init(void)
18{
19  /* BRGCLK is VCO_OUT/4 */
20/*
21  m8260.sccr = 0;
22*/
23
24#if 0
25  register unsigned long t1, t2;
26
27  /* Let's clear MSR[IR] and MSR[DR] */
28  t2 = PPC_MSR_IR | PPC_MSR_DR;
29  __asm__ volatile (
30    "mfmsr    %0\n"
31    "andc     %0, %0, %1\n"
32    "mtmsr    %0\n" :"=r"(t1), "=r"(t2):
33    "1"(t2));
34 
35  t1 = M8xx_CACHE_CMD_UNLOCK;
36  /*  PUT_DC_CST(t1); */
37  PUT_IC_CST(t1);
38
39  t1 = M8xx_CACHE_CMD_INVALIDATE;
40  /*  PUT_DC_CST(t1); */
41  PUT_IC_CST(t1);
42
43  t1 = M8xx_CACHE_CMD_ENABLE;
44  PUT_IC_CST(t1);
45
46  t1 = M8xx_CACHE_CMD_SFWT;
47  /*  PUT_DC_CST(t1); */
48  t1 = M8xx_CACHE_CMD_ENABLE;
49  /*  PUT_DC_CST(t1);*/
50#endif
51}
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