4.104.114.84.95
Line | |
---|
1 | /* |
---|
2 | * cpuinit.c - this file contains functions for initializing the CPU |
---|
3 | * |
---|
4 | * Written by Jay Monkman (jmonkman@frasca.com) |
---|
5 | * |
---|
6 | * $Id$ |
---|
7 | */ |
---|
8 | |
---|
9 | #include <bsp.h> |
---|
10 | |
---|
11 | /* Macros for handling all the MMU SPRs */ |
---|
12 | #define PUT_IC_CST(r) __asm__ volatile ("mtspr 0x230,%0\n" ::"r"(r)) |
---|
13 | #define GET_IC_CST(r) __asm__ volatile ("mfspr %0,0x230\n" :"=r"(r)) |
---|
14 | #define PUT_DC_CST(r) __asm__ volatile ("mtspr 0x238,%0\n" ::"r"(r)) |
---|
15 | #define GET_DC_CST(r) __asm__ volatile ("mfspr %0,0x238\n" :"=r"(r)) |
---|
16 | |
---|
17 | void cpu_init(void) |
---|
18 | { |
---|
19 | /* BRGCLK is VCO_OUT/4 */ |
---|
20 | /* |
---|
21 | m8260.sccr = 0; |
---|
22 | */ |
---|
23 | |
---|
24 | #if 0 |
---|
25 | register unsigned long t1, t2; |
---|
26 | |
---|
27 | /* Let's clear MSR[IR] and MSR[DR] */ |
---|
28 | t2 = PPC_MSR_IR | PPC_MSR_DR; |
---|
29 | __asm__ volatile ( |
---|
30 | "mfmsr %0\n" |
---|
31 | "andc %0, %0, %1\n" |
---|
32 | "mtmsr %0\n" :"=r"(t1), "=r"(t2): |
---|
33 | "1"(t2)); |
---|
34 | |
---|
35 | t1 = M8xx_CACHE_CMD_UNLOCK; |
---|
36 | /* PUT_DC_CST(t1); */ |
---|
37 | PUT_IC_CST(t1); |
---|
38 | |
---|
39 | t1 = M8xx_CACHE_CMD_INVALIDATE; |
---|
40 | /* PUT_DC_CST(t1); */ |
---|
41 | PUT_IC_CST(t1); |
---|
42 | |
---|
43 | t1 = M8xx_CACHE_CMD_ENABLE; |
---|
44 | PUT_IC_CST(t1); |
---|
45 | |
---|
46 | t1 = M8xx_CACHE_CMD_SFWT; |
---|
47 | /* PUT_DC_CST(t1); */ |
---|
48 | t1 = M8xx_CACHE_CMD_ENABLE; |
---|
49 | /* PUT_DC_CST(t1);*/ |
---|
50 | #endif |
---|
51 | } |
---|
Note: See
TracBrowser
for help on using the repository browser.