1 | /* |
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2 | * This routine does the bulk of the system initialization. |
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3 | */ |
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4 | |
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5 | /* |
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6 | * The MPC860 specific stuff was written by Jay Monkman (jmonkman@frasca.com) |
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7 | * |
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8 | * Modified for the MPC8260ADS board by Andy Dachs <a.dachs@sstl.co.uk> |
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9 | * Surrey Satellite Technology Limited, 2001 |
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10 | * A 40MHz system clock is assumed. |
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11 | * The PON. RST.CONF. Dip switches (DS1) are |
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12 | * 1 - Off |
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13 | * 2 - On |
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14 | * 3 - Off |
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15 | * 4 - On |
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16 | * 5 - Off |
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17 | * 6 - Off |
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18 | * 7 - Off |
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19 | * 8 - Off |
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20 | * Dip switches on DS2 and DS3 are all set to ON |
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21 | * The LEDs on the board are used to signal panic and fatal_error |
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22 | * conditions. |
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23 | * The mmu is unused at this time. |
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24 | * |
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25 | * COPYRIGHT (c) 1989-2007. |
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26 | * On-Line Applications Research Corporation (OAR). |
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27 | * |
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28 | * The license and distribution terms for this file may be |
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29 | * found in the file LICENSE in this distribution or at |
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30 | * http://www.rtems.org/license/LICENSE. |
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31 | */ |
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32 | |
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33 | #include <bsp.h> |
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34 | #include <bsp/bootcard.h> |
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35 | |
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36 | /* |
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37 | #include <mmu.h> |
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38 | */ |
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39 | |
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40 | #include <mpc8260.h> |
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41 | #include <rtems/score/thread.h> |
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42 | #include <rtems/powerpc/powerpc.h> |
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43 | |
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44 | #include <rtems/bspIo.h> |
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45 | #include <rtems/counter.h> |
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46 | #include <bsp/irq.h> |
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47 | #include <libcpu/cpuIdent.h> |
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48 | #include <libcpu/spr.h> |
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49 | |
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50 | #include <string.h> |
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51 | |
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52 | #define UART1_E 0x02000002 /* bit 6 of BCSR1 */ |
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53 | #define UART2_E 0x01000001 /* bit 7 of BCSR1 */ |
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54 | |
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55 | #define GP0_LED 0x02000002 /* bit 6 of BCSR0 */ |
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56 | #define GP1_LED 0x01000001 /* bit 7 of BCSR0 */ |
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57 | |
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58 | SPR_RW(SPRG1) |
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59 | |
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60 | /* |
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61 | * Driver configuration parameters |
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62 | */ |
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63 | uint32_t bsp_clock_speed; |
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64 | uint32_t bsp_time_base_frequency; |
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65 | uint32_t bsp_clicks_per_usec; |
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66 | uint32_t bsp_serial_per_sec; /* Serial clocks per second */ |
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67 | bool bsp_serial_external_clock; |
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68 | bool bsp_serial_xon_xoff; |
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69 | bool bsp_serial_cts_rts; |
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70 | uint32_t bsp_serial_rate; |
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71 | uint32_t bsp_timer_average_overhead; /* Average overhead of timer in ticks */ |
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72 | uint32_t bsp_timer_least_valid; /* Least valid number from timer */ |
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73 | |
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74 | extern char IntrStack_start []; |
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75 | extern char intrStack []; |
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76 | |
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77 | static void _BSP_GPLED0_on(void) |
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78 | { |
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79 | BCSR *csr; |
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80 | csr = (BCSR *)(m8260.memc[1].br & 0xFFFF8000); |
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81 | csr->bcsr0 &= ~GP0_LED; /* Turn on GP0 LED */ |
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82 | } |
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83 | |
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84 | static void _BSP_GPLED0_off(void) |
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85 | { |
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86 | BCSR *csr; |
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87 | csr = (BCSR *)(m8260.memc[1].br & 0xFFFF8000); |
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88 | csr->bcsr0 |= GP0_LED; /* Turn off GP0 LED */ |
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89 | } |
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90 | |
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91 | static void _BSP_GPLED1_on(void) |
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92 | { |
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93 | BCSR *csr; |
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94 | csr = (BCSR *)(m8260.memc[1].br & 0xFFFF8000); |
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95 | csr->bcsr0 &= ~GP1_LED; /* Turn on GP1 LED */ |
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96 | } |
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97 | |
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98 | static void _BSP_GPLED1_off(void) |
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99 | { |
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100 | BCSR *csr; |
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101 | csr = (BCSR *)(m8260.memc[1].br & 0xFFFF8000); |
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102 | csr->bcsr0 |= GP1_LED; /* Turn off GP1 LED */ |
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103 | } |
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104 | |
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105 | static void _BSP_Uart1_enable(void) |
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106 | { |
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107 | BCSR *csr; |
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108 | csr = (BCSR *)(m8260.memc[1].br & 0xFFFF8000); |
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109 | csr->bcsr1 &= ~UART1_E; /* Enable Uart1 */ |
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110 | } |
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111 | |
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112 | static void _BSP_Uart2_enable(void) |
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113 | { |
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114 | BCSR *csr; |
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115 | csr = (BCSR *)(m8260.memc[1].br & 0xFFFF8000); |
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116 | csr->bcsr1 &= ~UART2_E; /* Enable Uart2 */ |
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117 | } |
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118 | |
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119 | void bsp_start(void) |
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120 | { |
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121 | /* Set MPC8260ADS board LEDS and Uart enable lines */ |
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122 | _BSP_GPLED0_off(); |
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123 | _BSP_GPLED1_off(); |
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124 | _BSP_Uart1_enable(); |
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125 | _BSP_Uart2_enable(); |
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126 | |
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127 | /* |
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128 | * Get CPU identification dynamically. Note that the get_ppc_cpu_type() |
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129 | * function stores the result in global variables so that it can be used |
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130 | * later... |
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131 | */ |
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132 | get_ppc_cpu_type(); |
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133 | get_ppc_cpu_revision(); |
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134 | |
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135 | cpu_init(); |
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136 | |
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137 | /* |
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138 | mmu_init(); |
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139 | */ |
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140 | |
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141 | /* Initialize exception handler */ |
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142 | /* FIXME: Interrupt stack begin and size */ |
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143 | ppc_exc_initialize( |
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144 | (uintptr_t) IntrStack_start, |
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145 | (uintptr_t) intrStack - (uintptr_t) IntrStack_start |
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146 | ); |
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147 | |
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148 | /* Initalize interrupt support */ |
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149 | bsp_interrupt_initialize(); |
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150 | |
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151 | /* |
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152 | mmu_init(); |
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153 | */ |
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154 | |
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155 | /* |
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156 | * Enable instruction and data caches. Do not force writethrough mode. |
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157 | */ |
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158 | #if BSP_INSTRUCTION_CACHE_ENABLED |
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159 | rtems_cache_enable_instruction(); |
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160 | #endif |
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161 | #if BSP_DATA_CACHE_ENABLED |
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162 | rtems_cache_enable_data(); |
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163 | #endif |
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164 | |
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165 | /* |
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166 | * initialize the device driver parameters |
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167 | */ |
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168 | bsp_time_base_frequency = 10000000; |
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169 | bsp_clicks_per_usec = 10; /* for 40MHz extclk */ |
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170 | bsp_serial_per_sec = 40000000; |
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171 | bsp_serial_external_clock = 0; |
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172 | bsp_serial_xon_xoff = 0; |
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173 | bsp_serial_cts_rts = 0; |
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174 | bsp_serial_rate = 9600; |
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175 | bsp_timer_average_overhead = 3; |
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176 | bsp_timer_least_valid = 3; |
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177 | bsp_clock_speed = 40000000; |
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178 | rtems_counter_initialize_converter(bsp_clock_speed); |
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179 | |
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180 | #ifdef REV_0_2 |
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181 | /* set up some board specific registers */ |
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182 | m8260.siumcr &= 0xF3FFFFFF; /* set TBEN ** BUG FIX ** */ |
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183 | m8260.siumcr |= 0x08000000; |
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184 | #endif |
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185 | |
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186 | /* use BRG1 to generate 32kHz timebase */ |
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187 | /* |
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188 | m8260.brgc1 = M8260_BRG_EN + (uint32_t)(((uint16_t)((40016384)/(32768)) - 1) << 1) + 0; |
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189 | */ |
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190 | |
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191 | #ifdef SHOW_MORE_INIT_SETTINGS |
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192 | printk("Exit from bspstart\n"); |
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193 | #endif |
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194 | |
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195 | } |
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