[5edbffe] | 1 | /* bsp_start() |
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| 2 | * |
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| 3 | * This routine starts the application. It includes application, |
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| 4 | * board, and monitor specific initialization and configuration. |
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| 5 | * The generic CPU dependent initialization has been performed |
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| 6 | * before this routine is invoked. |
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| 7 | * |
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| 8 | * The MPC860 specific stuff was written by Jay Monkman (jmonkman@frasca.com) |
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| 9 | * |
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| 10 | * Modified for the MPC8260ADS board by Andy Dachs <a.dachs@sstl.co.uk> |
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| 11 | * Surrey Satellite Technology Limited, 2001 |
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| 12 | * A 40MHz system clock is assumed. |
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| 13 | * The PON. RST.CONF. Dip switches (DS1) are |
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| 14 | * 1 - Off |
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| 15 | * 2 - On |
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| 16 | * 3 - Off |
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| 17 | * 4 - On |
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| 18 | * 5 - Off |
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| 19 | * 6 - Off |
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| 20 | * 7 - Off |
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| 21 | * 8 - Off |
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| 22 | * Dip switches on DS2 and DS3 are all set to ON |
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| 23 | * The LEDs on the board are used to signal panic and fatal_error |
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| 24 | * conditions. |
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| 25 | * The mmu is unused at this time. |
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| 26 | * |
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| 27 | * |
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[07e9642c] | 28 | * COPYRIGHT (c) 1989-2007. |
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[5edbffe] | 29 | * On-Line Applications Research Corporation (OAR). |
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| 30 | * |
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| 31 | * The license and distribution terms for this file may be |
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| 32 | * found in the file LICENSE in this distribution or at |
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[478277a] | 33 | * http://www.rtems.com/license/LICENSE. |
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[5edbffe] | 34 | */ |
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| 35 | |
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| 36 | #include <bsp.h> |
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| 37 | |
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| 38 | /* |
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| 39 | #include <mmu.h> |
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| 40 | */ |
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| 41 | |
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| 42 | #include <mpc8260.h> |
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| 43 | #include <rtems/score/thread.h> |
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[1899fe4] | 44 | #include <rtems/powerpc/powerpc.h> |
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| 45 | |
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[fb19f111] | 46 | #include <rtems/bspIo.h> |
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[ae1ce9be] | 47 | #include <bsp/irq.h> |
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[fb19f111] | 48 | #include <libcpu/cpuIdent.h> |
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[7b59de1c] | 49 | #include <libcpu/spr.h> |
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[5edbffe] | 50 | |
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| 51 | #include <string.h> |
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| 52 | |
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[7b59de1c] | 53 | SPR_RW(SPRG1) |
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[5edbffe] | 54 | |
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[07e9642c] | 55 | /* |
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| 56 | * Driver configuration parameters |
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| 57 | */ |
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| 58 | uint32_t bsp_clock_speed; |
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[8bb00ac] | 59 | uint32_t bsp_time_base_frequency; |
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[07e9642c] | 60 | uint32_t bsp_clicks_per_usec; |
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| 61 | uint32_t bsp_serial_per_sec; /* Serial clocks per second */ |
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[9f91d0f] | 62 | bool bsp_serial_external_clock; |
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| 63 | bool bsp_serial_xon_xoff; |
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| 64 | bool bsp_serial_cts_rts; |
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[07e9642c] | 65 | uint32_t bsp_serial_rate; |
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| 66 | uint32_t bsp_timer_average_overhead; /* Average overhead of timer in ticks */ |
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| 67 | uint32_t bsp_timer_least_valid; /* Least valid number from timer */ |
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[9f91d0f] | 68 | bool bsp_timer_internal_clock; /* TRUE, when timer runs with CPU clk */ |
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[07e9642c] | 69 | |
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[89fcd5ca] | 70 | void _BSP_GPLED1_on(void); |
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| 71 | void _BSP_GPLED0_on(void); |
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| 72 | void cpu_init(void); |
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[2d2de4eb] | 73 | |
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| 74 | extern char IntrStack_start []; |
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| 75 | extern char intrStack []; |
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[5edbffe] | 76 | |
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| 77 | void BSP_panic(char *s) |
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| 78 | { |
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| 79 | _BSP_GPLED1_on(); |
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| 80 | printk("%s PANIC %s\n",_RTEMS_version, s); |
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| 81 | __asm__ __volatile ("sc"); |
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| 82 | } |
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| 83 | |
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| 84 | void _BSP_Fatal_error(unsigned int v) |
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| 85 | { |
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| 86 | _BSP_GPLED0_on(); |
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| 87 | _BSP_GPLED1_on(); |
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| 88 | printk("%s PANIC ERROR %x\n",_RTEMS_version, v); |
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| 89 | __asm__ __volatile ("sc"); |
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| 90 | } |
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| 91 | |
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[e08dbc5] | 92 | void _BSP_GPLED0_on(void) |
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[5edbffe] | 93 | { |
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| 94 | BCSR *csr; |
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| 95 | csr = (BCSR *)(m8260.memc[1].br & 0xFFFF8000); |
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| 96 | csr->bcsr0 &= ~GP0_LED; /* Turn on GP0 LED */ |
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| 97 | } |
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| 98 | |
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[e08dbc5] | 99 | void _BSP_GPLED0_off(void) |
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[5edbffe] | 100 | { |
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| 101 | BCSR *csr; |
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| 102 | csr = (BCSR *)(m8260.memc[1].br & 0xFFFF8000); |
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| 103 | csr->bcsr0 |= GP0_LED; /* Turn off GP0 LED */ |
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| 104 | } |
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| 105 | |
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[e08dbc5] | 106 | void _BSP_GPLED1_on(void) |
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[5edbffe] | 107 | { |
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| 108 | BCSR *csr; |
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| 109 | csr = (BCSR *)(m8260.memc[1].br & 0xFFFF8000); |
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| 110 | csr->bcsr0 &= ~GP1_LED; /* Turn on GP1 LED */ |
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| 111 | } |
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| 112 | |
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[e08dbc5] | 113 | void _BSP_GPLED1_off(void) |
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[5edbffe] | 114 | { |
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| 115 | BCSR *csr; |
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| 116 | csr = (BCSR *)(m8260.memc[1].br & 0xFFFF8000); |
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| 117 | csr->bcsr0 |= GP1_LED; /* Turn off GP1 LED */ |
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| 118 | } |
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| 119 | |
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[e08dbc5] | 120 | void _BSP_Uart1_enable(void) |
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[5edbffe] | 121 | { |
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| 122 | BCSR *csr; |
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| 123 | csr = (BCSR *)(m8260.memc[1].br & 0xFFFF8000); |
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| 124 | csr->bcsr1 &= ~UART1_E; /* Enable Uart1 */ |
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| 125 | } |
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| 126 | |
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[e08dbc5] | 127 | void _BSP_Uart1_disable(void) |
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[5edbffe] | 128 | { |
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| 129 | BCSR *csr; |
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| 130 | csr = (BCSR *)(m8260.memc[1].br & 0xFFFF8000); |
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| 131 | csr->bcsr1 |= UART1_E; /* Disable Uart1 */ |
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| 132 | } |
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| 133 | |
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[e08dbc5] | 134 | void _BSP_Uart2_enable(void) |
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[5edbffe] | 135 | { |
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| 136 | BCSR *csr; |
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| 137 | csr = (BCSR *)(m8260.memc[1].br & 0xFFFF8000); |
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| 138 | csr->bcsr1 &= ~UART2_E; /* Enable Uart2 */ |
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| 139 | } |
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| 140 | |
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[e08dbc5] | 141 | void _BSP_Uart2_disable(void) |
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[5edbffe] | 142 | { |
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| 143 | BCSR *csr; |
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| 144 | csr = (BCSR *)(m8260.memc[1].br & 0xFFFF8000); |
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| 145 | csr->bcsr1 |= UART2_E; /* Disable Uart2 */ |
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| 146 | |
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| 147 | } |
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| 148 | |
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| 149 | void bsp_start(void) |
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| 150 | { |
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[2d2de4eb] | 151 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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[5edbffe] | 152 | ppc_cpu_id_t myCpu; |
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| 153 | ppc_cpu_revision_t myCpuRevision; |
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| 154 | |
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| 155 | /* Set MPC8260ADS board LEDS and Uart enable lines */ |
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| 156 | _BSP_GPLED0_off(); |
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| 157 | _BSP_GPLED1_off(); |
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| 158 | _BSP_Uart1_enable(); |
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| 159 | _BSP_Uart2_enable(); |
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| 160 | |
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| 161 | /* |
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| 162 | * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function |
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| 163 | * store the result in global variables so that it can be used latter... |
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| 164 | */ |
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| 165 | myCpu = get_ppc_cpu_type(); |
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| 166 | myCpuRevision = get_ppc_cpu_revision(); |
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| 167 | |
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| 168 | cpu_init(); |
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| 169 | |
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| 170 | /* |
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| 171 | mmu_init(); |
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| 172 | */ |
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| 173 | |
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[2d2de4eb] | 174 | /* Initialize exception handler */ |
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| 175 | /* FIXME: Interrupt stack begin and size */ |
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| 176 | sc = ppc_exc_initialize( |
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| 177 | PPC_INTERRUPT_DISABLE_MASK_DEFAULT, |
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| 178 | (uintptr_t) IntrStack_start, |
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| 179 | (uintptr_t) intrStack - (uintptr_t) IntrStack_start |
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| 180 | ); |
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| 181 | if (sc != RTEMS_SUCCESSFUL) { |
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| 182 | BSP_panic("cannot intitialize exceptions"); |
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| 183 | } |
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[5edbffe] | 184 | |
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[2d2de4eb] | 185 | /* Initalize interrupt support */ |
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[dd8df59] | 186 | bsp_interrupt_initialize(); |
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[5edbffe] | 187 | |
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| 188 | /* |
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| 189 | mmu_init(); |
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| 190 | */ |
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[6128a4a] | 191 | |
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[5edbffe] | 192 | /* |
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| 193 | * Enable instruction and data caches. Do not force writethrough mode. |
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| 194 | */ |
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[353be08] | 195 | #if BSP_INSTRUCTION_CACHE_ENABLED |
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[5edbffe] | 196 | rtems_cache_enable_instruction(); |
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| 197 | #endif |
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[353be08] | 198 | #if BSP_DATA_CACHE_ENABLED |
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[5edbffe] | 199 | rtems_cache_enable_data(); |
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| 200 | #endif |
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| 201 | |
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| 202 | /* |
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[cafa2c5] | 203 | * initialize the device driver parameters |
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[5edbffe] | 204 | */ |
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[8bb00ac] | 205 | bsp_time_base_frequency = 10000000; |
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[45550867] | 206 | bsp_clicks_per_usec = 10; /* for 40MHz extclk */ |
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| 207 | bsp_serial_per_sec = 40000000; |
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[07e9642c] | 208 | bsp_serial_external_clock = 0; |
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[45550867] | 209 | bsp_serial_xon_xoff = 0; |
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| 210 | bsp_serial_cts_rts = 0; |
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| 211 | bsp_serial_rate = 9600; |
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[07e9642c] | 212 | bsp_timer_average_overhead = 3; |
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[45550867] | 213 | bsp_timer_least_valid = 3; |
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[07e9642c] | 214 | bsp_clock_speed = 40000000; |
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[5edbffe] | 215 | |
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| 216 | #ifdef REV_0_2 |
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| 217 | /* set up some board specific registers */ |
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| 218 | m8260.siumcr &= 0xF3FFFFFF; /* set TBEN ** BUG FIX ** */ |
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| 219 | m8260.siumcr |= 0x08000000; |
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| 220 | #endif |
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| 221 | |
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| 222 | /* use BRG1 to generate 32kHz timebase */ |
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| 223 | /* |
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[2a832d8] | 224 | m8260.brgc1 = M8260_BRG_EN + (uint32_t)(((uint16_t)((40016384)/(32768)) - 1) << 1) + 0; |
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[5edbffe] | 225 | */ |
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| 226 | |
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| 227 | #ifdef SHOW_MORE_INIT_SETTINGS |
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| 228 | printk("Exit from bspstart\n"); |
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| 229 | #endif |
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| 230 | |
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| 231 | } |
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