source: rtems/c/src/lib/libbsp/powerpc/mpc8260ads/startup/bspstart.c @ dd8df59

4.115
Last change on this file since dd8df59 was dd8df59, checked in by Sebastian Huber <sebastian.huber@…>, on 11/14/12 at 12:59:27

bsps: Interrupt initialization error is fatal

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File size: 5.3 KB
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[5edbffe]1/*  bsp_start()
2 *
3 *  This routine starts the application.  It includes application,
4 *  board, and monitor specific initialization and configuration.
5 *  The generic CPU dependent initialization has been performed
6 *  before this routine is invoked.
7 *
8 *  The MPC860 specific stuff was written by Jay Monkman (jmonkman@frasca.com)
9 *
10 *  Modified for the MPC8260ADS board by Andy Dachs <a.dachs@sstl.co.uk>
11 *  Surrey Satellite Technology Limited, 2001
12 *  A 40MHz system clock is assumed.
13 *  The PON. RST.CONF. Dip switches (DS1) are
14 *  1 - Off
15 *  2 - On
16 *  3 - Off
17 *  4 - On
18 *  5 - Off
19 *  6 - Off
20 *  7 - Off
21 *  8 - Off
22 *  Dip switches on DS2 and DS3 are all set to ON
23 *  The LEDs on the board are used to signal panic and fatal_error
24 *  conditions.
25 *  The mmu is unused at this time.
26 *
27 *
[07e9642c]28 *  COPYRIGHT (c) 1989-2007.
[5edbffe]29 *  On-Line Applications Research Corporation (OAR).
30 *
31 *  The license and distribution terms for this file may be
32 *  found in the file LICENSE in this distribution or at
[478277a]33 *  http://www.rtems.com/license/LICENSE.
[5edbffe]34 */
35
36#include <bsp.h>
37
38/*
39#include <mmu.h>
40*/
41
42#include <mpc8260.h>
43#include <rtems/score/thread.h>
[1899fe4]44#include <rtems/powerpc/powerpc.h>
45
[fb19f111]46#include <rtems/bspIo.h>
[ae1ce9be]47#include <bsp/irq.h>
[fb19f111]48#include <libcpu/cpuIdent.h>
[7b59de1c]49#include <libcpu/spr.h>
[5edbffe]50
51#include <string.h>
52
[7b59de1c]53SPR_RW(SPRG1)
[5edbffe]54
[07e9642c]55/*
56 *  Driver configuration parameters
57 */
58uint32_t   bsp_clock_speed;
[8bb00ac]59uint32_t   bsp_time_base_frequency;
[07e9642c]60uint32_t   bsp_clicks_per_usec;
61uint32_t   bsp_serial_per_sec;         /* Serial clocks per second */
[9f91d0f]62bool       bsp_serial_external_clock;
63bool       bsp_serial_xon_xoff;
64bool       bsp_serial_cts_rts;
[07e9642c]65uint32_t   bsp_serial_rate;
66uint32_t   bsp_timer_average_overhead; /* Average overhead of timer in ticks */
67uint32_t   bsp_timer_least_valid;      /* Least valid number from timer      */
[9f91d0f]68bool       bsp_timer_internal_clock;   /* TRUE, when timer runs with CPU clk */
[07e9642c]69
[89fcd5ca]70void  _BSP_GPLED1_on(void);
71void  _BSP_GPLED0_on(void);
72void  cpu_init(void);
[2d2de4eb]73
74extern char IntrStack_start [];
75extern char intrStack [];
[5edbffe]76
77void BSP_panic(char *s)
78{
79  _BSP_GPLED1_on();
80  printk("%s PANIC %s\n",_RTEMS_version, s);
81  __asm__ __volatile ("sc");
82}
83
84void _BSP_Fatal_error(unsigned int v)
85{
86  _BSP_GPLED0_on();
87  _BSP_GPLED1_on();
88  printk("%s PANIC ERROR %x\n",_RTEMS_version, v);
89  __asm__ __volatile ("sc");
90}
91
[e08dbc5]92void _BSP_GPLED0_on(void)
[5edbffe]93{
94  BCSR *csr;
95  csr = (BCSR *)(m8260.memc[1].br & 0xFFFF8000);
96  csr->bcsr0 &=  ~GP0_LED;              /* Turn on GP0 LED */
97}
98
[e08dbc5]99void _BSP_GPLED0_off(void)
[5edbffe]100{
101  BCSR *csr;
102  csr = (BCSR *)(m8260.memc[1].br & 0xFFFF8000);
103  csr->bcsr0 |=  GP0_LED;               /* Turn off GP0 LED */
104}
105
[e08dbc5]106void _BSP_GPLED1_on(void)
[5edbffe]107{
108  BCSR *csr;
109  csr = (BCSR *)(m8260.memc[1].br & 0xFFFF8000);
110  csr->bcsr0 &=  ~GP1_LED;              /* Turn on GP1 LED */
111}
112
[e08dbc5]113void _BSP_GPLED1_off(void)
[5edbffe]114{
115  BCSR *csr;
116  csr = (BCSR *)(m8260.memc[1].br & 0xFFFF8000);
117  csr->bcsr0 |=  GP1_LED;               /* Turn off GP1 LED */
118}
119
[e08dbc5]120void _BSP_Uart1_enable(void)
[5edbffe]121{
122  BCSR *csr;
123  csr = (BCSR *)(m8260.memc[1].br & 0xFFFF8000);
124  csr->bcsr1 &= ~UART1_E;               /* Enable Uart1 */
125}
126
[e08dbc5]127void _BSP_Uart1_disable(void)
[5edbffe]128{
129  BCSR *csr;
130  csr = (BCSR *)(m8260.memc[1].br & 0xFFFF8000);
131  csr->bcsr1 |=  UART1_E;               /* Disable Uart1 */
132}
133
[e08dbc5]134void _BSP_Uart2_enable(void)
[5edbffe]135{
136  BCSR *csr;
137  csr = (BCSR *)(m8260.memc[1].br & 0xFFFF8000);
138  csr->bcsr1 &= ~UART2_E;               /* Enable Uart2 */
139}
140
[e08dbc5]141void _BSP_Uart2_disable(void)
[5edbffe]142{
143  BCSR *csr;
144  csr = (BCSR *)(m8260.memc[1].br & 0xFFFF8000);
145  csr->bcsr1 |=  UART2_E;               /* Disable Uart2 */
146
147}
148
149void bsp_start(void)
150{
[2d2de4eb]151  rtems_status_code sc = RTEMS_SUCCESSFUL;
[5edbffe]152  ppc_cpu_id_t myCpu;
153  ppc_cpu_revision_t myCpuRevision;
154
155  /* Set MPC8260ADS board LEDS and Uart enable lines */
156  _BSP_GPLED0_off();
157  _BSP_GPLED1_off();
158  _BSP_Uart1_enable();
159  _BSP_Uart2_enable();
160
161  /*
162   * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function
163   * store the result in global variables so that it can be used latter...
164   */
165  myCpu         = get_ppc_cpu_type();
166  myCpuRevision = get_ppc_cpu_revision();
167
168  cpu_init();
169
170/*
171  mmu_init();
172*/
173
[2d2de4eb]174  /* Initialize exception handler */
175  /* FIXME: Interrupt stack begin and size */
176  sc = ppc_exc_initialize(
177    PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
178    (uintptr_t) IntrStack_start,
179    (uintptr_t) intrStack - (uintptr_t) IntrStack_start
180  );
181  if (sc != RTEMS_SUCCESSFUL) {
182    BSP_panic("cannot intitialize exceptions");
183  }
[5edbffe]184
[2d2de4eb]185  /* Initalize interrupt support */
[dd8df59]186  bsp_interrupt_initialize();
[5edbffe]187
188/*
189  mmu_init();
190*/
[6128a4a]191
[5edbffe]192  /*
193   * Enable instruction and data caches. Do not force writethrough mode.
194   */
[353be08]195#if BSP_INSTRUCTION_CACHE_ENABLED
[5edbffe]196  rtems_cache_enable_instruction();
197#endif
[353be08]198#if BSP_DATA_CACHE_ENABLED
[5edbffe]199  rtems_cache_enable_data();
200#endif
201
202  /*
[cafa2c5]203   *  initialize the device driver parameters
[5edbffe]204   */
[8bb00ac]205  bsp_time_base_frequency    = 10000000;
[45550867]206  bsp_clicks_per_usec        = 10;  /* for 40MHz extclk */
207  bsp_serial_per_sec         = 40000000;
[07e9642c]208  bsp_serial_external_clock  = 0;
[45550867]209  bsp_serial_xon_xoff        = 0;
210  bsp_serial_cts_rts         = 0;
211  bsp_serial_rate            = 9600;
[07e9642c]212  bsp_timer_average_overhead = 3;
[45550867]213  bsp_timer_least_valid    = 3;
[07e9642c]214  bsp_clock_speed          = 40000000;
[5edbffe]215
216#ifdef REV_0_2
217  /* set up some board specific registers */
218  m8260.siumcr &= 0xF3FFFFFF;           /* set TBEN ** BUG FIX ** */
219  m8260.siumcr |= 0x08000000;
220#endif
221
222  /* use BRG1 to generate 32kHz timebase */
223/*
[2a832d8]224  m8260.brgc1 = M8260_BRG_EN + (uint32_t)(((uint16_t)((40016384)/(32768)) - 1) << 1) + 0;
[5edbffe]225*/
226
227#ifdef SHOW_MORE_INIT_SETTINGS
228  printk("Exit from bspstart\n");
229#endif
230
231}
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