[5edbffe] | 1 | /* bsp_start() |
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| 2 | * |
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| 3 | * This routine starts the application. It includes application, |
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| 4 | * board, and monitor specific initialization and configuration. |
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| 5 | * The generic CPU dependent initialization has been performed |
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| 6 | * before this routine is invoked. |
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| 7 | * |
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| 8 | * The MPC860 specific stuff was written by Jay Monkman (jmonkman@frasca.com) |
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| 9 | * |
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| 10 | * Modified for the MPC8260ADS board by Andy Dachs <a.dachs@sstl.co.uk> |
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| 11 | * Surrey Satellite Technology Limited, 2001 |
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| 12 | * A 40MHz system clock is assumed. |
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| 13 | * The PON. RST.CONF. Dip switches (DS1) are |
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| 14 | * 1 - Off |
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| 15 | * 2 - On |
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| 16 | * 3 - Off |
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| 17 | * 4 - On |
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| 18 | * 5 - Off |
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| 19 | * 6 - Off |
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| 20 | * 7 - Off |
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| 21 | * 8 - Off |
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| 22 | * Dip switches on DS2 and DS3 are all set to ON |
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| 23 | * The LEDs on the board are used to signal panic and fatal_error |
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| 24 | * conditions. |
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| 25 | * The mmu is unused at this time. |
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| 26 | * |
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| 27 | * |
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[07e9642c] | 28 | * COPYRIGHT (c) 1989-2007. |
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[5edbffe] | 29 | * On-Line Applications Research Corporation (OAR). |
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| 30 | * |
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| 31 | * The license and distribution terms for this file may be |
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| 32 | * found in the file LICENSE in this distribution or at |
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[478277a] | 33 | * http://www.rtems.com/license/LICENSE. |
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[5edbffe] | 34 | * |
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| 35 | * $Id$ |
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| 36 | */ |
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| 37 | |
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| 38 | #include <bsp.h> |
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| 39 | |
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| 40 | /* |
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| 41 | #include <mmu.h> |
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| 42 | */ |
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| 43 | |
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| 44 | #include <mpc8260.h> |
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| 45 | #include <rtems/libio.h> |
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| 46 | #include <rtems/libcsupport.h> |
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| 47 | #include <rtems/score/thread.h> |
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[1899fe4] | 48 | #include <rtems/powerpc/powerpc.h> |
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| 49 | |
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[fb19f111] | 50 | #include <rtems/bspIo.h> |
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| 51 | #include <libcpu/cpuIdent.h> |
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[7b59de1c] | 52 | #include <libcpu/spr.h> |
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[5edbffe] | 53 | |
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| 54 | #include <string.h> |
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| 55 | |
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| 56 | #ifdef STACK_CHECKER_ON |
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| 57 | #include <stackchk.h> |
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| 58 | #endif |
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| 59 | |
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[7b59de1c] | 60 | SPR_RW(SPRG0) |
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| 61 | SPR_RW(SPRG1) |
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[5edbffe] | 62 | |
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| 63 | /* |
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| 64 | * The original table from the application (in ROM) and our copy of it with |
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| 65 | * some changes. Configuration is defined in <confdefs.h>. Make sure that |
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| 66 | * our configuration tables are uninitialized so that they get allocated in |
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| 67 | * the .bss section (RAM). |
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| 68 | */ |
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| 69 | extern rtems_configuration_table Configuration; |
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| 70 | extern unsigned long intrStackPtr; |
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| 71 | rtems_configuration_table BSP_Configuration; |
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| 72 | |
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| 73 | rtems_cpu_table Cpu_table; |
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| 74 | |
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| 75 | char *rtems_progname; |
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| 76 | |
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[07e9642c] | 77 | /* |
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| 78 | * Driver configuration parameters |
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| 79 | */ |
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| 80 | uint32_t bsp_clock_speed; |
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| 81 | uint32_t bsp_clicks_per_usec; |
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| 82 | uint32_t bsp_serial_per_sec; /* Serial clocks per second */ |
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| 83 | boolean bsp_serial_external_clock; |
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| 84 | boolean bsp_serial_xon_xoff; |
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| 85 | boolean bsp_serial_cts_rts; |
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| 86 | uint32_t bsp_serial_rate; |
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| 87 | uint32_t bsp_timer_average_overhead; /* Average overhead of timer in ticks */ |
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| 88 | uint32_t bsp_timer_least_valid; /* Least valid number from timer */ |
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| 89 | boolean bsp_timer_internal_clock; /* TRUE, when timer runs with CPU clk */ |
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| 90 | |
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[5edbffe] | 91 | /* |
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| 92 | * Use the shared implementations of the following routines. |
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| 93 | * Look in rtems/c/src/lib/libbsp/shared/bsppost.c and |
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| 94 | * rtems/c/src/lib/libbsp/shared/bsplibc.c. |
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| 95 | */ |
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| 96 | void bsp_postdriver_hook(void); |
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[2a832d8] | 97 | void bsp_libc_init( void *, uint32_t, int ); |
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[5edbffe] | 98 | |
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[89fcd5ca] | 99 | void _BSP_GPLED1_on(void); |
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| 100 | void _BSP_GPLED0_on(void); |
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| 101 | void cpu_init(void); |
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| 102 | void initialize_exceptions(void); |
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[5edbffe] | 103 | |
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| 104 | void BSP_panic(char *s) |
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| 105 | { |
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| 106 | _BSP_GPLED1_on(); |
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| 107 | printk("%s PANIC %s\n",_RTEMS_version, s); |
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| 108 | __asm__ __volatile ("sc"); |
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| 109 | } |
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| 110 | |
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| 111 | void _BSP_Fatal_error(unsigned int v) |
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| 112 | { |
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| 113 | _BSP_GPLED0_on(); |
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| 114 | _BSP_GPLED1_on(); |
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| 115 | printk("%s PANIC ERROR %x\n",_RTEMS_version, v); |
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| 116 | __asm__ __volatile ("sc"); |
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| 117 | } |
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| 118 | |
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| 119 | void _BSP_GPLED0_on() |
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| 120 | { |
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| 121 | BCSR *csr; |
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| 122 | csr = (BCSR *)(m8260.memc[1].br & 0xFFFF8000); |
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| 123 | csr->bcsr0 &= ~GP0_LED; /* Turn on GP0 LED */ |
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| 124 | } |
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| 125 | |
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| 126 | void _BSP_GPLED0_off() |
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| 127 | { |
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| 128 | BCSR *csr; |
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| 129 | csr = (BCSR *)(m8260.memc[1].br & 0xFFFF8000); |
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| 130 | csr->bcsr0 |= GP0_LED; /* Turn off GP0 LED */ |
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| 131 | } |
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| 132 | |
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| 133 | void _BSP_GPLED1_on() |
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| 134 | { |
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| 135 | BCSR *csr; |
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| 136 | csr = (BCSR *)(m8260.memc[1].br & 0xFFFF8000); |
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| 137 | csr->bcsr0 &= ~GP1_LED; /* Turn on GP1 LED */ |
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| 138 | } |
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| 139 | |
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| 140 | void _BSP_GPLED1_off() |
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| 141 | { |
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| 142 | BCSR *csr; |
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| 143 | csr = (BCSR *)(m8260.memc[1].br & 0xFFFF8000); |
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| 144 | csr->bcsr0 |= GP1_LED; /* Turn off GP1 LED */ |
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| 145 | } |
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| 146 | |
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| 147 | void _BSP_Uart1_enable() |
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| 148 | { |
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| 149 | BCSR *csr; |
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| 150 | csr = (BCSR *)(m8260.memc[1].br & 0xFFFF8000); |
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| 151 | csr->bcsr1 &= ~UART1_E; /* Enable Uart1 */ |
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| 152 | } |
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| 153 | |
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| 154 | void _BSP_Uart1_disable() |
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| 155 | { |
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| 156 | BCSR *csr; |
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| 157 | csr = (BCSR *)(m8260.memc[1].br & 0xFFFF8000); |
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| 158 | csr->bcsr1 |= UART1_E; /* Disable Uart1 */ |
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| 159 | } |
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| 160 | |
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| 161 | void _BSP_Uart2_enable() |
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| 162 | { |
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| 163 | BCSR *csr; |
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| 164 | csr = (BCSR *)(m8260.memc[1].br & 0xFFFF8000); |
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| 165 | csr->bcsr1 &= ~UART2_E; /* Enable Uart2 */ |
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| 166 | } |
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| 167 | |
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| 168 | void _BSP_Uart2_disable() |
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| 169 | { |
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| 170 | BCSR *csr; |
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| 171 | csr = (BCSR *)(m8260.memc[1].br & 0xFFFF8000); |
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| 172 | csr->bcsr1 |= UART2_E; /* Disable Uart2 */ |
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| 173 | |
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| 174 | } |
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| 175 | |
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| 176 | extern void m8260_console_reserve_resources(rtems_configuration_table *); |
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| 177 | |
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| 178 | /* |
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| 179 | * Function: bsp_pretasking_hook |
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| 180 | * Created: 95/03/10 |
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| 181 | * |
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| 182 | * Description: |
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| 183 | * BSP pretasking hook. Called just before drivers are initialized. |
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| 184 | * Used to setup libc and install any BSP extensions. |
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| 185 | * |
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| 186 | * NOTES: |
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| 187 | * Must not use libc (to do io) from here, since drivers are |
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| 188 | * not yet initialized. |
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| 189 | * |
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| 190 | */ |
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[6128a4a] | 191 | |
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[5edbffe] | 192 | void |
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| 193 | bsp_pretasking_hook(void) |
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| 194 | { |
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[6128a4a] | 195 | /* |
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[5edbffe] | 196 | * These are assigned addresses in the linkcmds file for the BSP. This |
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| 197 | * approach is better than having these defined as manifest constants and |
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| 198 | * compiled into the kernel, but it is still not ideal when dealing with |
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| 199 | * multiprocessor configuration in which each board as a different memory |
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| 200 | * map. A better place for defining these symbols might be the makefiles. |
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| 201 | * Consideration should also be given to developing an approach in which |
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| 202 | * the kernel and the application can be linked and burned into ROM |
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| 203 | * independently of each other. |
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| 204 | */ |
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| 205 | extern unsigned char _HeapStart; |
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| 206 | extern unsigned char _HeapEnd; |
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| 207 | |
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| 208 | bsp_libc_init( &_HeapStart, &_HeapEnd - &_HeapStart, 0 ); |
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| 209 | |
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| 210 | #ifdef STACK_CHECKER_ON |
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| 211 | /* |
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| 212 | * Initialize the stack bounds checker |
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| 213 | * We can either turn it on here or from the app. |
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| 214 | */ |
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[6128a4a] | 215 | |
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[5edbffe] | 216 | Stack_check_Initialize(); |
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| 217 | #endif |
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[6128a4a] | 218 | |
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[5edbffe] | 219 | #ifdef RTEMS_DEBUG |
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| 220 | rtems_debug_enable( RTEMS_DEBUG_ALL_MASK ); |
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| 221 | #endif |
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| 222 | } |
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| 223 | |
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| 224 | void bsp_start(void) |
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| 225 | { |
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| 226 | extern void *_WorkspaceBase; |
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| 227 | ppc_cpu_id_t myCpu; |
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| 228 | ppc_cpu_revision_t myCpuRevision; |
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| 229 | register unsigned char* intrStack; |
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| 230 | |
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| 231 | /* Set MPC8260ADS board LEDS and Uart enable lines */ |
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| 232 | _BSP_GPLED0_off(); |
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| 233 | _BSP_GPLED1_off(); |
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| 234 | _BSP_Uart1_enable(); |
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| 235 | _BSP_Uart2_enable(); |
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| 236 | |
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| 237 | /* |
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| 238 | * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function |
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| 239 | * store the result in global variables so that it can be used latter... |
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| 240 | */ |
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| 241 | myCpu = get_ppc_cpu_type(); |
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| 242 | myCpuRevision = get_ppc_cpu_revision(); |
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| 243 | |
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| 244 | cpu_init(); |
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| 245 | |
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| 246 | /* |
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| 247 | mmu_init(); |
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| 248 | */ |
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| 249 | /* |
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| 250 | * Initialize some SPRG registers related to irq handling |
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| 251 | */ |
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| 252 | |
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[1899fe4] | 253 | intrStack = (((unsigned char*)&intrStackPtr) - PPC_MINIMUM_STACK_FRAME_SIZE); |
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[7b59de1c] | 254 | _write_SPRG1((unsigned int)intrStack); |
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| 255 | /* signal that we have fixed PR288 - eventually, this should go away */ |
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| 256 | _write_SPRG0(PPC_BSP_HAS_FIXED_PR288); |
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[5edbffe] | 257 | |
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| 258 | /* |
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| 259 | printk( "About to call initialize_exceptions\n" ); |
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| 260 | */ |
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| 261 | /* |
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| 262 | * Install our own set of exception vectors |
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| 263 | */ |
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| 264 | |
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| 265 | initialize_exceptions(); |
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| 266 | |
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| 267 | /* |
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| 268 | mmu_init(); |
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| 269 | */ |
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[6128a4a] | 270 | |
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[5edbffe] | 271 | /* |
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| 272 | * Enable instruction and data caches. Do not force writethrough mode. |
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| 273 | */ |
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| 274 | #if INSTRUCTION_CACHE_ENABLE |
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| 275 | rtems_cache_enable_instruction(); |
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| 276 | #endif |
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| 277 | #if DATA_CACHE_ENABLE |
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| 278 | rtems_cache_enable_data(); |
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| 279 | #endif |
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| 280 | |
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| 281 | /* |
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| 282 | * Allocate the memory for the RTEMS Work Space. This can come from |
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| 283 | * a variety of places: hard coded address, malloc'ed from outside |
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| 284 | * RTEMS world (e.g. simulator or primitive memory manager), or (as |
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| 285 | * typically done by stock BSPs) by subtracting the required amount |
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| 286 | * of work space from the last physical address on the CPU board. |
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| 287 | */ |
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| 288 | |
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| 289 | /* |
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| 290 | * Need to "allocate" the memory for the RTEMS Workspace and |
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| 291 | * tell the RTEMS configuration where it is. This memory is |
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| 292 | * not malloc'ed. It is just "pulled from the air". |
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| 293 | */ |
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| 294 | |
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| 295 | BSP_Configuration.work_space_start = (void *)&_WorkspaceBase; |
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| 296 | |
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| 297 | /* |
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| 298 | BSP_Configuration.microseconds_per_tick = 1000; |
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| 299 | */ |
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| 300 | |
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| 301 | /* |
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| 302 | * initialize the CPU table for this BSP |
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| 303 | */ |
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| 304 | |
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| 305 | Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */ |
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| 306 | Cpu_table.postdriver_hook = bsp_postdriver_hook; |
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| 307 | if( Cpu_table.interrupt_stack_size < 4*1024 ) |
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| 308 | Cpu_table.interrupt_stack_size = 4 * 1024; |
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| 309 | |
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[07e9642c] | 310 | bsp_clicks_per_usec = 10; /* for 40MHz extclk */ |
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| 311 | bsp_serial_per_sec = 40000000; |
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| 312 | bsp_serial_external_clock = 0; |
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| 313 | bsp_serial_xon_xoff = 0; |
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| 314 | bsp_serial_cts_rts = 0; |
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| 315 | bsp_serial_rate = 9600; |
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| 316 | bsp_timer_average_overhead = 3; |
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| 317 | bsp_timer_least_valid = 3; |
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| 318 | bsp_clock_speed = 40000000; |
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[5edbffe] | 319 | |
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| 320 | #ifdef REV_0_2 |
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| 321 | /* set up some board specific registers */ |
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| 322 | m8260.siumcr &= 0xF3FFFFFF; /* set TBEN ** BUG FIX ** */ |
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| 323 | m8260.siumcr |= 0x08000000; |
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| 324 | #endif |
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| 325 | |
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| 326 | /* use BRG1 to generate 32kHz timebase */ |
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| 327 | /* |
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[2a832d8] | 328 | m8260.brgc1 = M8260_BRG_EN + (uint32_t)(((uint16_t)((40016384)/(32768)) - 1) << 1) + 0; |
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[5edbffe] | 329 | */ |
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| 330 | |
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| 331 | /* |
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| 332 | * Initalize RTEMS IRQ system |
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| 333 | */ |
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| 334 | BSP_rtems_irq_mng_init(0); |
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| 335 | |
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| 336 | /* |
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| 337 | * Call this in case we use TERMIOS for console I/O |
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| 338 | */ |
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| 339 | |
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| 340 | m8xx_uart_reserve_resources(&BSP_Configuration); |
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| 341 | |
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| 342 | /* |
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| 343 | rtems_termios_initialize(); |
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| 344 | */ |
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| 345 | #ifdef SHOW_MORE_INIT_SETTINGS |
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| 346 | printk("Exit from bspstart\n"); |
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| 347 | #endif |
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| 348 | |
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| 349 | } |
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| 350 | |
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| 351 | /* |
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| 352 | * |
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| 353 | * _Thread_Idle_body |
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| 354 | * |
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| 355 | * Replaces the one in c/src/exec/score/src/threadidlebody.c |
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| 356 | * The MSR[POW] bit is set to put the CPU into the low power mode |
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| 357 | * defined in HID0. HID0 is set during starup in start.S. |
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| 358 | * |
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| 359 | */ |
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| 360 | Thread _Thread_Idle_body( |
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[2a832d8] | 361 | uint32_t ignored ) |
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[5edbffe] | 362 | { |
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| 363 | |
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| 364 | for( ; ; ) |
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| 365 | { |
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| 366 | asm volatile( |
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| 367 | "mfmsr 3; oris 3,3,4; sync; mtmsr 3; isync; ori 3,3,0; ori 3,3,0" |
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| 368 | ); |
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| 369 | } |
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[89fcd5ca] | 370 | |
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| 371 | return 0; /* to remove warning */ |
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[5edbffe] | 372 | } |
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