source: rtems/c/src/lib/libbsp/powerpc/mpc8260ads/start/start.S @ 1628414

4.104.114.84.95
Last change on this file since 1628414 was 1628414, checked in by Joel Sherrill <joel.sherrill@…>, on Apr 18, 2002 at 8:55:01 PM

2002-04-18 Ralf Corsepius <corsepiu@…>

  • irq/irq.c: Reflect changes to <rtems/score/cpu.h>.
  • irq/irq_asm.S: Ditto.
  • network/network.c: Include <rtems/bspIo.h>.
  • start/start.S: Include <asm.h> instead of "asm.h".
  • vectors/vectors.S: Reflect changes to <rtems/score/cpu.h>.
  • Property mode set to 100644
File size: 4.6 KB
Line 
1/*  start.S
2 *
3 *  $Id$
4 *
5 *  Modified for the Motorola PQII ADS board by
6 *  Andy Dachs <a.dachs@sstl.co.uk> 23-11-00.
7 *  Surrey Satellite Technology Limited
8 *
9 *  I have a proprietary bootloader programmed into the flash
10 *  on the board which initialises the SDRAM prior to calling
11 *  this function.
12 *
13 *  This file is based on the one by Jay Monkman (jmonkman@fracsa.com)
14 *  which in turn was based on the dlentry.s file for the Papyrus BSP,
15 *  written by:
16 *
17 *  Author:     Andrew Bray <andy@i-cubed.co.uk>
18 *
19 *  COPYRIGHT (c) 1995 by i-cubed ltd.
20 *
21 *  To anyone who acknowledges that this file is provided "AS IS"
22 *  without any express or implied warranty:
23 *      permission to use, copy, modify, and distribute this file
24 *      for any purpose is hereby granted without fee, provided that
25 *      the above copyright notice and this notice appears in all
26 *      copies, and that the name of i-cubed limited not be used in
27 *      advertising or publicity pertaining to distribution of the
28 *      software without specific, written prior permission.
29 *      i-cubed limited makes no representations about the suitability
30 *      of this software for any purpose.
31 *
32 */
33
34#include <asm.h>
35
36/*
37 *  The initial stack is set to run BELOW the code base address.
38 *  (between the vectors and text sections)
39 *
40 *  The entry veneer has to clear the BSS and copy the read only
41 *  version of the data segment to the correct location.
42 */
43
44
45        .section ".entry"  /* This might have to be the first thing in the
46                            * text section. At one time, it had to be
47                            * first, but I don't believe it is true
48                            * any more. */
49        PUBLIC_VAR (start)
50SYM(start):
51        bl      .startup
52base_addr:     
53
54/*
55 * Parameters from linker
56 */
57toc_pointer:   
58        .long   s.got
59bss_length:     
60        .long   bss.size
61bss_addr:       
62        .long   bss.start
63
64PUBLIC_VAR (data_length )
65data_length:
66        .long   data.size
67PUBLIC_VAR (data_addr )
68data_addr:
69        .long   data.start
70
71
72
73PUBLIC_VAR (text_addr)
74text_addr:
75        .long   text.start
76
77PUBLIC_VAR (text_length)
78text_length:
79        .long   text.size
80
81
82/*
83 * Initialization code
84 */
85.startup:
86    /* Get start address */
87        mflr    r1
88
89
90    /* --------------------------------------------------
91     * Clear MSR[EE] to disable interrupts
92     * Clear MSR[IP] bit to put vectors at 0x00000000
93     * Set MSR[FP] to enable FPU - not on my eval board!
94     * -------------------------------------------------- */
95        mfmsr   r5
96        lis     r13, 0xFFFF
97        ori     r13, r13, 0x7FBF
98        and     r5, r5, r13                     /* Clear EE and IP */
99#if 1
100        ori     r5, r5, 0x2000                  /* Enable FPU */
101#endif
102        mtmsr   r5
103
104
105
106
107#ifdef ENABLE_CACHE     
108        /* Enable caches */
109        mfspr   r5, 1008
110        ori     r5, r5, 0x8000
111        isync
112        mtspr   1008, r5
113       
114/*      Leave D-cache disabled for now */
115#if 0   
116        ori     r5, r5, 0x4000
117        sync
118        mtspr   1008, r5
119#endif
120#endif
121
122
123        /*--------------------------------------------------
124         * Set up the power management modes
125         * The 8260 has a dynamic power management mode that
126         * is automatically invoked if the unit is idle.
127         * We invoke the NAP mode in the RTEMS idle task.
128         *-------------------------------------------------- */
129
130        lis     r13, 0x0050     /* set nap mode and DPM */
131        or      r5, r5, r13     
132        mtspr   1008, r5
133
134        /*--------------------------------------------------
135         *
136         *-------------------------------------------------- */
137
138
139
140        /* clear the bss section */
141        bl      bssclr
142
143
144/*
145 * C_setup.
146 */
147
148        /* set toc */
149        lwz r2, toc_pointer-base_addr(r1)
150
151        /* Set up stack pointer = beginning of text section - 56 */
152        addi    r1, r1, -56-4
153
154
155        /* clear argc and argv */
156        xor     r3, r3, r3
157        xor     r4, r4, r4
158       
159        .extern SYM (boot_card)
160        bl       SYM (boot_card)        /* call the first C routine */
161
162       
163
164        /* we don't expect to return from boot_card but if we do */
165        /* wait here for watchdog to kick us into hard reset     */
166
167
168twiddle:
169        b               twiddle
170
171
172/*
173 * bssclr - zero out bss
174 */
175bssclr:
176        lwz     r4, bss_addr-base_addr(r1)      /* Start of bss */
177        lwz     r5, bss_length-base_addr(r1)    /* Length of bss */
178
179        rlwinm. r5,r5,30,0x3FFFFFFF             /* form length/4 */
180        beqlr                                   /* no bss */
181        mtctr   r5                              /* set ctr reg */
182        xor     r6,r6,r6                        /* r6 = 0 */
183clear_bss:
184        stswi   r6,r4,0x4                       /* store r6 */
185        addi    r4,r4,0x4                       /* update r2 */
186
187        bdnz    clear_bss                       /* dec counter and loop */
188        blr                                     /* return */
189
190
191
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