source: rtems/c/src/lib/libbsp/powerpc/mpc8260ads/network/network.c @ 888bc77

4.104.114.84.9
Last change on this file since 888bc77 was 888bc77, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 25, 2004 at 2:24:01 PM

2004-07-25 Joel Sherrill <joel@…>

  • network/network.c: Add include of <sys/errno.h>.
  • Property mode set to 100644
File size: 23.8 KB
Line 
1/*
2 * RTEMS/TCPIP driver for MPC8260 SCC
3 *
4 * Modified for MPC8260 by Andy Dachs <a.dachs@sstl.co.uk>
5 * Surrey Satellite Technology Limited
6 *
7 *   On the ADS board the ethernet interface is connected to FCC2
8 *   but in my application I want TCP over HDLC (see README)
9 *   so will use SCC3 as the network interface. I have other plans
10 *   for the FCCs so am unlikely to add true ethernet support to
11 *   this BSP.  Contributions welcome!
12 *
13 * Modified for MPC860 by Jay Monkman (jmonkman@frasca.com)
14 *
15 *  This supports ethernet on either SCC1 or the FEC of the MPC860T.
16 *  Right now, we only do 10 Mbps, even with the FEC. The function
17 *  rtems_m860_enet_driver_attach determines which one to use. Currently,
18 *  only one may be used at a time.
19 *
20 * W. Eric Norum
21 * Saskatchewan Accelerator Laboratory
22 * University of Saskatchewan
23 * Saskatoon, Saskatchewan, CANADA
24 * eric@skatter.usask.ca
25 *
26 *  $Id$
27 */
28#include <bsp.h>
29#include <bsp/irq.h>
30#include <mpc8260.h>
31#include <mpc8260/cpm.h>
32#include <stdio.h>
33#include <rtems/error.h>
34#include <rtems/rtems_bsdnet.h>
35#include <rtems/bspIo.h>
36
37#include <sys/param.h>
38#include <sys/mbuf.h>
39#include <sys/socket.h>
40#include <sys/sockio.h>
41#include <sys/errno.h>
42
43#include <net/if.h>
44
45#include <netinet/in.h>
46#include <netinet/if_ether.h>
47
48#include "if_hdlcsubr.h"
49
50/*
51 * Number of interfaces supported by this driver
52 */
53#define NIFACES 1
54
55/*
56 * Default number of buffer descriptors set aside for this driver.
57 * The number of transmit buffer descriptors has to be quite large
58 * since a single frame often uses four or more buffer descriptors.
59 */
60#define RX_BUF_COUNT     32
61#define TX_BUF_COUNT     8
62#define TX_BD_PER_BUF    4
63
64#define INET_ADDR_MAX_BUF_SIZE (sizeof "255.255.255.255")
65
66extern void m8xx_dump_brgs( void );
67
68/*
69 * RTEMS event used by interrupt handler to signal daemons.
70 * This must *not* be the same event used by the TCP/IP task synchronization.
71 */
72#define INTERRUPT_EVENT RTEMS_EVENT_1
73
74/*
75 * RTEMS event used to start transmit daemon.
76 * This must not be the same as INTERRUPT_EVENT.
77 */
78#define START_TRANSMIT_EVENT    RTEMS_EVENT_2
79
80/*
81 * Receive buffer size -- Allow for a full ethernet packet plus CRC (1518).
82 * Round off to nearest multiple of RBUF_ALIGN.
83 */
84#define MAX_MTU_SIZE    1518
85/*#define MAX_MTU_SIZE  2050*/
86#define RBUF_ALIGN      4
87#define RBUF_SIZE       ((MAX_MTU_SIZE + RBUF_ALIGN) & ~RBUF_ALIGN)
88
89#if (MCLBYTES < RBUF_SIZE)
90# error "Driver must have MCLBYTES > RBUF_SIZE"
91#endif
92
93/*
94 * Per-device data
95 */
96struct m8260_hdlc_struct {
97        struct ifnet            ac_if;
98        struct mbuf             **rxMbuf;
99        struct mbuf             **txMbuf;
100        int                     acceptBroadcast;
101        int                     rxBdCount;
102        int                     txBdCount;
103        int                     txBdHead;
104        int                     txBdTail;
105        int                     txBdActiveCount;
106        m8260BufferDescriptor_t  *rxBdBase;
107        m8260BufferDescriptor_t  *txBdBase;
108        rtems_id                rxDaemonTid;
109        rtems_id                txDaemonTid;
110
111        /*
112         * Statistics
113         */
114        unsigned long   rxNotFirst;
115        unsigned long   rxNotLast;
116        unsigned long   rxInterrupts;
117        unsigned long   rxGiant;
118        unsigned long   rxNonOctet;
119        unsigned long   rxAbort;
120        unsigned long   rxBadCRC;
121        unsigned long   rxOverrun;
122        unsigned long   rxLostCarrier;
123        unsigned long   txInterrupts;
124        unsigned long   txUnderrun;
125        unsigned long   txLostCarrier;
126        unsigned long   txRawWait;
127};
128static struct m8260_hdlc_struct hdlc_driver[NIFACES];
129
130static void  m8xx_scc3_hdlc_on(const rtems_irq_connect_data* ptr)
131{
132}
133
134static void  m8xx_scc3_hdlc_off(const rtems_irq_connect_data* ptr)
135{
136  /*
137   * Please put relevant code there
138   */
139}
140
141static int  m8xx_scc3_hdlc_isOn(const rtems_irq_connect_data* ptr)
142{
143  return BSP_irq_enabled_at_cpm (ptr->name);
144}
145
146/*
147 * SCC interrupt handler
148 * TBD: Can we work out which SCC generated the interrupt from the
149 *      value of v? If so we can use the same handler for multiple
150 *      SCCs.
151 */
152static void
153m8xx_scc3_interrupt_handler ()
154{
155  /*
156   * Frame received?
157   */
158  if ((m8260.scc3.sccm & M8260_SCCE_RXF) &&
159      (m8260.scc3.scce & M8260_SCCE_RXF) ) {
160    m8260.scc3.scce = M8260_SCCE_RXF;
161/*    m8260.scc3.sccm &= ~M8260_SCCE_RXF; */
162    hdlc_driver[0].rxInterrupts++;
163    rtems_event_send (hdlc_driver[0].rxDaemonTid, INTERRUPT_EVENT);
164/*
165    printk( "Rx " );
166*/
167  }
168
169  /*
170   * Buffer transmitted or transmitter error?
171   */
172  if ((m8260.scc3.sccm & (M8260_SCCE_TX | M8260_SCCE_TXE) ) &&
173      (m8260.scc3.scce & (M8260_SCCE_TX | M8260_SCCE_TXE) )) {
174    m8260.scc3.scce = M8260_SCCE_TX | M8260_SCCE_TXE;
175/*    m8260.scc3.sccm &= ~(M8260_SCCE_TX | M8260_SCCE_TXE); */
176    hdlc_driver[0].txInterrupts++;
177    rtems_event_send (hdlc_driver[0].txDaemonTid, INTERRUPT_EVENT);
178/*
179    printk( "Tx " );
180*/
181  }
182
183#if 0
184  m8260.sipnr_l = M8260_SIMASK_SCC3; /* Clear SCC3 interrupt-in-service bit */
185#endif
186}
187
188static rtems_irq_connect_data hdlcSCC3IrqData = {
189  BSP_CPM_IRQ_SCC3,
190  (rtems_irq_hdl) m8xx_scc3_interrupt_handler,
191  (rtems_irq_enable) m8xx_scc3_hdlc_on,
192  (rtems_irq_disable) m8xx_scc3_hdlc_off,
193  (rtems_irq_is_enabled)m8xx_scc3_hdlc_isOn
194};
195
196/*
197 * Initialize the SCC hardware
198 * Configure I/O ports for SCC3
199 * Internal Tx clock, External Rx clock
200 */
201static void
202m8260_scc_initialize_hardware (struct m8260_hdlc_struct *sc)
203{
204  int i;
205  int brg;
206
207/*
208  unsigned char *hwaddr;
209*/
210  rtems_status_code status;
211/*
212  rtems_isr_entry old_handler;
213*/
214
215  /* RxD PB14 */
216  m8260.pparb |=  0x00020000;
217  m8260.psorb &= ~0x00020000;
218  m8260.pdirb &= ~0x00020000;
219
220  /* RxC (CLK5) PC27 */
221  m8260.pparc |=  0x00000010;
222  m8260.psorc &= ~0x00000010;
223  m8260.pdirc &= ~0x00000010;
224
225  /* TxD PD24 and TxC PD10 (BRG4) */
226  m8260.ppard |=  0x00200080;
227  m8260.psord |=  0x00200000;
228  m8260.psord &= ~0x00000080;
229  m8260.pdird |=  0x00200080;
230
231  /* External Rx Clock from CLK5 */
232  if( m8xx_get_clk( M8xx_CLK_5 ) == -1 )
233    printk( "Error allocating CLK5 for network device.\n" );
234  else
235    m8260.cmxscr |= 0x00002000;
236
237  /* Internal Tx Clock from BRG4 */
238  if( (brg = m8xx_get_brg(M8xx_BRG_4, 8000000 )) == -1 )
239    printk( "Error allocating BRG for network device\n" );
240  else
241    m8260.cmxscr |= ((unsigned)brg << 8);
242
243  /*
244   * Allocate mbuf pointers
245   */
246  sc->rxMbuf = malloc (sc->rxBdCount * sizeof *sc->rxMbuf,
247                       M_MBUF, M_NOWAIT);
248  sc->txMbuf = malloc (sc->txBdCount * sizeof *sc->txMbuf,
249                       M_MBUF, M_NOWAIT);
250  if (!sc->rxMbuf || !sc->txMbuf)
251    rtems_panic ("No memory for mbuf pointers");
252
253  /*
254   * Set receiver and transmitter buffer descriptor bases
255   */
256  sc->rxBdBase = m8xx_bd_allocate (sc->rxBdCount);
257  sc->txBdBase = m8xx_bd_allocate (sc->txBdCount);
258
259  m8260.scc3p.rbase = (char *)sc->rxBdBase - (char *)&m8260;
260  m8260.scc3p.tbase = (char *)sc->txBdBase - (char *)&m8260;
261
262  /*
263   * Send "Init parameters" command
264   */
265
266  m8xx_cp_execute_cmd (M8260_CR_OP_INIT_RX_TX | M8260_CR_SCC3 );
267
268  /*
269   * Set receive and transmit function codes
270   */
271  m8260.scc3p.rfcr = M8260_RFCR_MOT | M8260_RFCR_60X_BUS;
272  m8260.scc3p.tfcr = M8260_TFCR_MOT | M8260_TFCR_60X_BUS;
273
274  /*
275   * Set maximum receive buffer length
276   */
277  m8260.scc3p.mrblr = RBUF_SIZE;
278
279  m8260.scc3p.un.hdlc.c_mask = 0xF0B8;
280  m8260.scc3p.un.hdlc.c_pres = 0xFFFF;
281  m8260.scc3p.un.hdlc.disfc  = 0;
282  m8260.scc3p.un.hdlc.crcec  = 0;
283  m8260.scc3p.un.hdlc.abtsc  = 0;
284  m8260.scc3p.un.hdlc.nmarc  = 0;
285  m8260.scc3p.un.hdlc.retrc  = 0;
286  m8260.scc3p.un.hdlc.rfthr  = 1;
287  m8260.scc3p.un.hdlc.mflr   = RBUF_SIZE;
288
289  m8260.scc3p.un.hdlc.hmask  = 0x0000;  /* promiscuous */
290
291  m8260.scc3p.un.hdlc.haddr1 = 0xFFFF;  /* Broadcast address */
292  m8260.scc3p.un.hdlc.haddr2 = 0xFFFF;  /* Station address */
293  m8260.scc3p.un.hdlc.haddr3 = 0xFFFF;  /* Dummy */
294  m8260.scc3p.un.hdlc.haddr4 = 0xFFFF;  /* Dummy */
295
296  /*
297   * Send "Init parameters" command
298   */
299/*
300  m8xx_cp_execute_cmd (M8260_CR_OP_INIT_RX_TX | M8260_CR_SCC3 );
301*/
302
303  /*
304   * Set up receive buffer descriptors
305   */
306  for (i = 0 ; i < sc->rxBdCount ; i++) {
307    (sc->rxBdBase + i)->status = 0;
308  }
309
310  /*
311   * Set up transmit buffer descriptors
312   */
313  for (i = 0 ; i < sc->txBdCount ; i++) {
314    (sc->txBdBase + i)->status = 0;
315    sc->txMbuf[i] = NULL;
316  }
317  sc->txBdHead = sc->txBdTail = 0;
318  sc->txBdActiveCount = 0;
319
320  m8260.scc3.sccm = 0;     /* No interrupts unmasked till necessary */
321
322  /*
323   * Clear any outstanding events
324   */
325  m8260.scc3.scce = 0xFFFF;
326
327  /*
328   * Set up interrupts
329   */
330  status = BSP_install_rtems_irq_handler (&hdlcSCC3IrqData);
331/*
332  printk( "status = %d, Success = %d\n", status, RTEMS_SUCCESSFUL );
333*/
334  if (status != 1 /*RTEMS_SUCCESSFUL*/ ) {
335    rtems_panic ("Can't attach M8260 SCC3 interrupt handler: %s\n",
336                 rtems_status_text (status));
337  }
338  m8260.scc3.sccm = 0;     /* No interrupts unmasked till necessary */
339
340#if 0
341  /*
342   * Set up interrupts
343   */
344  status = rtems_interrupt_catch (m8260_scc3_interrupt_handler,
345                                  PPC_IRQ_CPM_SCC3,
346                                  &old_handler);
347  if (status != RTEMS_SUCCESSFUL) {
348    rtems_panic ("Can't attach M8260 SCC3 interrupt handler: %s\n",
349                 rtems_status_text (status));
350  }
351
352  m8260.sipnr_l = M8260_SIMASK_SCC3; /* clear pending event */
353  m8260.simr_l |= M8260_SIMASK_SCC3; /* Enable SCC interrupt */
354
355#endif
356
357  m8260.scc3.gsmr_h  = 0;
358  m8260.scc3.gsmr_l  = 0x10000000;
359  m8260.scc3.dsr     = 0x7E7E;  /* flag character */
360  m8260.scc3.psmr    = 0x2000;  /* 2 flags between Tx'd frames */
361
362/*  printk("scc3 init\n" ); */
363
364  m8260.scc3.gsmr_l |=  0x00000030;  /* Set ENR and ENT to enable Rx and Tx */
365
366}
367
368/*
369 * Soak up buffer descriptors that have been sent
370 * Note that a buffer descriptor can't be retired as soon as it becomes
371 * ready.  The MC68360 Errata (May 96) says that, "If an Ethernet frame is
372 *  made up of multiple buffers, the user should not reuse the first buffer
373 * descriptor until the last buffer descriptor of the frame has had its
374 * ready bit cleared by the CPM".
375 */
376static void
377m8260Enet_retire_tx_bd (struct m8260_hdlc_struct *sc)
378{
379  uint16_t         status;
380  int i;
381  int nRetired;
382  struct mbuf *m, *n;
383
384  i = sc->txBdTail;
385  nRetired = 0;
386  while ((sc->txBdActiveCount != 0)
387         &&  (((status = (sc->txBdBase + i)->status) & M8260_BD_READY) == 0)) {
388    /*
389     * See if anything went wrong
390     */
391    if (status & (M8260_BD_UNDERRUN |
392                  M8260_BD_CTS_LOST)) {
393      /*
394       * Check for errors which stop the transmitter.
395       */
396      if( status & M8260_BD_UNDERRUN ) {
397          hdlc_driver[0].txUnderrun++;
398
399        /*
400         * Restart the transmitter
401         */
402        /* FIXME: this should get executed only if using the SCC */
403        m8xx_cp_execute_cmd (M8260_CR_OP_RESTART_TX | M8260_CR_SCC3);
404      }
405      if (status & M8260_BD_CTS_LOST)
406        hdlc_driver[0].txLostCarrier++;
407    }
408    nRetired++;
409    if (status & M8260_BD_LAST) {
410      /*
411       * A full frame has been transmitted.
412       * Free all the associated buffer descriptors.
413       */
414      sc->txBdActiveCount -= nRetired;
415      while (nRetired) {
416        nRetired--;
417        m = sc->txMbuf[sc->txBdTail];
418        MFREE (m, n);
419        if (++sc->txBdTail == sc->txBdCount)
420          sc->txBdTail = 0;
421      }
422    }
423    if (++i == sc->txBdCount)
424      i = 0;
425  }
426}
427
428/*
429 * reader task
430 */
431static void
432scc_rxDaemon (void *arg)
433{
434  struct m8260_hdlc_struct *sc = (struct m8260_hdlc_struct *)arg;
435  struct ifnet *ifp = &sc->ac_if;
436  struct mbuf *m;
437  uint16_t         status;
438  m8260BufferDescriptor_t *rxBd;
439  int rxBdIndex;
440
441  /*
442   * Allocate space for incoming packets and start reception
443   */
444  for (rxBdIndex = 0 ; ;) {
445    rxBd = sc->rxBdBase + rxBdIndex;
446    MGETHDR (m, M_WAIT, MT_DATA);
447    MCLGET (m, M_WAIT);
448    m->m_pkthdr.rcvif = ifp;
449    sc->rxMbuf[rxBdIndex] = m;
450    rxBd->buffer = mtod (m, void *);
451    rxBd->status = M8260_BD_EMPTY | M8260_BD_INTERRUPT;
452    if (++rxBdIndex == sc->rxBdCount) {
453      rxBd->status |= M8260_BD_WRAP;
454      break;
455    }
456  }
457
458/*
459  m8260.scc3.sccm |= M8260_SCCE_RXF;
460*/
461
462  /*
463   * Input packet handling loop
464   */
465  rxBdIndex = 0;
466  for (;;) {
467    rxBd = sc->rxBdBase + rxBdIndex;
468
469    /*
470     * Wait for packet if there's not one ready
471     */
472    if ((status = rxBd->status) & M8260_BD_EMPTY) {
473      /*
474       * Clear old events
475       */
476
477      m8260.scc3.scce = M8260_SCCE_RXF;
478
479      /*
480       * Wait for packet
481       * Note that the buffer descriptor is checked
482       * *before* the event wait -- this catches the
483       * possibility that a packet arrived between the
484       * `if' above, and the clearing of the event register.
485       */
486      while ((status = rxBd->status) & M8260_BD_EMPTY) {
487        rtems_event_set events;
488
489        /*
490         * Unmask RXF (Full frame received) event
491         */
492        m8260.scc3.sccm |= M8260_SCCE_RXF;
493
494/*        printk( "Rxdwait "); */
495
496        rtems_bsdnet_event_receive (INTERRUPT_EVENT,
497                                    RTEMS_WAIT|RTEMS_EVENT_ANY,
498                                    RTEMS_NO_TIMEOUT,
499                                    &events);
500
501/*        printk( "Rxd " ); */
502      }
503    }
504
505    /*
506     * Check that packet is valid
507     */
508    if ((status & (M8260_BD_LAST |
509                   M8260_BD_FIRST_IN_FRAME |
510                   M8260_BD_LONG |
511                   M8260_BD_NONALIGNED |
512                   M8260_BD_ABORT |
513                   M8260_BD_CRC_ERROR |
514                   M8260_BD_OVERRUN /*|
515                   M8260_BD_CARRIER_LOST*/)) ==
516                   (M8260_BD_LAST |
517                   M8260_BD_FIRST_IN_FRAME ) ) {
518
519/*      printk( "RxV " ); */
520
521/*
522 * Invalidate the buffer for this descriptor
523 */
524
525      rtems_cache_invalidate_multiple_data_lines((void *)rxBd->buffer, rxBd->length);
526
527      m = sc->rxMbuf[rxBdIndex];
528
529      /* strip off HDLC CRC */
530      m->m_len = m->m_pkthdr.len = rxBd->length - sizeof(uint16_t);
531
532      hdlc_input( ifp, m );
533
534      /*
535       * Allocate a new mbuf
536       */
537      MGETHDR (m, M_WAIT, MT_DATA);
538      MCLGET (m, M_WAIT);
539      m->m_pkthdr.rcvif = ifp;
540      sc->rxMbuf[rxBdIndex] = m;
541      rxBd->buffer = mtod (m, void *);
542    }
543    else {
544      printk( "RxErr[%04X,%d]", status, rxBd->length );
545      /*
546       * Something went wrong with the reception
547       */
548      if (!(status & M8260_BD_LAST))
549        sc->rxNotLast++;
550      if (!(status & M8260_BD_FIRST_IN_FRAME))
551        sc->rxNotFirst++;
552
553      if (status & M8260_BD_LONG)
554        sc->rxGiant++;
555      if (status & M8260_BD_NONALIGNED)
556        sc->rxNonOctet++;
557      if (status & M8260_BD_ABORT)
558        sc->rxAbort++;
559      if (status & M8260_BD_CRC_ERROR)
560        sc->rxBadCRC++;
561      if (status & M8260_BD_OVERRUN)
562        sc->rxOverrun++;
563      if (status & M8260_BD_CARRIER_LOST)
564        sc->rxLostCarrier++;
565    }
566
567    /*
568     * Reenable the buffer descriptor
569     */
570    rxBd->status = (status & (M8260_BD_WRAP | M8260_BD_INTERRUPT)) |
571                    M8260_BD_EMPTY;
572
573    /*
574     * Move to next buffer descriptor
575     */
576    if (++rxBdIndex == sc->rxBdCount)
577      rxBdIndex = 0;
578  }
579}
580
581static void
582scc_sendpacket (struct ifnet *ifp, struct mbuf *m)
583{
584  struct m8260_hdlc_struct *sc = ifp->if_softc;
585  volatile m8260BufferDescriptor_t *firstTxBd, *txBd;
586  struct mbuf *l = NULL;
587  uint16_t         status;
588  int nAdded;
589
590  /*
591   * Free up buffer descriptors
592   */
593  m8260Enet_retire_tx_bd (sc);
594
595  /*
596   * Set up the transmit buffer descriptors.
597   * No need to pad out short packets since the
598   * hardware takes care of that automatically.
599   * No need to copy the packet to a contiguous buffer
600   * since the hardware is capable of scatter/gather DMA.
601   */
602  nAdded = 0;
603  txBd = firstTxBd = sc->txBdBase + sc->txBdHead;
604
605/*
606  m8260.scc3.sccm |= (M8260_SCCE_TX | M8260_SCCE_TXE);
607*/
608
609  for (;;) {
610    /*
611     * Wait for buffer descriptor to become available.
612     */
613    if ((sc->txBdActiveCount + nAdded) == sc->txBdCount) {
614      /*
615       * Clear old events
616       */
617      m8260.scc3.scce = M8260_SCCE_TX | M8260_SCCE_TXE;
618
619      /*
620       * Wait for buffer descriptor to become available.
621       * Note that the buffer descriptors are checked
622       * *before* * entering the wait loop -- this catches
623       * the possibility that a buffer descriptor became
624       * available between the `if' above, and the clearing
625       * of the event register.
626       * This is to catch the case where the transmitter
627       * stops in the middle of a frame -- and only the
628       * last buffer descriptor in a frame can generate
629       * an interrupt.
630       */
631      m8260Enet_retire_tx_bd (sc);
632      while ((sc->txBdActiveCount + nAdded) == sc->txBdCount) {
633        rtems_event_set events;
634
635        /*
636         * Unmask TX (buffer transmitted) event
637         */
638        m8260.scc3.sccm |= (M8260_SCCE_TX | M8260_SCCE_TXE);
639
640        rtems_bsdnet_event_receive (INTERRUPT_EVENT,
641                                    RTEMS_WAIT|RTEMS_EVENT_ANY,
642                                    RTEMS_NO_TIMEOUT,
643                                    &events);
644        m8260Enet_retire_tx_bd (sc);
645      }
646    }
647
648    /*
649     * Don't set the READY flag till the
650     * whole packet has been readied.
651     */
652    status = nAdded ? M8260_BD_READY : 0;
653
654    /*
655     *  FIXME: Why not deal with empty mbufs at at higher level?
656     * The IP fragmentation routine in ip_output
657     * can produce packet fragments with zero length.
658     * I think that ip_output should be changed to get
659     * rid of these zero-length mbufs, but for now,
660     * I'll deal with them here.
661     */
662    if (m->m_len) {
663      /*
664       * Fill in the buffer descriptor
665       */
666
667      txBd->buffer = mtod (m, void *);
668      txBd->length = m->m_len;
669
670      /*
671       * Flush the buffer for this descriptor
672       */
673
674      rtems_cache_flush_multiple_data_lines((void *)txBd->buffer, txBd->length);
675
676/* throw off the header for Ethernet Emulation mode */
677/*
678      txBd->buffer = mtod (m, void *);
679      txBd->buffer += sizeof( struct ether_header ) + 2;
680      txBd->length = m->m_len - sizeof( struct ether_header ) - 2;
681*/
682      sc->txMbuf[sc->txBdHead] = m;
683      nAdded++;
684      if (++sc->txBdHead == sc->txBdCount) {
685        status |= M8260_BD_WRAP;
686        sc->txBdHead = 0;
687      }
688      l = m;
689      m = m->m_next;
690    }
691    else {
692      /*
693       * Just toss empty mbufs
694       */
695      struct mbuf *n;
696      MFREE (m, n);
697      m = n;
698      if (l != NULL)
699        l->m_next = m;
700    }
701
702    /*
703     * Set the transmit buffer status.
704     * Break out of the loop if this mbuf is the last in the frame.
705     */
706    if (m == NULL) {
707      if (nAdded) {
708        status |= M8260_BD_LAST | M8260_BD_TX_CRC | M8260_BD_INTERRUPT;
709        txBd->status = status;
710        firstTxBd->status |= M8260_BD_READY;
711        sc->txBdActiveCount += nAdded;
712      }
713      break;
714    }
715    txBd->status = status;
716    txBd = sc->txBdBase + sc->txBdHead;
717  }
718}
719
720/*
721 * Driver transmit daemon
722 */
723void
724scc_txDaemon (void *arg)
725{
726  struct m8260_hdlc_struct *sc = (struct m8260_hdlc_struct *)arg;
727  struct ifnet *ifp = &sc->ac_if;
728  struct mbuf *m;
729  rtems_event_set events;
730
731  for (;;) {
732    /*
733     * Wait for packet
734     */
735    rtems_bsdnet_event_receive (START_TRANSMIT_EVENT, RTEMS_EVENT_ANY | RTEMS_WAIT, RTEMS_NO_TIMEOUT, &events);
736
737    /*
738     * Send packets till queue is empty
739     */
740    for (;;) {
741      /*
742       * Get the next mbuf chain to transmit.
743       */
744      IF_DEQUEUE(&ifp->if_snd, m);
745      if (!m)
746        break;
747
748      scc_sendpacket (ifp, m);
749
750    }
751    ifp->if_flags &= ~IFF_OACTIVE;
752  }
753}
754
755/*
756 * Send packet (caller provides header).
757 */
758static void
759m8260_hdlc_start (struct ifnet *ifp)
760{
761  struct m8260_hdlc_struct *sc = ifp->if_softc;
762
763  rtems_event_send (sc->txDaemonTid, START_TRANSMIT_EVENT);
764  ifp->if_flags |= IFF_OACTIVE;
765}
766
767/*
768 * Initialize and start the device
769 */
770static void
771scc_init (void *arg)
772{
773  struct m8260_hdlc_struct *sc = arg;
774  struct ifnet *ifp = &sc->ac_if;
775
776  if (sc->txDaemonTid == 0) {
777
778    /*
779     * Set up SCC hardware
780     */
781    m8260_scc_initialize_hardware (sc);
782
783    /*
784     * Start driver tasks
785     */
786    sc->txDaemonTid = rtems_bsdnet_newproc ("SCtx", 4096, scc_txDaemon, sc);
787    sc->rxDaemonTid = rtems_bsdnet_newproc ("SCrx", 4096, scc_rxDaemon, sc);
788
789  }
790
791#if 0
792  /*
793   * Set flags appropriately
794   */
795  if (ifp->if_flags & IFF_PROMISC)
796    m8260.scc3.psmr |= 0x200;
797  else
798    m8260.scc3.psmr &= ~0x200;
799#endif
800
801  /*
802   * Tell the world that we're running.
803   */
804  ifp->if_flags |= IFF_RUNNING;
805
806  /*
807   * Enable receiver and transmitter
808   */
809  m8260.scc3.gsmr_l |= 0x30;
810}
811
812/*
813 * Stop the device
814 */
815static void
816scc_stop (struct m8260_hdlc_struct *sc)
817{
818  struct ifnet *ifp = &sc->ac_if;
819
820  ifp->if_flags &= ~IFF_RUNNING;
821
822  /*
823   * Shut down receiver and transmitter
824   */
825  m8260.scc3.gsmr_l &= ~0x30;
826}
827
828/*
829 * Show interface statistics
830 */
831static void
832hdlc_stats (struct m8260_hdlc_struct *sc)
833{
834  printf ("      Rx Interrupts:%-8lu", sc->rxInterrupts);
835  printf ("              Giant:%-8lu", sc->rxGiant);
836  printf ("          Non-octet:%-8lu\n", sc->rxNonOctet);
837  printf ("            Bad CRC:%-8lu", sc->rxBadCRC);
838  printf ("            Overrun:%-8lu", sc->rxOverrun);
839  printf ("         No Carrier:%-8lu\n", sc->rxLostCarrier);
840  printf ("          Discarded:%-8lu\n", (unsigned long)m8260.scc3p.un.hdlc.disfc);
841
842  printf ("      Tx Interrupts:%-8lu", sc->txInterrupts);
843  printf ("         No Carrier:%-8lu", sc->txLostCarrier);
844  printf ("           Underrun:%-8lu\n", sc->txUnderrun);
845  printf ("    Raw output wait:%-8lu\n", sc->txRawWait);
846}
847
848/*
849 * Driver ioctl handler
850 */
851static int
852scc_ioctl (struct ifnet *ifp, int command, caddr_t data)
853{
854  struct m8260_hdlc_struct *sc = ifp->if_softc;
855  int error = 0;
856
857  switch (command) {
858  case SIOCGIFADDR:
859  case SIOCSIFADDR:
860    hdlc_ioctl (ifp, command, data);
861    break;
862
863  case SIOCSIFFLAGS:
864    switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) {
865    case IFF_RUNNING:
866      scc_stop (sc);
867      break;
868
869    case IFF_UP:
870      scc_init (sc);
871      break;
872
873    case IFF_UP | IFF_RUNNING:
874      scc_stop (sc);
875      scc_init (sc);
876      break;
877
878    default:
879      break;
880    }
881    break;
882
883  case SIO_RTEMS_SHOW_STATS:
884    hdlc_stats (sc);
885    break;
886
887    /*
888     * FIXME: All sorts of multicast commands need to be added here!
889     */
890  default:
891    error = EINVAL;
892    break;
893  }
894  return error;
895}
896
897/*
898 * Attach an SCC driver to the system
899 */
900int
901rtems_scc3_driver_attach (struct rtems_bsdnet_ifconfig *config)
902{
903  struct m8260_hdlc_struct *sc;
904  struct ifnet *ifp;
905  int mtu;
906  int i;
907
908  /*
909   * Find a free driver
910   */
911  for (i = 0 ; i < NIFACES ; i++) {
912    sc = &hdlc_driver[i];
913    ifp = &sc->ac_if;
914    if (ifp->if_softc == NULL)
915      break;
916  }
917  if (i >= NIFACES) {
918    printf ("Too many SCC drivers.\n");
919    return 0;
920  }
921
922#if 0
923  /*
924   * Process options
925   */
926
927  if (config->hardware_address) {
928    memcpy (sc->arpcom.ac_enaddr, config->hardware_address, ETHER_ADDR_LEN);
929  }
930  else {
931    sc->arpcom.ac_enaddr[0] = 0x44;
932    sc->arpcom.ac_enaddr[1] = 0x22;
933    sc->arpcom.ac_enaddr[2] = 0x33;
934    sc->arpcom.ac_enaddr[3] = 0x33;
935    sc->arpcom.ac_enaddr[4] = 0x22;
936    sc->arpcom.ac_enaddr[5] = 0x44;
937  }
938#endif
939
940  if (config->mtu)
941    mtu = config->mtu;
942  else
943    mtu = ETHERMTU;
944  if (config->rbuf_count)
945    sc->rxBdCount = config->rbuf_count;
946  else
947    sc->rxBdCount = RX_BUF_COUNT;
948  if (config->xbuf_count)
949    sc->txBdCount = config->xbuf_count;
950  else
951    sc->txBdCount = TX_BUF_COUNT * TX_BD_PER_BUF;
952  sc->acceptBroadcast = !config->ignore_broadcast;
953
954  /*
955   * Set up network interface values
956   */
957  ifp->if_softc = sc;
958  ifp->if_unit = i + 1;
959  ifp->if_name = "eth";
960  ifp->if_mtu = mtu;
961  ifp->if_init = scc_init;
962  ifp->if_ioctl = scc_ioctl;
963  ifp->if_start = m8260_hdlc_start;
964  ifp->if_output = hdlc_output;
965  ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | /*IFF_PROMISC |*/ IFF_NOARP;
966  if (ifp->if_snd.ifq_maxlen == 0)
967    ifp->if_snd.ifq_maxlen = ifqmaxlen;
968
969  /*
970   * Attach the interface
971   */
972  if_attach (ifp);
973  hdlc_ifattach (ifp);
974  return 1;
975};
976
977int
978rtems_enet_driver_attach(struct rtems_bsdnet_ifconfig *config, int attaching)
979{
980  return rtems_scc3_driver_attach( config );
981
982/*
983  if ((m8260.fec.mii_data & 0xffff) == 0x2000) {
984    return rtems_fec_driver_attach(config);
985  }
986  else {
987    return rtems_scc1_driver_attach(config);
988  }
989*/
990}
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