source: rtems/c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.h @ 7068d7ac

4.104.114.84.95
Last change on this file since 7068d7ac was 7068d7ac, checked in by Jennifer Averett <Jennifer.Averett@…>, on 05/17/05 at 15:05:03

2005-05-17 Jennifer Averett <jennifer.averett@…>

  • irq/irq.c, irq/irq.h: Modified to use rtems/irq.h.
  • Property mode set to 100644
File size: 7.1 KB
Line 
1/* irq.h
2 *
3 *  This include file describe the data structure and the functions implemented
4 *  by rtems to write interrupt handlers.
5 *
6 *  CopyRight (C) 1999 valette@crf.canon.fr
7 *
8 *  This code is heavilly inspired by the public specification of STREAM V2
9 *  that can be found at :
10 *
11 *      <http://www.chorus.com/Documentation/index.html> by following
12 *  the STREAM API Specification Document link.
13 *
14 *  Modified for mpc8260 by Andy Dachs <a.dachs@sstl.co.uk>
15 *  Surrey Satellite Technology Limited
16 *    The interrupt handling on the mpc8260 seems quite different from
17 *    the 860 (I don't know the 860 well).  Although some interrupts
18 *    are routed via the CPM irq and some are direct to the SIU they all
19 *    appear logically the same.  Therefore I removed the distinction
20 *    between SIU and CPM interrupts.
21 *
22 *  The license and distribution terms for this file may be
23 *  found in found in the file LICENSE in this distribution or at
24 *  http://www.rtems.com/license/LICENSE.
25 *
26 *  $Id$
27 */
28
29#ifndef LIBBSP_POWERPC_IRQ_H
30#define LIBBSP_POWERPC_IRQ_H
31#include <rtems/irq.h>
32
33#define BSP_ASM_IRQ_VECTOR_BASE 0x0
34
35#ifndef ASM
36
37#ifdef __cplusplus
38extern "C" {
39#endif
40
41/*
42extern volatile unsigned int ppc_cached_irq_mask;
43*/
44
45/*
46 * Symblolic IRQ names and related definitions.
47 */
48
49  /* Base vector for our SIU IRQ handlers. */
50#define BSP_SIU_VECTOR_BASE             (BSP_ASM_IRQ_VECTOR_BASE)
51
52  /*
53   * CPM IRQ handlers related definitions
54   * CAUTION : BSP_CPM_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE
55   */
56#define BSP_CPM_IRQ_NUMBER              (64)
57#define BSP_CPM_IRQ_LOWEST_OFFSET       (BSP_SIU_VECTOR_BASE)
58#define BSP_CPM_IRQ_MAX_OFFSET          (BSP_CPM_IRQ_LOWEST_OFFSET + BSP_CPM_IRQ_NUMBER - 1)
59  /*
60   * PowerPc exceptions handled as interrupt where a rtems managed interrupt
61   * handler might be connected
62   */
63#define BSP_PROCESSOR_IRQ_NUMBER        (1)
64#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_CPM_IRQ_MAX_OFFSET + 1)
65#define BSP_PROCESSOR_IRQ_MAX_OFFSET    (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1)
66  /*
67   * Summary
68   */
69#define BSP_IRQ_NUMBER                  (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1)
70#define BSP_LOWEST_OFFSET               (BSP_CPM_IRQ_LOWEST_OFFSET)
71#define BSP_MAX_OFFSET                  (BSP_PROCESSOR_IRQ_MAX_OFFSET)
72
73  /*
74   * Some SIU IRQ symbolic name definition. Please note that
75   * INT IRQ are defined but a single one will be used to
76   * redirect all CPM interrupt.
77   *
78   * On the mpc8260 all this seems to be transparent.  Although the
79   * CPM, PIT and TMCNT interrupt may well be the only interrupts routed
80   * to the SIU at the hardware level all of them appear as CPM interupts
81   * to software apart from the registers for setting priority.
82   *
83   * The MPC8260 User Manual seems shot through with inconsistencies
84   * about this whole area.
85   */
86
87  /*
88   * Some CPM IRQ symbolic name definition
89   */
90#define BSP_CPM_IRQ_ERROR               (BSP_CPM_IRQ_LOWEST_OFFSET + 0)
91#define BSP_CPM_IRQ_I2C                 (BSP_CPM_IRQ_LOWEST_OFFSET + 1)
92#define BSP_CPM_IRQ_SPI                 (BSP_CPM_IRQ_LOWEST_OFFSET + 2)
93#define BSP_CPM_IRQ_RISC_TIMERS         (BSP_CPM_IRQ_LOWEST_OFFSET + 3)
94#define BSP_CPM_IRQ_SMC1                (BSP_CPM_IRQ_LOWEST_OFFSET + 4)
95#define BSP_CPM_IRQ_SMC2                (BSP_CPM_IRQ_LOWEST_OFFSET + 5)
96#define BSP_CPM_IRQ_IDMA1               (BSP_CPM_IRQ_LOWEST_OFFSET + 6)
97#define BSP_CPM_IRQ_IDMA2               (BSP_CPM_IRQ_LOWEST_OFFSET + 7)
98#define BSP_CPM_IRQ_IDMA3               (BSP_CPM_IRQ_LOWEST_OFFSET + 8)
99#define BSP_CPM_IRQ_IDMA4               (BSP_CPM_IRQ_LOWEST_OFFSET + 9)
100#define BSP_CPM_IRQ_SDMA                (BSP_CPM_IRQ_LOWEST_OFFSET + 10)
101
102#define BSP_CPM_IRQ_TIMER_1             (BSP_CPM_IRQ_LOWEST_OFFSET + 12)
103#define BSP_CPM_IRQ_TIMER_2             (BSP_CPM_IRQ_LOWEST_OFFSET + 13)
104#define BSP_CPM_IRQ_TIMER_3             (BSP_CPM_IRQ_LOWEST_OFFSET + 14)
105#define BSP_CPM_IRQ_TIMER_4             (BSP_CPM_IRQ_LOWEST_OFFSET + 15)
106#define BSP_CPM_IRQ_TMCNT               (BSP_CPM_IRQ_LOWEST_OFFSET + 16)
107#define BSP_CPM_IRQ_PIT                 (BSP_CPM_IRQ_LOWEST_OFFSET + 17)
108
109#define BSP_CPM_IRQ_IRQ1                (BSP_CPM_IRQ_LOWEST_OFFSET + 19)
110#define BSP_CPM_IRQ_IRQ2                (BSP_CPM_IRQ_LOWEST_OFFSET + 20)
111#define BSP_CPM_IRQ_IRQ3                (BSP_CPM_IRQ_LOWEST_OFFSET + 21)
112#define BSP_CPM_IRQ_IRQ4                (BSP_CPM_IRQ_LOWEST_OFFSET + 22)
113#define BSP_CPM_IRQ_IRQ5                (BSP_CPM_IRQ_LOWEST_OFFSET + 23)
114#define BSP_CPM_IRQ_IRQ6                (BSP_CPM_IRQ_LOWEST_OFFSET + 24)
115#define BSP_CPM_IRQ_IRQ7                (BSP_CPM_IRQ_LOWEST_OFFSET + 25)
116
117#define BSP_CPM_IRQ_FCC1                (BSP_CPM_IRQ_LOWEST_OFFSET + 32)
118#define BSP_CPM_IRQ_FCC2                (BSP_CPM_IRQ_LOWEST_OFFSET + 33)
119#define BSP_CPM_IRQ_FCC3                (BSP_CPM_IRQ_LOWEST_OFFSET + 34)
120#define BSP_CPM_IRQ_MCC1                (BSP_CPM_IRQ_LOWEST_OFFSET + 36)
121#define BSP_CPM_IRQ_MCC2                (BSP_CPM_IRQ_LOWEST_OFFSET + 37)
122
123#define BSP_CPM_IRQ_SCC1                (BSP_CPM_IRQ_LOWEST_OFFSET + 40)
124#define BSP_CPM_IRQ_SCC2                (BSP_CPM_IRQ_LOWEST_OFFSET + 41)
125#define BSP_CPM_IRQ_SCC3                (BSP_CPM_IRQ_LOWEST_OFFSET + 42)
126#define BSP_CPM_IRQ_SCC4                (BSP_CPM_IRQ_LOWEST_OFFSET + 43)
127
128#define BSP_CPM_IRQ_PC15                (BSP_CPM_IRQ_LOWEST_OFFSET + 48)
129#define BSP_CPM_IRQ_PC14                (BSP_CPM_IRQ_LOWEST_OFFSET + 49)
130#define BSP_CPM_IRQ_PC13                (BSP_CPM_IRQ_LOWEST_OFFSET + 50)
131#define BSP_CPM_IRQ_PC12                (BSP_CPM_IRQ_LOWEST_OFFSET + 51)
132#define BSP_CPM_IRQ_PC11                (BSP_CPM_IRQ_LOWEST_OFFSET + 52)
133#define BSP_CPM_IRQ_PC10                (BSP_CPM_IRQ_LOWEST_OFFSET + 53)
134#define BSP_CPM_IRQ_PC9                 (BSP_CPM_IRQ_LOWEST_OFFSET + 54)
135#define BSP_CPM_IRQ_PC8                 (BSP_CPM_IRQ_LOWEST_OFFSET + 55)
136#define BSP_CPM_IRQ_PC7                 (BSP_CPM_IRQ_LOWEST_OFFSET + 56)
137#define BSP_CPM_IRQ_PC6                 (BSP_CPM_IRQ_LOWEST_OFFSET + 57)
138#define BSP_CPM_IRQ_PC5                 (BSP_CPM_IRQ_LOWEST_OFFSET + 58)
139#define BSP_CPM_IRQ_PC4                 (BSP_CPM_IRQ_LOWEST_OFFSET + 59)
140#define BSP_CPM_IRQ_PC3                 (BSP_CPM_IRQ_LOWEST_OFFSET + 60)
141#define BSP_CPM_IRQ_PC2                 (BSP_CPM_IRQ_LOWEST_OFFSET + 61)
142#define BSP_CPM_IRQ_PC1                 (BSP_CPM_IRQ_LOWEST_OFFSET + 62)
143#define BSP_CPM_IRQ_PC0                 (BSP_CPM_IRQ_LOWEST_OFFSET + 63)
144
145    /*
146     * Some Processor exception handled as rtems IRQ symbolic name definition
147     */
148#define BSP_DECREMENTER                 (BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
149#define BSP_PERIODIC_TIMER              (BSP_DECREMENTER)
150
151
152#define CPM_INTERRUPT
153
154/*-------------------------------------------------------------------------+
155| Function Prototypes.
156+--------------------------------------------------------------------------*/
157/*
158 * ------------------------ PPC CPM Mngt Routines -------
159 */
160
161/*
162 * function to disable a particular irq. After calling
163 * this function, even if the device asserts the interrupt line it will
164 * not be propagated further to the processor
165 */
166int BSP_irq_disable_at_cpm        (const rtems_irq_number irqLine);
167/*
168 * function to enable a particular irq. After calling
169 * this function, if the device asserts the interrupt line it will
170 * be propagated further to the processor
171 */
172int BSP_irq_enable_at_cpm               (const rtems_irq_number irqLine);
173/*
174 * function to acknoledge a particular irq. After calling
175 * this function, if a device asserts an enabled interrupt line it will
176 * be propagated further to the processor. Mainly usefull for people
177 * writting raw handlers as this is automagically done for rtems managed
178 * handlers.
179 */
180int BSP_irq_ack_at_cpm                  (const rtems_irq_number irqLine);
181/*
182 * function to check if a particular irq is enabled. After calling
183 */
184int BSP_irq_enabled_at_cpm      (const rtems_irq_number irqLine);
185
186extern void BSP_rtems_irq_mng_init(unsigned cpuId);
187
188#ifdef __cplusplus
189}
190#endif
191
192#endif
193
194#endif
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