source: rtems/c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.c @ 4e0dd1f

5
Last change on this file since 4e0dd1f was 4e0dd1f, checked in by Sebastian Huber <sebastian.huber@…>, on 09/20/17 at 07:35:10

bsp/mpc8260ads: Fix for RTEMS_DEBUG
  • Property mode set to 100644
File size: 11.2 KB
Line 
1/*
2 *
3 *  This file contains the implementation of the function described in irq.h
4 *
5 *  Copyright (C) 1998, 1999 valette@crf.canon.fr
6 *
7 *  Modified for mpc8260 Andy Dachs <a.dachs@sstl.co.uk>
8 *  Surrey Satellite Technology Limited, 2000
9 *    21/4/2002 Added support for nested interrupts and improved
10 *    masking operations.  Now we compute priority mask based
11 *     on table in irq_init.c
12 *
13 *  The license and distribution terms for this file may be
14 *  found in the file LICENSE in this distribution or at
15 *  http://www.rtems.org/license/LICENSE.
16 */
17
18#include <bsp.h>
19#include <bsp/irq.h>
20#include <bsp/irq-generic.h>
21#include <rtems.h>
22#include <rtems/bspIo.h>
23#include <bsp/vectors.h>
24#include <mpc8260.h>
25
26/*
27 * Check if symbolic IRQ name is an CPM IRQ
28 */
29static inline int is_cpm_irq(const rtems_irq_number irqLine)
30{
31  return (((int) irqLine <= BSP_CPM_IRQ_MAX_OFFSET) &
32      ((int) irqLine >= BSP_CPM_IRQ_LOWEST_OFFSET)
33  );
34}
35
36typedef struct {
37  uint32_t         mask_h;  /* mask for sipnr_h and simr_h */
38  uint32_t         mask_l;  /* mask for sipnr_l and simr_l */
39  uint32_t         priority_h;  /* mask this and lower priority ints */
40  uint32_t         priority_l;
41} m82xxIrqMasks_t;
42
43static unsigned char irqPrioTable[BSP_CPM_IRQ_NUMBER]={
44  /*
45   * actual priorities for interrupt :
46   */
47  /*
48   * CPM Interrupts
49   */
50  0,  45, 63, 44, 66, 68, 35, 39, 50, 62, 34,  0,  30, 40, 52, 58,
51  2,  3,  0,  5,  15, 16, 17, 18, 49, 51,  0,  0,  0,  0,  0,  0,
52  6,  7,  8,  0,  11, 12, 0,  0,  20, 21, 22,  23, 0,  0,  0,  0,
53  29, 31, 33, 37, 38, 41, 47, 48, 55, 56, 57,  60, 64, 65, 69, 70,
54
55};
56
57/*
58 *  Mask fields should have a '1' in the bit position for that
59 *  interrupt.
60 *  Priority masks calculated later based on priority table
61 */
62
63static m82xxIrqMasks_t SIU_MaskBit[BSP_CPM_IRQ_NUMBER] =
64{
65  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* err */
66  { 0x00000000, 0x00008000, 0x00000000, 0x00000000 }, /* i2c */
67  { 0x00000000, 0x00004000, 0x00000000, 0x00000000 }, /* spi */
68  { 0x00000000, 0x00002000, 0x00000000, 0x00000000 }, /* rtt */
69  { 0x00000000, 0x00001000, 0x00000000, 0x00000000 }, /* smc1 */
70  { 0x00000000, 0x00000800, 0x00000000, 0x00000000 }, /* smc2 */
71  { 0x00000000, 0x00000400, 0x00000000, 0x00000000 }, /* idma1 */
72  { 0x00000000, 0x00000200, 0x00000000, 0x00000000 }, /* idma2 */
73  { 0x00000000, 0x00000100, 0x00000000, 0x00000000 }, /* idma3 */
74  { 0x00000000, 0x00000080, 0x00000000, 0x00000000 }, /* idma4 */
75  { 0x00000000, 0x00000040, 0x00000000, 0x00000000 }, /* sdma */
76  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
77  { 0x00000000, 0x00000010, 0x00000000, 0x00000000 }, /* tmr1 */
78  { 0x00000000, 0x00000008, 0x00000000, 0x00000000 }, /* tmr2 */
79  { 0x00000000, 0x00000004, 0x00000000, 0x00000000 }, /* tmr3 */
80  { 0x00000000, 0x00000002, 0x00000000, 0x00000000 }, /* tmr4 */
81  { 0x00000004, 0x00000000, 0x00000000, 0x00000000 }, /* tmcnt */
82  { 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* pit */
83  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
84  { 0x00004000, 0x00000000, 0x00000000, 0x00000000 }, /* irq1 */
85  { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* irq2 */
86  { 0x00001000, 0x00000000, 0x00000000, 0x00000000 }, /* irq3 */
87  { 0x00000800, 0x00000000, 0x00000000, 0x00000000 }, /* irq4 */
88  { 0x00000400, 0x00000000, 0x00000000, 0x00000000 }, /* irq5 */
89  { 0x00000200, 0x00000000, 0x00000000, 0x00000000 }, /* irq6 */
90  { 0x00000100, 0x00000000, 0x00000000, 0x00000000 }, /* irq7 */
91  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
92  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
93  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
94  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
95  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
96  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
97  { 0x00000000, 0x80000000, 0x00000000, 0x00000000 }, /* fcc1 */
98  { 0x00000000, 0x40000000, 0x00000000, 0x00000000 }, /* fcc2 */
99  { 0x00000000, 0x20000000, 0x00000000, 0x00000000 }, /* fcc3 */
100  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
101  { 0x00000000, 0x08000000, 0x00000000, 0x00000000 }, /* mcc1 */
102  { 0x00000000, 0x04000000, 0x00000000, 0x00000000 }, /* mcc2 */
103  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
104  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
105  { 0x00000000, 0x00800000, 0x00000000, 0x00000000 }, /* scc1 */
106  { 0x00000000, 0x00400000, 0x00000000, 0x00000000 }, /* scc2 */
107  { 0x00000000, 0x00200000, 0x00000000, 0x00000000 }, /* scc3 */
108  { 0x00000000, 0x00100000, 0x00000000, 0x00000000 }, /* scc4 */
109  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
110  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
111  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
112  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
113  { 0x00010000, 0x00000000, 0x00000000, 0x00000000 }, /* pc15 */
114  { 0x00020000, 0x00000000, 0x00000000, 0x00000000 }, /* pc14 */
115  { 0x00040000, 0x00000000, 0x00000000, 0x00000000 }, /* pc13 */
116  { 0x00080000, 0x00000000, 0x00000000, 0x00000000 }, /* pc12 */
117  { 0x00100000, 0x00000000, 0x00000000, 0x00000000 }, /* pc11 */
118  { 0x00200000, 0x00000000, 0x00000000, 0x00000000 }, /* pc10 */
119  { 0x00400000, 0x00000000, 0x00000000, 0x00000000 }, /* pc9 */
120  { 0x00800000, 0x00000000, 0x00000000, 0x00000000 }, /* pc8 */
121  { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc7 */
122  { 0x02000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc6 */
123  { 0x04000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc5 */
124  { 0x08000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc4 */
125  { 0x10000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc3 */
126  { 0x20000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc2 */
127  { 0x40000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc1 */
128  { 0x80000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc0 */
129
130};
131
132/*
133 * ------------------------ RTEMS Irq helper functions ----------------
134 */
135
136/*
137 * Caution : this function assumes the variable "internal_config"
138 * is already set and that the tables it contains are still valid
139 * and accessible.
140 */
141static void compute_SIU_IvectMask_from_prio (void)
142{
143  /*
144   * The actual masks defined
145   * correspond to the priorities defined
146   * for the SIU in irq_init.c.
147   */
148
149   int i,j;
150
151   for( i=0; i<BSP_CPM_IRQ_NUMBER; i++ )
152   {
153     for( j=0;j<BSP_CPM_IRQ_NUMBER; j++ )
154       if( irqPrioTable[j] < irqPrioTable[i] )
155       {
156        SIU_MaskBit[i].priority_h |= SIU_MaskBit[j].mask_h;
157        SIU_MaskBit[i].priority_l |= SIU_MaskBit[j].mask_l;
158      }
159   }
160
161}
162
163
164int BSP_irq_enable_at_cpm(const rtems_irq_number irqLine)
165{
166  int cpm_irq_index;
167
168  if (!is_cpm_irq(irqLine))
169    return 1;
170
171  cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET);
172
173  m8260.simr_h |= SIU_MaskBit[cpm_irq_index].mask_h;
174  m8260.simr_l |= SIU_MaskBit[cpm_irq_index].mask_l;
175
176  return 0;
177}
178
179int BSP_irq_disable_at_cpm(const rtems_irq_number irqLine)
180{
181  int cpm_irq_index;
182
183  if (!is_cpm_irq(irqLine))
184    return 1;
185
186  cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET);
187
188  m8260.simr_h &= ~(SIU_MaskBit[cpm_irq_index].mask_h);
189  m8260.simr_l &= ~(SIU_MaskBit[cpm_irq_index].mask_l);
190
191  return 0;
192}
193
194int BSP_irq_enabled_at_cpm(const rtems_irq_number irqLine)
195{
196       int cpm_irq_index;
197
198       if (!is_cpm_irq(irqLine))
199               return 0;
200
201       cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET);
202
203       return ((m8260.simr_h & SIU_MaskBit[cpm_irq_index].mask_h) ||
204                   (m8260.simr_l & SIU_MaskBit[cpm_irq_index].mask_l));
205}
206
207#ifdef DISPATCH_HANDLER_STAT
208volatile unsigned int maxLoop = 0;
209#endif
210
211/*
212 * High level IRQ handler called from shared_raw_irq_code_entry
213 */
214static int C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned excNum)
215{
216  register unsigned int irq;
217#if 0
218  register unsigned oldMask;          /* old siu pic masks */
219#endif
220  register unsigned msr;
221  register unsigned new_msr;
222  register unsigned old_simr_h;
223  register unsigned old_simr_l;
224#ifdef DISPATCH_HANDLER_STAT
225  unsigned loopCounter;
226#endif
227
228  /*
229   * Handle decrementer interrupt
230   */
231  if (excNum == ASM_DEC_VECTOR) {
232    _CPU_MSR_GET(msr);
233    new_msr = msr | MSR_EE;
234    _CPU_MSR_SET(new_msr);
235
236    bsp_interrupt_handler_dispatch(BSP_DECREMENTER);
237
238    _CPU_MSR_SET(msr);
239
240    return 0;
241  }
242
243  /*
244   * Handle external interrupt generated by SIU on PPC core
245   */
246#ifdef DISPATCH_HANDLER_STAT
247  loopCounter = 0;
248#endif
249
250  while (1) {
251
252    if( ((m8260.sipnr_h & m8260.simr_h) | (m8260.sipnr_l & m8260.simr_l)) == 0 ) {
253#ifdef DISPATCH_HANDLER_STAT
254      if (loopCounter >  maxLoop) maxLoop = loopCounter;
255#endif
256      break;
257    }
258
259    irq = (m8260.sivec >> 26) + BSP_CPM_IRQ_LOWEST_OFFSET;
260
261    /* Clear mask and pending register */
262    if( irq <= BSP_CPM_IRQ_MAX_OFFSET ) {
263      /* save interrupt masks */
264      old_simr_h = m8260.simr_h;
265      old_simr_l = m8260.simr_l;
266
267      /* mask off current interrupt and lower priority ones */
268      m8260.simr_h &= SIU_MaskBit[irq].priority_h;
269      m8260.simr_l &= SIU_MaskBit[irq].priority_l;
270
271      /* clear pending bit */
272      m8260.sipnr_h |= SIU_MaskBit[irq].mask_h;
273      m8260.sipnr_l |= SIU_MaskBit[irq].mask_l;
274
275      /*
276       * make sure, that the masking operations in
277       * ICTL and MSR are executed in order
278       */
279      __asm__ volatile("sync":::"memory");
280
281      /* re-enable external exceptions */
282      _CPU_MSR_GET(msr);
283      new_msr = msr | MSR_EE;
284      _CPU_MSR_SET(new_msr);
285
286      /* call handler */
287      bsp_interrupt_handler_dispatch(irq);
288
289      /* disable exceptions again */
290      _CPU_MSR_SET(msr);
291
292      /*
293       * make sure, that the masking operations in
294       * ICTL and MSR are executed in order
295       */
296      __asm__ volatile("sync":::"memory");
297
298      /* restore interrupt masks */
299      m8260.simr_h = old_simr_h;
300      m8260.simr_l = old_simr_l;
301
302    }
303#ifdef DISPATCH_HANDLER_STAT
304    ++ loopCounter;
305#endif
306  }
307  return 0;
308}
309
310/*
311 * Initialize CPM interrupt management
312 */
313static void
314BSP_CPM_irq_init(void)
315{
316   m8260.simr_l = 0;
317   m8260.simr_h = 0;
318   m8260.sipnr_l = 0xffffffff;
319   m8260.sipnr_h = 0xffffffff;
320   m8260.sicr = 0;
321
322  /*
323   * Initialize the interrupt priorities.
324   */
325   m8260.siprr   = 0x05309770;  /* reset value */
326   m8260.scprr_h = 0x05309770;  /* reset value */
327   m8260.scprr_l = 0x05309770;  /* reset value */
328
329}
330
331void bsp_interrupt_vector_enable( rtems_vector_number irqnum)
332{
333  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(irqnum));
334
335  if (is_cpm_irq(irqnum)) {
336    /*
337     * Enable interrupt at PIC level
338     */
339    BSP_irq_enable_at_cpm (irqnum);
340  }
341}
342
343void bsp_interrupt_vector_disable( rtems_vector_number irqnum)
344{
345  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
346
347  if (is_cpm_irq(irqnum)) {
348    /*
349     * disable interrupt at PIC level
350     */
351    BSP_irq_disable_at_cpm (irqnum);
352  }
353}
354
355rtems_status_code bsp_interrupt_facility_initialize()
356{
357  /* Install exception handler */
358  if (ppc_exc_set_handler( ASM_EXT_VECTOR, C_dispatch_irq_handler)) {
359    return RTEMS_IO_ERROR;
360  }
361  if (ppc_exc_set_handler( ASM_DEC_VECTOR, C_dispatch_irq_handler)) {
362    return RTEMS_IO_ERROR;
363  }
364
365  /* Fill in priority masks */
366  compute_SIU_IvectMask_from_prio();
367
368  /* Initialize the interrupt controller */
369  BSP_CPM_irq_init();
370
371  return RTEMS_SUCCESSFUL;
372}
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