1 | /* |
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2 | * |
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3 | * This file contains the implementation of the function described in irq.h |
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4 | * |
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5 | * Copyright (C) 1998, 1999 valette@crf.canon.fr |
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6 | * |
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7 | * Modified for mpc8260 Andy Dachs <a.dachs@sstl.co.uk> |
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8 | * Surrey Satellite Technology Limited, 2000 |
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9 | + * 21/4/2002 Added support for nested interrupts and improved |
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10 | + * masking operations. Now we compute priority mask based |
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11 | + * on table in irq_init.c |
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12 | * |
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13 | * The license and distribution terms for this file may be |
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14 | * found in found in the file LICENSE in this distribution or at |
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15 | * http://www.rtems.com/license/LICENSE. |
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16 | * |
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17 | * $Id$ |
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18 | */ |
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19 | |
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20 | #include <bsp.h> |
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21 | #include <bsp/irq.h> |
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22 | #include <rtems.h> |
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23 | #include <rtems/score/apiext.h> |
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24 | #include <rtems/bspIo.h> |
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25 | #include <libcpu/raw_exception.h> |
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26 | #include <bsp/vectors.h> |
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27 | #include <mpc8260.h> |
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28 | |
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29 | /* |
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30 | * default handler connected on each irq after bsp initialization |
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31 | */ |
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32 | static rtems_irq_connect_data default_rtems_entry; |
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33 | |
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34 | /* |
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35 | * location used to store initial tables used for interrupt |
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36 | * management. |
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37 | */ |
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38 | static rtems_irq_global_settings* internal_config; |
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39 | static rtems_irq_connect_data* rtems_hdl_tbl; |
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40 | |
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41 | /* |
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42 | * Check if symbolic IRQ name is an CPM IRQ |
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43 | */ |
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44 | static inline int is_cpm_irq(const rtems_irq_number irqLine) |
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45 | { |
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46 | return (((int) irqLine <= BSP_CPM_IRQ_MAX_OFFSET) & |
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47 | ((int) irqLine >= BSP_CPM_IRQ_LOWEST_OFFSET) |
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48 | ); |
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49 | } |
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50 | |
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51 | /* |
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52 | * Check if symbolic IRQ name is a Processor IRQ |
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53 | */ |
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54 | static inline int is_processor_irq(const rtems_irq_number irqLine) |
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55 | { |
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56 | return (((int) irqLine <= BSP_PROCESSOR_IRQ_MAX_OFFSET) & |
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57 | ((int) irqLine >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) |
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58 | ); |
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59 | } |
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60 | |
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61 | typedef struct { |
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62 | uint32_t mask_h; /* mask for sipnr_h and simr_h */ |
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63 | uint32_t mask_l; /* mask for sipnr_l and simr_l */ |
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64 | uint32_t priority_h; /* mask this and lower priority ints */ |
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65 | uint32_t priority_l; |
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66 | } m82xxIrqMasks_t; |
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67 | |
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68 | /* |
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69 | * Mask fields should have a '1' in the bit position for that |
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70 | * interrupt. |
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71 | * Priority masks calculated later based on priority table |
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72 | */ |
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73 | |
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74 | static m82xxIrqMasks_t SIU_MaskBit[BSP_CPM_IRQ_NUMBER] = |
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75 | { |
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76 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* err */ |
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77 | { 0x00000000, 0x00008000, 0x00000000, 0x00000000 }, /* i2c */ |
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78 | { 0x00000000, 0x00004000, 0x00000000, 0x00000000 }, /* spi */ |
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79 | { 0x00000000, 0x00002000, 0x00000000, 0x00000000 }, /* rtt */ |
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80 | { 0x00000000, 0x00001000, 0x00000000, 0x00000000 }, /* smc1 */ |
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81 | { 0x00000000, 0x00000800, 0x00000000, 0x00000000 }, /* smc2 */ |
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82 | { 0x00000000, 0x00000400, 0x00000000, 0x00000000 }, /* idma1 */ |
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83 | { 0x00000000, 0x00000200, 0x00000000, 0x00000000 }, /* idma2 */ |
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84 | { 0x00000000, 0x00000100, 0x00000000, 0x00000000 }, /* idma3 */ |
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85 | { 0x00000000, 0x00000080, 0x00000000, 0x00000000 }, /* idma4 */ |
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86 | { 0x00000000, 0x00000040, 0x00000000, 0x00000000 }, /* sdma */ |
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87 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */ |
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88 | { 0x00000000, 0x00000010, 0x00000000, 0x00000000 }, /* tmr1 */ |
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89 | { 0x00000000, 0x00000008, 0x00000000, 0x00000000 }, /* tmr2 */ |
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90 | { 0x00000000, 0x00000004, 0x00000000, 0x00000000 }, /* tmr3 */ |
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91 | { 0x00000000, 0x00000002, 0x00000000, 0x00000000 }, /* tmr4 */ |
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92 | { 0x00000004, 0x00000000, 0x00000000, 0x00000000 }, /* tmcnt */ |
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93 | { 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* pit */ |
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94 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */ |
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95 | { 0x00004000, 0x00000000, 0x00000000, 0x00000000 }, /* irq1 */ |
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96 | { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* irq2 */ |
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97 | { 0x00001000, 0x00000000, 0x00000000, 0x00000000 }, /* irq3 */ |
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98 | { 0x00000800, 0x00000000, 0x00000000, 0x00000000 }, /* irq4 */ |
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99 | { 0x00000400, 0x00000000, 0x00000000, 0x00000000 }, /* irq5 */ |
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100 | { 0x00000200, 0x00000000, 0x00000000, 0x00000000 }, /* irq6 */ |
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101 | { 0x00000100, 0x00000000, 0x00000000, 0x00000000 }, /* irq7 */ |
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102 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */ |
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103 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */ |
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104 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */ |
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105 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */ |
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106 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */ |
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107 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */ |
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108 | { 0x00000000, 0x80000000, 0x00000000, 0x00000000 }, /* fcc1 */ |
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109 | { 0x00000000, 0x40000000, 0x00000000, 0x00000000 }, /* fcc2 */ |
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110 | { 0x00000000, 0x20000000, 0x00000000, 0x00000000 }, /* fcc3 */ |
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111 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */ |
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112 | { 0x00000000, 0x08000000, 0x00000000, 0x00000000 }, /* mcc1 */ |
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113 | { 0x00000000, 0x04000000, 0x00000000, 0x00000000 }, /* mcc2 */ |
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114 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */ |
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115 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */ |
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116 | { 0x00000000, 0x00800000, 0x00000000, 0x00000000 }, /* scc1 */ |
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117 | { 0x00000000, 0x00400000, 0x00000000, 0x00000000 }, /* scc2 */ |
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118 | { 0x00000000, 0x00200000, 0x00000000, 0x00000000 }, /* scc3 */ |
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119 | { 0x00000000, 0x00100000, 0x00000000, 0x00000000 }, /* scc4 */ |
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120 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */ |
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121 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */ |
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122 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */ |
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123 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */ |
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124 | { 0x00010000, 0x00000000, 0x00000000, 0x00000000 }, /* pc15 */ |
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125 | { 0x00020000, 0x00000000, 0x00000000, 0x00000000 }, /* pc14 */ |
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126 | { 0x00040000, 0x00000000, 0x00000000, 0x00000000 }, /* pc13 */ |
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127 | { 0x00080000, 0x00000000, 0x00000000, 0x00000000 }, /* pc12 */ |
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128 | { 0x00100000, 0x00000000, 0x00000000, 0x00000000 }, /* pc11 */ |
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129 | { 0x00200000, 0x00000000, 0x00000000, 0x00000000 }, /* pc10 */ |
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130 | { 0x00400000, 0x00000000, 0x00000000, 0x00000000 }, /* pc9 */ |
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131 | { 0x00800000, 0x00000000, 0x00000000, 0x00000000 }, /* pc8 */ |
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132 | { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc7 */ |
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133 | { 0x02000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc6 */ |
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134 | { 0x04000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc5 */ |
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135 | { 0x08000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc4 */ |
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136 | { 0x10000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc3 */ |
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137 | { 0x20000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc2 */ |
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138 | { 0x40000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc1 */ |
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139 | { 0x80000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc0 */ |
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140 | |
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141 | }; |
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142 | |
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143 | void dump_irq_masks(void ) |
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144 | { |
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145 | int i; |
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146 | for( i=0; i<BSP_CPM_IRQ_NUMBER;i++ ) |
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147 | { |
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148 | printk( "%04d: %08X %08X\n", |
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149 | i, |
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150 | SIU_MaskBit[i].priority_h, |
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151 | SIU_MaskBit[i].priority_l |
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152 | ); |
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153 | } |
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154 | } |
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155 | |
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156 | /* |
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157 | * ------------------------ RTEMS Irq helper functions ---------------- |
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158 | */ |
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159 | |
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160 | /* |
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161 | * Caution : this function assumes the variable "internal_config" |
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162 | * is already set and that the tables it contains are still valid |
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163 | * and accessible. |
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164 | */ |
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165 | static void compute_SIU_IvectMask_from_prio (void) |
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166 | { |
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167 | /* |
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168 | * The actual masks defined |
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169 | * correspond to the priorities defined |
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170 | * for the SIU in irq_init.c. |
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171 | */ |
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172 | |
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173 | int i,j; |
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174 | |
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175 | for( i=0; i<BSP_CPM_IRQ_NUMBER; i++ ) |
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176 | { |
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177 | for( j=0;j<BSP_CPM_IRQ_NUMBER; j++ ) |
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178 | if( internal_config->irqPrioTbl[j] < internal_config->irqPrioTbl[i] ) |
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179 | { |
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180 | SIU_MaskBit[i].priority_h |= SIU_MaskBit[j].mask_h; |
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181 | SIU_MaskBit[i].priority_l |= SIU_MaskBit[j].mask_l; |
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182 | } |
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183 | } |
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184 | |
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185 | } |
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186 | |
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187 | /* |
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188 | * This function check that the value given for the irq line |
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189 | * is valid. |
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190 | */ |
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191 | |
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192 | static int isValidInterrupt(int irq) |
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193 | { |
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194 | if ( (irq < BSP_LOWEST_OFFSET) || (irq > BSP_MAX_OFFSET) ) |
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195 | return 0; |
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196 | return 1; |
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197 | } |
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198 | |
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199 | int BSP_irq_enable_at_cpm(const rtems_irq_number irqLine) |
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200 | { |
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201 | int cpm_irq_index; |
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202 | |
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203 | if (!is_cpm_irq(irqLine)) |
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204 | return 1; |
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205 | |
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206 | cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET); |
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207 | |
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208 | m8260.simr_h |= SIU_MaskBit[cpm_irq_index].mask_h; |
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209 | m8260.simr_l |= SIU_MaskBit[cpm_irq_index].mask_l; |
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210 | |
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211 | return 0; |
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212 | } |
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213 | |
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214 | int BSP_irq_disable_at_cpm(const rtems_irq_number irqLine) |
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215 | { |
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216 | int cpm_irq_index; |
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217 | |
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218 | if (!is_cpm_irq(irqLine)) |
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219 | return 1; |
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220 | |
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221 | cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET); |
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222 | |
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223 | m8260.simr_h &= ~(SIU_MaskBit[cpm_irq_index].mask_h); |
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224 | m8260.simr_l &= ~(SIU_MaskBit[cpm_irq_index].mask_l); |
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225 | |
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226 | return 0; |
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227 | } |
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228 | |
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229 | int BSP_irq_enabled_at_cpm(const rtems_irq_number irqLine) |
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230 | { |
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231 | int cpm_irq_index; |
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232 | |
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233 | if (!is_cpm_irq(irqLine)) |
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234 | return 0; |
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235 | |
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236 | cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET); |
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237 | |
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238 | return ((m8260.simr_h & SIU_MaskBit[cpm_irq_index].mask_h) || |
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239 | (m8260.simr_l & SIU_MaskBit[cpm_irq_index].mask_l)); |
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240 | } |
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241 | |
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242 | /* |
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243 | * ------------------------ RTEMS Single Irq Handler Mngt Routines ---------------- |
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244 | */ |
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245 | |
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246 | int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) |
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247 | { |
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248 | rtems_interrupt_level level; |
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249 | |
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250 | if (!isValidInterrupt(irq->name)) { |
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251 | printk( "not a valid intr\n" ) ; |
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252 | return 0; |
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253 | } |
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254 | /* |
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255 | * Check if default handler is actually connected. If not issue an error. |
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256 | * You must first get the current handler via i386_get_current_idt_entry |
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257 | * and then disconnect it using i386_delete_idt_entry. |
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258 | * RATIONALE : to always have the same transition by forcing the user |
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259 | * to get the previous handler before accepting to disconnect. |
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260 | */ |
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261 | if (rtems_hdl_tbl[irq->name].hdl != default_rtems_entry.hdl) { |
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262 | printk( "Default handler not there\n" ); |
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263 | return 0; |
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264 | } |
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265 | |
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266 | rtems_interrupt_disable(level); |
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267 | |
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268 | /* |
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269 | * store the data provided by user |
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270 | */ |
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271 | rtems_hdl_tbl[irq->name] = *irq; |
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272 | |
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273 | if (is_cpm_irq(irq->name)) { |
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274 | /* |
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275 | * Enable interrupt at PIC level |
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276 | */ |
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277 | BSP_irq_enable_at_cpm (irq->name); |
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278 | } |
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279 | |
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280 | #if 0 |
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281 | if (is_processor_irq(irq->name)) { |
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282 | /* |
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283 | * Should Enable exception at processor level but not needed. Will restore |
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284 | * EE flags at the end of the routine anyway. |
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285 | */ |
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286 | } |
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287 | #endif |
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288 | |
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289 | /* |
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290 | * Enable interrupt on device |
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291 | */ |
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292 | if (irq->on) |
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293 | irq->on(irq); |
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294 | |
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295 | rtems_interrupt_enable(level); |
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296 | |
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297 | /* |
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298 | printk( "Enabled\n" ); |
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299 | */ |
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300 | return 1; |
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301 | } |
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302 | |
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303 | int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* irq) |
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304 | { |
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305 | if (!isValidInterrupt(irq->name)) { |
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306 | return 0; |
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307 | } |
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308 | *irq = rtems_hdl_tbl[irq->name]; |
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309 | return 1; |
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310 | } |
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311 | |
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312 | int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) |
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313 | { |
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314 | rtems_interrupt_level level; |
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315 | |
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316 | if (!isValidInterrupt(irq->name)) { |
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317 | return 0; |
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318 | } |
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319 | /* |
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320 | * Check if default handler is actually connected. If not issue an error. |
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321 | * You must first get the current handler via i386_get_current_idt_entry |
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322 | * and then disconnect it using i386_delete_idt_entry. |
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323 | * RATIONALE : to always have the same transition by forcing the user |
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324 | * to get the previous handler before accepting to disconnect. |
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325 | */ |
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326 | if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) { |
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327 | return 0; |
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328 | } |
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329 | rtems_interrupt_disable(level); |
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330 | |
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331 | if (is_cpm_irq(irq->name)) { |
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332 | /* |
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333 | * disable interrupt at PIC level |
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334 | */ |
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335 | BSP_irq_disable_at_cpm (irq->name); |
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336 | } |
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337 | |
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338 | if (is_processor_irq(irq->name)) { |
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339 | /* |
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340 | * disable exception at processor level |
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341 | */ |
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342 | } |
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343 | |
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344 | /* |
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345 | * Disable interrupt on device |
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346 | */ |
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347 | if (irq->off) |
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348 | irq->off(irq); |
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349 | |
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350 | /* |
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351 | * restore the default irq value |
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352 | */ |
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353 | rtems_hdl_tbl[irq->name] = default_rtems_entry; |
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354 | |
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355 | rtems_interrupt_enable(level); |
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356 | |
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357 | return 1; |
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358 | } |
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359 | |
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360 | /* |
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361 | * ------------------------ RTEMS Global Irq Handler Mngt Routines ---------------- |
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362 | */ |
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363 | |
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364 | int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config) |
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365 | { |
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366 | int i; |
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367 | rtems_interrupt_level level; |
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368 | |
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369 | /* |
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370 | * Store various code accelerators |
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371 | */ |
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372 | internal_config = config; |
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373 | default_rtems_entry = config->defaultEntry; |
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374 | rtems_hdl_tbl = config->irqHdlTbl; |
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375 | |
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376 | /* Fill in priority masks */ |
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377 | compute_SIU_IvectMask_from_prio(); |
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378 | |
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379 | rtems_interrupt_disable(level); |
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380 | /* |
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381 | * start with CPM IRQ |
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382 | */ |
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383 | for (i=BSP_CPM_IRQ_LOWEST_OFFSET; i < BSP_CPM_IRQ_LOWEST_OFFSET + BSP_CPM_IRQ_NUMBER ; i++) { |
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384 | if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { |
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385 | BSP_irq_enable_at_cpm (i); |
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386 | if (rtems_hdl_tbl[i].on) |
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387 | rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); |
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388 | } else { |
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389 | if (rtems_hdl_tbl[i].off) |
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390 | rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); |
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391 | BSP_irq_disable_at_cpm (i); |
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392 | } |
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393 | } |
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394 | |
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395 | /* |
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396 | * finish with Processor exceptions handled like IRQ |
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397 | */ |
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398 | for (i=BSP_PROCESSOR_IRQ_LOWEST_OFFSET; i < BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER; i++) { |
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399 | if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { |
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400 | if (rtems_hdl_tbl[i].on) |
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401 | rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); |
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402 | } else { |
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403 | if (rtems_hdl_tbl[i].off) |
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404 | rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); |
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405 | } |
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406 | } |
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407 | |
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408 | rtems_interrupt_enable(level); |
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409 | return 1; |
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410 | } |
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411 | |
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412 | int BSP_rtems_irq_mngt_get(rtems_irq_global_settings** config) |
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413 | { |
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414 | *config = internal_config; |
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415 | return 0; |
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416 | } |
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417 | |
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418 | #ifdef DISPATCH_HANDLER_STAT |
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419 | volatile unsigned int maxLoop = 0; |
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420 | #endif |
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421 | |
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422 | /* |
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423 | * High level IRQ handler called from shared_raw_irq_code_entry |
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424 | */ |
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425 | int C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) |
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426 | { |
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427 | register unsigned int irq; |
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428 | #if 0 |
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429 | register unsigned oldMask; /* old siu pic masks */ |
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430 | #endif |
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431 | register unsigned msr; |
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432 | register unsigned new_msr; |
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433 | register unsigned old_simr_h; |
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434 | register unsigned old_simr_l; |
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435 | #ifdef DISPATCH_HANDLER_STAT |
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436 | unsigned loopCounter; |
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437 | #endif |
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438 | |
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439 | /* |
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440 | * Handle decrementer interrupt |
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441 | */ |
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442 | if (excNum == ASM_DEC_VECTOR) { |
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443 | _CPU_MSR_GET(msr); |
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444 | new_msr = msr | MSR_EE; |
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445 | _CPU_MSR_SET(new_msr); |
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446 | |
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447 | rtems_hdl_tbl[BSP_DECREMENTER].hdl(rtems_hdl_tbl[BSP_DECREMENTER].handle); |
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448 | |
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449 | _CPU_MSR_SET(msr); |
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450 | |
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451 | return 0; |
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452 | } |
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453 | |
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454 | /* |
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455 | * Handle external interrupt generated by SIU on PPC core |
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456 | */ |
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457 | #ifdef DISPATCH_HANDLER_STAT |
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458 | loopCounter = 0; |
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459 | #endif |
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460 | |
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461 | while (1) { |
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462 | |
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463 | if( ((m8260.sipnr_h & m8260.simr_h) | (m8260.sipnr_l & m8260.simr_l)) == 0 ) { |
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464 | #ifdef DISPATCH_HANDLER_STAT |
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465 | if (loopCounter > maxLoop) maxLoop = loopCounter; |
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466 | #endif |
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467 | break; |
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468 | } |
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469 | |
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470 | irq = (m8260.sivec >> 26) + BSP_CPM_IRQ_LOWEST_OFFSET; |
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471 | |
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472 | /* Clear mask and pending register */ |
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473 | if( irq <= BSP_CPM_IRQ_MAX_OFFSET ) { |
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474 | /* save interrupt masks */ |
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475 | old_simr_h = m8260.simr_h; |
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476 | old_simr_l = m8260.simr_l; |
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477 | |
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478 | /* mask off current interrupt and lower priority ones */ |
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479 | m8260.simr_h &= SIU_MaskBit[irq].priority_h; |
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480 | m8260.simr_l &= SIU_MaskBit[irq].priority_l; |
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481 | |
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482 | /* clear pending bit */ |
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483 | m8260.sipnr_h |= SIU_MaskBit[irq].mask_h; |
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484 | m8260.sipnr_l |= SIU_MaskBit[irq].mask_l; |
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485 | |
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486 | /* |
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487 | * make sure, that the masking operations in |
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488 | * ICTL and MSR are executed in order |
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489 | */ |
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490 | asm volatile("sync":::"memory"); |
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491 | |
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492 | /* re-enable external exceptions */ |
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493 | _CPU_MSR_GET(msr); |
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494 | new_msr = msr | MSR_EE; |
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495 | _CPU_MSR_SET(new_msr); |
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496 | |
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497 | /* call handler */ |
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498 | rtems_hdl_tbl[irq].hdl(rtems_hdl_tbl[irq].handle); |
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499 | |
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500 | /* disable exceptions again */ |
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501 | _CPU_MSR_SET(msr); |
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502 | |
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503 | /* |
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504 | * make sure, that the masking operations in |
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505 | * ICTL and MSR are executed in order |
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506 | */ |
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507 | asm volatile("sync":::"memory"); |
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508 | |
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509 | /* restore interrupt masks */ |
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510 | m8260.simr_h = old_simr_h; |
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511 | m8260.simr_l = old_simr_l; |
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512 | |
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513 | } |
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514 | #ifdef DISPATCH_HANDLER_STAT |
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515 | ++ loopCounter; |
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516 | #endif |
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517 | } |
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518 | return 0; |
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519 | } |
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520 | |
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521 | void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx) |
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522 | { |
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523 | /* |
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524 | * Process pending signals that have not already been |
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525 | * processed by _Thread_Displatch. This happens quite |
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526 | * unfrequently : the ISR must have posted an action |
---|
527 | * to the current running thread. |
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528 | */ |
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529 | if ( _Thread_Do_post_task_switch_extension || |
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530 | _Thread_Executing->do_post_task_switch_extension ) { |
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531 | _Thread_Executing->do_post_task_switch_extension = FALSE; |
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532 | _API_extensions_Run_postswitch(); |
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533 | } |
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534 | |
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535 | /* |
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536 | * I plan to process other thread related events here. |
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537 | * This will include DEBUG session requested from keyboard... |
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538 | */ |
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539 | } |
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