source: rtems/c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.c @ 0f31fddc

4.115
Last change on this file since 0f31fddc was 0f31fddc, checked in by Sebastian Huber <sebastian.huber@…>, on 03/24/12 at 21:01:08

bsps: Add shared default IRQ handler
  • Property mode set to 100644
File size: 11.2 KB
Line 
1/*
2 *
3 *  This file contains the implementation of the function described in irq.h
4 *
5 *  Copyright (C) 1998, 1999 valette@crf.canon.fr
6 *
7 *  Modified for mpc8260 Andy Dachs <a.dachs@sstl.co.uk>
8 *  Surrey Satellite Technology Limited, 2000
9 *    21/4/2002 Added support for nested interrupts and improved
10 *    masking operations.  Now we compute priority mask based
11 *     on table in irq_init.c
12 *
13 *  The license and distribution terms for this file may be
14 *  found in the file LICENSE in this distribution or at
15 *  http://www.rtems.com/license/LICENSE.
16 *
17 *  $Id$
18 */
19
20#include <bsp.h>
21#include <bsp/irq.h>
22#include <bsp/irq-generic.h>
23#include <rtems.h>
24#include <rtems/bspIo.h>
25#include <bsp/vectors.h>
26#include <mpc8260.h>
27
28/*
29 * Check if symbolic IRQ name is an CPM IRQ
30 */
31static inline int is_cpm_irq(const rtems_irq_number irqLine)
32{
33  return (((int) irqLine <= BSP_CPM_IRQ_MAX_OFFSET) &
34      ((int) irqLine >= BSP_CPM_IRQ_LOWEST_OFFSET)
35  );
36}
37
38typedef struct {
39  uint32_t         mask_h;  /* mask for sipnr_h and simr_h */
40  uint32_t         mask_l;  /* mask for sipnr_l and simr_l */
41  uint32_t         priority_h;  /* mask this and lower priority ints */
42  uint32_t         priority_l;
43} m82xxIrqMasks_t;
44
45static unsigned char irqPrioTable[BSP_CPM_IRQ_NUMBER]={
46  /*
47   * actual priorities for interrupt :
48   */
49  /*
50   * CPM Interrupts
51   */
52  0,  45, 63, 44, 66, 68, 35, 39, 50, 62, 34,  0,  30, 40, 52, 58,
53  2,  3,  0,  5,  15, 16, 17, 18, 49, 51,  0,  0,  0,  0,  0,  0,
54  6,  7,  8,  0,  11, 12, 0,  0,  20, 21, 22,  23, 0,  0,  0,  0,
55  29, 31, 33, 37, 38, 41, 47, 48, 55, 56, 57,  60, 64, 65, 69, 70,
56
57};
58
59/*
60 *  Mask fields should have a '1' in the bit position for that
61 *  interrupt.
62 *  Priority masks calculated later based on priority table
63 */
64
65static m82xxIrqMasks_t SIU_MaskBit[BSP_CPM_IRQ_NUMBER] =
66{
67  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* err */
68  { 0x00000000, 0x00008000, 0x00000000, 0x00000000 }, /* i2c */
69  { 0x00000000, 0x00004000, 0x00000000, 0x00000000 }, /* spi */
70  { 0x00000000, 0x00002000, 0x00000000, 0x00000000 }, /* rtt */
71  { 0x00000000, 0x00001000, 0x00000000, 0x00000000 }, /* smc1 */
72  { 0x00000000, 0x00000800, 0x00000000, 0x00000000 }, /* smc2 */
73  { 0x00000000, 0x00000400, 0x00000000, 0x00000000 }, /* idma1 */
74  { 0x00000000, 0x00000200, 0x00000000, 0x00000000 }, /* idma2 */
75  { 0x00000000, 0x00000100, 0x00000000, 0x00000000 }, /* idma3 */
76  { 0x00000000, 0x00000080, 0x00000000, 0x00000000 }, /* idma4 */
77  { 0x00000000, 0x00000040, 0x00000000, 0x00000000 }, /* sdma */
78  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
79  { 0x00000000, 0x00000010, 0x00000000, 0x00000000 }, /* tmr1 */
80  { 0x00000000, 0x00000008, 0x00000000, 0x00000000 }, /* tmr2 */
81  { 0x00000000, 0x00000004, 0x00000000, 0x00000000 }, /* tmr3 */
82  { 0x00000000, 0x00000002, 0x00000000, 0x00000000 }, /* tmr4 */
83  { 0x00000004, 0x00000000, 0x00000000, 0x00000000 }, /* tmcnt */
84  { 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* pit */
85  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
86  { 0x00004000, 0x00000000, 0x00000000, 0x00000000 }, /* irq1 */
87  { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* irq2 */
88  { 0x00001000, 0x00000000, 0x00000000, 0x00000000 }, /* irq3 */
89  { 0x00000800, 0x00000000, 0x00000000, 0x00000000 }, /* irq4 */
90  { 0x00000400, 0x00000000, 0x00000000, 0x00000000 }, /* irq5 */
91  { 0x00000200, 0x00000000, 0x00000000, 0x00000000 }, /* irq6 */
92  { 0x00000100, 0x00000000, 0x00000000, 0x00000000 }, /* irq7 */
93  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
94  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
95  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
96  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
97  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
98  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
99  { 0x00000000, 0x80000000, 0x00000000, 0x00000000 }, /* fcc1 */
100  { 0x00000000, 0x40000000, 0x00000000, 0x00000000 }, /* fcc2 */
101  { 0x00000000, 0x20000000, 0x00000000, 0x00000000 }, /* fcc3 */
102  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
103  { 0x00000000, 0x08000000, 0x00000000, 0x00000000 }, /* mcc1 */
104  { 0x00000000, 0x04000000, 0x00000000, 0x00000000 }, /* mcc2 */
105  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
106  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
107  { 0x00000000, 0x00800000, 0x00000000, 0x00000000 }, /* scc1 */
108  { 0x00000000, 0x00400000, 0x00000000, 0x00000000 }, /* scc2 */
109  { 0x00000000, 0x00200000, 0x00000000, 0x00000000 }, /* scc3 */
110  { 0x00000000, 0x00100000, 0x00000000, 0x00000000 }, /* scc4 */
111  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
112  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
113  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
114  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
115  { 0x00010000, 0x00000000, 0x00000000, 0x00000000 }, /* pc15 */
116  { 0x00020000, 0x00000000, 0x00000000, 0x00000000 }, /* pc14 */
117  { 0x00040000, 0x00000000, 0x00000000, 0x00000000 }, /* pc13 */
118  { 0x00080000, 0x00000000, 0x00000000, 0x00000000 }, /* pc12 */
119  { 0x00100000, 0x00000000, 0x00000000, 0x00000000 }, /* pc11 */
120  { 0x00200000, 0x00000000, 0x00000000, 0x00000000 }, /* pc10 */
121  { 0x00400000, 0x00000000, 0x00000000, 0x00000000 }, /* pc9 */
122  { 0x00800000, 0x00000000, 0x00000000, 0x00000000 }, /* pc8 */
123  { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc7 */
124  { 0x02000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc6 */
125  { 0x04000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc5 */
126  { 0x08000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc4 */
127  { 0x10000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc3 */
128  { 0x20000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc2 */
129  { 0x40000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc1 */
130  { 0x80000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc0 */
131
132};
133
134/*
135 * ------------------------ RTEMS Irq helper functions ----------------
136 */
137
138/*
139 * Caution : this function assumes the variable "internal_config"
140 * is already set and that the tables it contains are still valid
141 * and accessible.
142 */
143static void compute_SIU_IvectMask_from_prio (void)
144{
145  /*
146   * The actual masks defined
147   * correspond to the priorities defined
148   * for the SIU in irq_init.c.
149   */
150
151   int i,j;
152
153   for( i=0; i<BSP_CPM_IRQ_NUMBER; i++ )
154   {
155     for( j=0;j<BSP_CPM_IRQ_NUMBER; j++ )
156       if( irqPrioTable[j] < irqPrioTable[i] )
157       {
158        SIU_MaskBit[i].priority_h |= SIU_MaskBit[j].mask_h;
159        SIU_MaskBit[i].priority_l |= SIU_MaskBit[j].mask_l;
160      }
161   }
162
163}
164
165
166int BSP_irq_enable_at_cpm(const rtems_irq_number irqLine)
167{
168  int cpm_irq_index;
169
170  if (!is_cpm_irq(irqLine))
171    return 1;
172
173  cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET);
174
175  m8260.simr_h |= SIU_MaskBit[cpm_irq_index].mask_h;
176  m8260.simr_l |= SIU_MaskBit[cpm_irq_index].mask_l;
177
178  return 0;
179}
180
181int BSP_irq_disable_at_cpm(const rtems_irq_number irqLine)
182{
183  int cpm_irq_index;
184
185  if (!is_cpm_irq(irqLine))
186    return 1;
187
188  cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET);
189
190  m8260.simr_h &= ~(SIU_MaskBit[cpm_irq_index].mask_h);
191  m8260.simr_l &= ~(SIU_MaskBit[cpm_irq_index].mask_l);
192
193  return 0;
194}
195
196int BSP_irq_enabled_at_cpm(const rtems_irq_number irqLine)
197{
198       int cpm_irq_index;
199
200       if (!is_cpm_irq(irqLine))
201               return 0;
202
203       cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET);
204
205       return ((m8260.simr_h & SIU_MaskBit[cpm_irq_index].mask_h) ||
206                   (m8260.simr_l & SIU_MaskBit[cpm_irq_index].mask_l));
207}
208
209#ifdef DISPATCH_HANDLER_STAT
210volatile unsigned int maxLoop = 0;
211#endif
212
213/*
214 * High level IRQ handler called from shared_raw_irq_code_entry
215 */
216int C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned excNum)
217{
218  register unsigned int irq;
219#if 0
220  register unsigned oldMask;          /* old siu pic masks */
221#endif
222  register unsigned msr;
223  register unsigned new_msr;
224  register unsigned old_simr_h;
225  register unsigned old_simr_l;
226#ifdef DISPATCH_HANDLER_STAT
227  unsigned loopCounter;
228#endif
229
230  /*
231   * Handle decrementer interrupt
232   */
233  if (excNum == ASM_DEC_VECTOR) {
234    _CPU_MSR_GET(msr);
235    new_msr = msr | MSR_EE;
236    _CPU_MSR_SET(new_msr);
237
238    bsp_interrupt_handler_dispatch(BSP_DECREMENTER);
239
240    _CPU_MSR_SET(msr);
241
242    return 0;
243  }
244
245  /*
246   * Handle external interrupt generated by SIU on PPC core
247   */
248#ifdef DISPATCH_HANDLER_STAT
249  loopCounter = 0;
250#endif
251
252  while (1) {
253
254    if( ((m8260.sipnr_h & m8260.simr_h) | (m8260.sipnr_l & m8260.simr_l)) == 0 ) {
255#ifdef DISPATCH_HANDLER_STAT
256      if (loopCounter >  maxLoop) maxLoop = loopCounter;
257#endif
258      break;
259    }
260
261    irq = (m8260.sivec >> 26) + BSP_CPM_IRQ_LOWEST_OFFSET;
262
263    /* Clear mask and pending register */
264    if( irq <= BSP_CPM_IRQ_MAX_OFFSET ) {
265      /* save interrupt masks */
266      old_simr_h = m8260.simr_h;
267      old_simr_l = m8260.simr_l;
268
269      /* mask off current interrupt and lower priority ones */
270      m8260.simr_h &= SIU_MaskBit[irq].priority_h;
271      m8260.simr_l &= SIU_MaskBit[irq].priority_l;
272
273      /* clear pending bit */
274      m8260.sipnr_h |= SIU_MaskBit[irq].mask_h;
275      m8260.sipnr_l |= SIU_MaskBit[irq].mask_l;
276
277      /*
278       * make sure, that the masking operations in
279       * ICTL and MSR are executed in order
280       */
281      __asm__ volatile("sync":::"memory");
282
283      /* re-enable external exceptions */
284      _CPU_MSR_GET(msr);
285      new_msr = msr | MSR_EE;
286      _CPU_MSR_SET(new_msr);
287
288      /* call handler */
289      bsp_interrupt_handler_dispatch(irq);
290
291      /* disable exceptions again */
292      _CPU_MSR_SET(msr);
293
294      /*
295       * make sure, that the masking operations in
296       * ICTL and MSR are executed in order
297       */
298      __asm__ volatile("sync":::"memory");
299
300      /* restore interrupt masks */
301      m8260.simr_h = old_simr_h;
302      m8260.simr_l = old_simr_l;
303
304    }
305#ifdef DISPATCH_HANDLER_STAT
306    ++ loopCounter;
307#endif
308  }
309  return 0;
310}
311
312/*
313 * Initialize CPM interrupt management
314 */
315void
316BSP_CPM_irq_init(void)
317{
318   m8260.simr_l = 0;
319   m8260.simr_h = 0;
320   m8260.sipnr_l = 0xffffffff;
321   m8260.sipnr_h = 0xffffffff;
322   m8260.sicr = 0;
323
324  /*
325   * Initialize the interrupt priorities.
326   */
327   m8260.siprr   = 0x05309770;  /* reset value */
328   m8260.scprr_h = 0x05309770;  /* reset value */
329   m8260.scprr_l = 0x05309770;  /* reset value */
330
331}
332
333rtems_status_code bsp_interrupt_vector_enable( rtems_vector_number irqnum)
334{
335  if (is_cpm_irq(irqnum)) {
336    /*
337     * Enable interrupt at PIC level
338     */
339    BSP_irq_enable_at_cpm (irqnum);
340  }
341
342  return RTEMS_SUCCESSFUL;
343}
344
345rtems_status_code bsp_interrupt_vector_disable( rtems_vector_number irqnum)
346{
347  if (is_cpm_irq(irqnum)) {
348    /*
349     * disable interrupt at PIC level
350     */
351    BSP_irq_disable_at_cpm (irqnum);
352  }
353
354  return RTEMS_SUCCESSFUL;
355}
356
357rtems_status_code bsp_interrupt_facility_initialize()
358{
359  /* Install exception handler */
360  if (ppc_exc_set_handler( ASM_EXT_VECTOR, C_dispatch_irq_handler)) {
361    return RTEMS_IO_ERROR;
362  }
363  if (ppc_exc_set_handler( ASM_DEC_VECTOR, C_dispatch_irq_handler)) {
364    return RTEMS_IO_ERROR;
365  }
366
367  /* Fill in priority masks */
368  compute_SIU_IvectMask_from_prio();
369
370  /* Initialize the interrupt controller */
371  BSP_CPM_irq_init();
372
373  return RTEMS_SUCCESSFUL;
374}
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