[5edbffe] | 1 | /* |
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| 2 | * |
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| 3 | * This file contains the implementation of the function described in irq.h |
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| 4 | * |
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| 5 | * Copyright (C) 1998, 1999 valette@crf.canon.fr |
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| 6 | * |
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| 7 | * Modified for mpc8260 Andy Dachs <a.dachs@sstl.co.uk> |
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| 8 | * Surrey Satellite Technology Limited, 2000 |
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| 9 | * Nested exception handlers not working yet. |
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| 10 | * |
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| 11 | * The license and distribution terms for this file may be |
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| 12 | * found in found in the file LICENSE in this distribution or at |
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| 13 | * http://www.OARcorp.com/rtems/license.html. |
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| 14 | * |
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| 15 | * $Id$ |
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| 16 | */ |
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| 17 | |
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[1628414] | 18 | #include <rtems/system.h> |
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[5edbffe] | 19 | #include <bsp.h> |
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| 20 | #include <bsp/irq.h> |
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| 21 | #include <rtems/score/thread.h> |
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| 22 | #include <rtems/score/apiext.h> |
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| 23 | #include <libcpu/raw_exception.h> |
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| 24 | #include <bsp/vectors.h> |
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| 25 | /*#include <bsp/8xx_immap.h>*/ |
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| 26 | #include <mpc8260.h> |
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| 27 | /*#include <bsp/commproc.h>*/ |
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| 28 | |
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| 29 | /* |
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| 30 | * default handler connected on each irq after bsp initialization |
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| 31 | */ |
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| 32 | static rtems_irq_connect_data default_rtems_entry; |
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| 33 | |
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| 34 | /* |
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| 35 | * location used to store initial tables used for interrupt |
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| 36 | * management. |
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| 37 | */ |
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| 38 | static rtems_irq_global_settings* internal_config; |
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| 39 | static rtems_irq_connect_data* rtems_hdl_tbl; |
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| 40 | |
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| 41 | |
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| 42 | /* |
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| 43 | * Check if symbolic IRQ name is an CPM IRQ |
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| 44 | */ |
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| 45 | static inline int is_cpm_irq(const rtems_irq_symbolic_name irqLine) |
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| 46 | { |
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| 47 | return (((int) irqLine <= BSP_CPM_IRQ_MAX_OFFSET) & |
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| 48 | ((int) irqLine >= BSP_CPM_IRQ_LOWEST_OFFSET) |
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| 49 | ); |
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| 50 | } |
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| 51 | |
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| 52 | /* |
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| 53 | * Check if symbolic IRQ name is a Processor IRQ |
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| 54 | */ |
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| 55 | static inline int is_processor_irq(const rtems_irq_symbolic_name irqLine) |
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| 56 | { |
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| 57 | return (((int) irqLine <= BSP_PROCESSOR_IRQ_MAX_OFFSET) & |
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| 58 | ((int) irqLine >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) |
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| 59 | ); |
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| 60 | } |
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| 61 | |
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| 62 | |
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| 63 | /* |
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| 64 | * bit in the SIU mask registers (PPC bit numbering) that should |
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| 65 | * be set to enable the relevant interrupt |
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| 66 | * |
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| 67 | */ |
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| 68 | const static unsigned int SIU_MaskBit[BSP_CPM_IRQ_NUMBER] = |
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| 69 | { |
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| 70 | 63, 48, 49, 50, /* err, i2c, spi, rtt */ |
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| 71 | 51, 52, 53, 54, /* smc1, smc2, idma1, idma2 */ |
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| 72 | 55, 56, 57, 63, /* idma3, idma4, sdma, - */ |
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| 73 | 59, 60, 61, 62, /* tmr1, tmr2, tmr3, tmr4 */ |
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| 74 | 29, 30, 63, 17, /* pit, tmcnt, -, irq1 */ |
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| 75 | 18, 19, 20, 21, /* irq2, irq3, irq4, irq5 */ |
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| 76 | 22, 23, 63, 63, /* irq6, irq7, -, - */ |
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| 77 | 63, 63, 63, 63, /* -, -, -, - */ |
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| 78 | 32, 33, 34, 35, /* fcc1, fcc2, fcc3, - */ |
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| 79 | 36, 37, 38, 39, /* mcc1, mcc2, -, - */ |
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| 80 | 40, 41, 42, 43, /* scc1, scc2, scc3, scc4 */ |
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| 81 | 44, 45, 46, 47, /* -, -, -, - */ |
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| 82 | 0, 1, 2, 3, /* pc0, pc1, pc2, pc3 */ |
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| 83 | 4, 5, 6, 7, /* pc4, pc5, pc6, pc7 */ |
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| 84 | 8, 9, 10, 11, /* pc8, pc9, pc10, pc11 */ |
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| 85 | 12, 13, 14, 15 /* pc12, pc13, pc14, pc15 */ |
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| 86 | }; |
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| 87 | |
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| 88 | /* |
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| 89 | * ------------------------ RTEMS Irq helper functions ---------------- |
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| 90 | */ |
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| 91 | |
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| 92 | /* |
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| 93 | * Caution : this function assumes the variable "internal_config" |
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| 94 | * is already set and that the tables it contains are still valid |
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| 95 | * and accessible. |
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| 96 | */ |
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| 97 | static void compute_SIU_IvectMask_from_prio () |
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| 98 | { |
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| 99 | /* |
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| 100 | * In theory this is feasible. No time to code it yet. See i386/shared/irq.c |
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| 101 | * for an example based on 8259 controller mask. The actual masks defined |
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| 102 | * correspond to the priorities defined for the SIU in irq_init.c. |
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| 103 | */ |
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| 104 | } |
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| 105 | |
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| 106 | /* |
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| 107 | * This function check that the value given for the irq line |
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| 108 | * is valid. |
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| 109 | */ |
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| 110 | |
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| 111 | static int isValidInterrupt(int irq) |
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| 112 | { |
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| 113 | if ( (irq < BSP_LOWEST_OFFSET) || (irq > BSP_MAX_OFFSET) ) |
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| 114 | return 0; |
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| 115 | return 1; |
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| 116 | } |
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| 117 | |
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| 118 | int BSP_irq_enable_at_cpm(const rtems_irq_symbolic_name irqLine) |
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| 119 | { |
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| 120 | int cpm_irq_index; |
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| 121 | |
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| 122 | if (!is_cpm_irq(irqLine)) |
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| 123 | return 1; |
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| 124 | |
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| 125 | cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET); |
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| 126 | |
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| 127 | |
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| 128 | if( SIU_MaskBit[cpm_irq_index] < 32 ) |
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| 129 | m8260.simr_h |= (0x80000000 >> SIU_MaskBit[cpm_irq_index]); |
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| 130 | else |
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| 131 | m8260.simr_l |= (0x80000000 >> (SIU_MaskBit[cpm_irq_index]-32)); |
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| 132 | |
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| 133 | return 0; |
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| 134 | } |
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| 135 | |
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| 136 | int BSP_irq_disable_at_cpm(const rtems_irq_symbolic_name irqLine) |
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| 137 | { |
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| 138 | int cpm_irq_index; |
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| 139 | |
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| 140 | if (!is_cpm_irq(irqLine)) |
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| 141 | return 1; |
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| 142 | |
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| 143 | cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET); |
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| 144 | |
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| 145 | if( SIU_MaskBit[cpm_irq_index] < 32 ) |
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| 146 | m8260.simr_h &= ~(0x80000000 >> SIU_MaskBit[cpm_irq_index]); |
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| 147 | else |
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| 148 | m8260.simr_l &= ~(0x80000000 >> (SIU_MaskBit[cpm_irq_index]-32)); |
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| 149 | |
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| 150 | |
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| 151 | return 0; |
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| 152 | } |
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| 153 | |
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| 154 | int BSP_irq_enabled_at_cpm(const rtems_irq_symbolic_name irqLine) |
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| 155 | { |
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| 156 | int cpm_irq_index; |
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| 157 | |
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| 158 | if (!is_cpm_irq(irqLine)) |
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| 159 | return 0; |
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| 160 | |
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| 161 | cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET); |
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| 162 | |
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| 163 | if( SIU_MaskBit[cpm_irq_index] < 32 ) |
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| 164 | return m8260.simr_h & (0x80000000 >> SIU_MaskBit[cpm_irq_index]); |
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| 165 | else |
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| 166 | return m8260.simr_l & (0x80000000 >> (SIU_MaskBit[cpm_irq_index]-32)); |
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| 167 | } |
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| 168 | |
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| 169 | |
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| 170 | /* |
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| 171 | * ------------------------ RTEMS Single Irq Handler Mngt Routines ---------------- |
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| 172 | */ |
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| 173 | |
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| 174 | int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) |
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| 175 | { |
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| 176 | unsigned int level; |
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| 177 | |
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| 178 | if (!isValidInterrupt(irq->name)) { |
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| 179 | printk( "not a valid intr\n" ) ; |
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| 180 | return 0; |
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| 181 | } |
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| 182 | /* |
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| 183 | * Check if default handler is actually connected. If not issue an error. |
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| 184 | * You must first get the current handler via i386_get_current_idt_entry |
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| 185 | * and then disconnect it using i386_delete_idt_entry. |
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| 186 | * RATIONALE : to always have the same transition by forcing the user |
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| 187 | * to get the previous handler before accepting to disconnect. |
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| 188 | */ |
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| 189 | if (rtems_hdl_tbl[irq->name].hdl != default_rtems_entry.hdl) { |
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| 190 | printk( "Default handler not there\n" ); |
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| 191 | return 0; |
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| 192 | } |
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| 193 | |
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| 194 | _CPU_ISR_Disable(level); |
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| 195 | |
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| 196 | /* |
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| 197 | * store the data provided by user |
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| 198 | */ |
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| 199 | rtems_hdl_tbl[irq->name] = *irq; |
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| 200 | |
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| 201 | if (is_cpm_irq(irq->name)) { |
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| 202 | /* |
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| 203 | * Enable interrupt at PIC level |
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| 204 | */ |
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| 205 | BSP_irq_enable_at_cpm (irq->name); |
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| 206 | } |
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| 207 | |
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| 208 | |
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| 209 | if (is_processor_irq(irq->name)) { |
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| 210 | /* |
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| 211 | * Should Enable exception at processor level but not needed. Will restore |
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| 212 | * EE flags at the end of the routine anyway. |
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| 213 | */ |
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| 214 | } |
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| 215 | /* |
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| 216 | * Enable interrupt on device |
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| 217 | */ |
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| 218 | irq->on(irq); |
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| 219 | |
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| 220 | _CPU_ISR_Enable(level); |
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| 221 | |
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| 222 | /* |
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| 223 | printk( "Enabled\n" ); |
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| 224 | */ |
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| 225 | return 1; |
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| 226 | } |
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| 227 | |
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| 228 | |
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| 229 | int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* irq) |
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| 230 | { |
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| 231 | if (!isValidInterrupt(irq->name)) { |
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| 232 | return 0; |
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| 233 | } |
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| 234 | *irq = rtems_hdl_tbl[irq->name]; |
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| 235 | return 1; |
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| 236 | } |
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| 237 | |
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| 238 | int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) |
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| 239 | { |
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| 240 | unsigned int level; |
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| 241 | |
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| 242 | if (!isValidInterrupt(irq->name)) { |
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| 243 | return 0; |
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| 244 | } |
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| 245 | /* |
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| 246 | * Check if default handler is actually connected. If not issue an error. |
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| 247 | * You must first get the current handler via i386_get_current_idt_entry |
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| 248 | * and then disconnect it using i386_delete_idt_entry. |
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| 249 | * RATIONALE : to always have the same transition by forcing the user |
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| 250 | * to get the previous handler before accepting to disconnect. |
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| 251 | */ |
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| 252 | if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) { |
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| 253 | return 0; |
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| 254 | } |
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| 255 | _CPU_ISR_Disable(level); |
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| 256 | |
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| 257 | if (is_cpm_irq(irq->name)) { |
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| 258 | /* |
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| 259 | * disable interrupt at PIC level |
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| 260 | */ |
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| 261 | BSP_irq_disable_at_cpm (irq->name); |
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| 262 | } |
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| 263 | |
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| 264 | if (is_processor_irq(irq->name)) { |
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| 265 | /* |
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| 266 | * disable exception at processor level |
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| 267 | */ |
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| 268 | } |
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| 269 | |
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| 270 | /* |
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| 271 | * Disable interrupt on device |
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| 272 | */ |
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| 273 | irq->off(irq); |
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| 274 | |
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| 275 | /* |
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| 276 | * restore the default irq value |
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| 277 | */ |
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| 278 | rtems_hdl_tbl[irq->name] = default_rtems_entry; |
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| 279 | |
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| 280 | _CPU_ISR_Enable(level); |
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| 281 | |
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| 282 | return 1; |
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| 283 | } |
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| 284 | |
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| 285 | /* |
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| 286 | * ------------------------ RTEMS Global Irq Handler Mngt Routines ---------------- |
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| 287 | */ |
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| 288 | |
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| 289 | int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config) |
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| 290 | { |
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| 291 | int i; |
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| 292 | unsigned int level; |
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| 293 | /* |
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| 294 | * Store various code accelerators |
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| 295 | */ |
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| 296 | internal_config = config; |
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| 297 | default_rtems_entry = config->defaultEntry; |
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| 298 | rtems_hdl_tbl = config->irqHdlTbl; |
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| 299 | |
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| 300 | _CPU_ISR_Disable(level); |
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| 301 | /* |
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| 302 | * start with CPM IRQ |
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| 303 | */ |
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| 304 | for (i=BSP_CPM_IRQ_LOWEST_OFFSET; i < BSP_CPM_IRQ_LOWEST_OFFSET + BSP_CPM_IRQ_NUMBER ; i++) { |
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| 305 | if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { |
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| 306 | BSP_irq_enable_at_cpm (i); |
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| 307 | rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); |
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| 308 | } |
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| 309 | else { |
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| 310 | rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); |
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| 311 | BSP_irq_disable_at_cpm (i); |
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| 312 | } |
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| 313 | } |
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| 314 | |
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| 315 | /* |
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| 316 | * finish with Processor exceptions handled like IRQ |
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| 317 | */ |
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| 318 | for (i=BSP_PROCESSOR_IRQ_LOWEST_OFFSET; i < BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER; i++) { |
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| 319 | if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { |
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| 320 | rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); |
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| 321 | } |
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| 322 | else { |
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| 323 | rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); |
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| 324 | } |
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| 325 | } |
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| 326 | _CPU_ISR_Enable(level); |
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| 327 | return 1; |
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| 328 | } |
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| 329 | |
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| 330 | int BSP_rtems_irq_mngt_get(rtems_irq_global_settings** config) |
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| 331 | { |
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| 332 | *config = internal_config; |
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| 333 | return 0; |
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| 334 | } |
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| 335 | |
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| 336 | #ifdef DISPATCH_HANDLER_STAT |
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| 337 | volatile unsigned int maxLoop = 0; |
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| 338 | #endif |
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| 339 | |
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| 340 | /* |
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| 341 | * High level IRQ handler called from shared_raw_irq_code_entry |
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| 342 | */ |
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| 343 | void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) |
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| 344 | { |
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| 345 | register unsigned int irq; |
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| 346 | #if 0 |
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| 347 | register unsigned oldMask; /* old siu pic masks */ |
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| 348 | #endif |
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| 349 | register unsigned msr; |
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| 350 | register unsigned new_msr; |
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| 351 | #ifdef DISPATCH_HANDLER_STAT |
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| 352 | unsigned loopCounter; |
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| 353 | #endif |
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| 354 | |
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| 355 | |
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| 356 | |
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| 357 | /* |
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| 358 | * Handle decrementer interrupt |
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| 359 | */ |
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| 360 | if (excNum == ASM_DEC_VECTOR) { |
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| 361 | |
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| 362 | /* |
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| 363 | _BSP_GPLED1_on(); |
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| 364 | */ |
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| 365 | _CPU_MSR_GET(msr); |
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| 366 | new_msr = msr | MSR_EE; |
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| 367 | _CPU_MSR_SET(new_msr); |
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| 368 | |
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| 369 | rtems_hdl_tbl[BSP_DECREMENTER].hdl(); |
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| 370 | |
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| 371 | _CPU_MSR_SET(msr); |
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| 372 | |
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| 373 | /* |
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| 374 | _BSP_GPLED1_off(); |
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| 375 | */ |
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| 376 | return; |
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| 377 | } |
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| 378 | |
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| 379 | /* |
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| 380 | * Handle external interrupt generated by SIU on PPC core |
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| 381 | */ |
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| 382 | #ifdef DISPATCH_HANDLER_STAT |
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| 383 | loopCounter = 0; |
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| 384 | #endif |
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| 385 | while (1) { |
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| 386 | |
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| 387 | if( ((m8260.sipnr_h & m8260.simr_h) | (m8260.sipnr_l & m8260.simr_l)) == 0 ) { |
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| 388 | #ifdef DISPATCH_HANDLER_STAT |
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| 389 | if (loopCounter > maxLoop) maxLoop = loopCounter; |
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| 390 | #endif |
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| 391 | break; |
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| 392 | } |
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| 393 | |
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| 394 | irq = (m8260.sivec >> 26) + BSP_CPM_IRQ_LOWEST_OFFSET; |
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| 395 | |
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| 396 | /* |
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| 397 | printk( "dispatching %d\n", irq ); |
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| 398 | */ |
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| 399 | |
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| 400 | /* Clear pending register */ |
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| 401 | if( irq <= BSP_CPM_IRQ_MAX_OFFSET ) { |
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| 402 | if( SIU_MaskBit[irq] < 32 ) |
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| 403 | m8260.sipnr_h = (0x80000000 >> SIU_MaskBit[irq]); |
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| 404 | else |
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| 405 | m8260.sipnr_l = (0x80000000 >> (SIU_MaskBit[irq]-32)); |
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| 406 | } |
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| 407 | |
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| 408 | /* |
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| 409 | _CPU_MSR_GET(msr); |
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| 410 | new_msr = msr | MSR_EE; |
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| 411 | _CPU_MSR_SET(new_msr); |
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| 412 | */ |
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| 413 | rtems_hdl_tbl[irq].hdl(); |
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| 414 | /* |
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| 415 | _CPU_MSR_SET(msr); |
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| 416 | */ |
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| 417 | |
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| 418 | |
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| 419 | |
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| 420 | #if 0 |
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| 421 | ppc_cached_irq_mask |= (oldMask & ~(SIU_IvectMask[irq])); |
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| 422 | ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = ppc_cached_irq_mask; |
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| 423 | #endif |
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| 424 | #ifdef DISPATCH_HANDLER_STAT |
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| 425 | ++ loopCounter; |
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| 426 | #endif |
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| 427 | } |
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| 428 | |
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| 429 | |
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| 430 | |
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| 431 | |
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| 432 | } |
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| 433 | |
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| 434 | |
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| 435 | |
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| 436 | void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx) |
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| 437 | { |
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| 438 | /* |
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| 439 | * Process pending signals that have not already been |
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| 440 | * processed by _Thread_Displatch. This happens quite |
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| 441 | * unfrequently : the ISR must have posted an action |
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| 442 | * to the current running thread. |
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| 443 | */ |
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| 444 | if ( _Thread_Do_post_task_switch_extension || |
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| 445 | _Thread_Executing->do_post_task_switch_extension ) { |
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| 446 | _Thread_Executing->do_post_task_switch_extension = FALSE; |
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| 447 | _API_extensions_Run_postswitch(); |
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| 448 | } |
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| 449 | /* |
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| 450 | * I plan to process other thread related events here. |
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| 451 | * This will include DEBUG session requested from keyboard... |
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| 452 | */ |
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| 453 | } |
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