source: rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start.S @ d374492

4.104.11
Last change on this file since d374492 was 976b159, checked in by Chris Johns <chrisj@…>, on Apr 28, 2009 at 6:33:16 AM

2009-04-28 Chris Johns <chrisj@…>

  • startup/start.S: Update for boot_card command line change.
  • Property mode set to 100644
File size: 4.3 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup mpc55xx_asm
5 *
6 * @brief Boot and system start code.
7 */
8
9/*
10 * Copyright (c) 2008
11 * Embedded Brains GmbH
12 * Obere Lagerstr. 30
13 * D-82178 Puchheim
14 * Germany
15 * rtems@embedded-brains.de
16 *
17 * The license and distribution terms for this file may be found in the file
18 * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
19 */
20
21#warning Call to boot_card has changed and needs checking.
22#warning The call is "void boot_card(const char* cmdline);"
23#warning You need to pass a NULL.
24#warning Please check and remove these warnings.
25       
26/**
27 * @defgroup mpc55xx_asm Assembler files
28 *
29 * @ingroup mpc55xx
30 */
31   
32#include <libcpu/powerpc-utility.h>
33#include <mpc55xx/reg-defs.h>
34
35.section ".entry", "ax" 
36PUBLIC_VAR (start)
37start:
38/*
39 * BAM
40 */
41
42        /* BAM: RCHW */
43        .int 0x5a0000
44
45        /* BAM: Address of start instruction */
46        .int 0x8
47
48/*
49 * Enable time base
50 */
51
52        li r0, 0
53        mtspr TBWU, r0
54        mtspr TBWL, r0
55        mfspr r2, HID0
56        ori r2, r2, 0x4000
57        mtspr HID0, r2
58
59/*
60 * System clock
61 */
62
63        bl SYM (mpc55xx_fmpll_reset_config)
64
65/*
66 * Enable branch prediction
67 */
68
69        LWI r2, BUCSR_BBFI | BUCSR_BPEN
70        mtspr BUCSR, r2
71
72/*
73 * Basics
74 */
75
76        /* Set stack start to end of ram */
77        LA r1, bsp_ram_end
78        addi r1, r1, -8
79
80        /* Enable SPE */
81        mfmsr r2
82        oris r2, r2, 0x200
83        mtmsr r2
84
85        /* Config internal flash */
86        bl SYM (mpc55xx_flash_config)
87
88        /* FIXME: Config cache */
89        bl config_cache
90
91/*
92 * TODO, FIXME: Enable cache in the MMU for the SRAM
93 */
94
95.equ MAS0, 624
96.equ MAS1, 625
97.equ MAS2, 626
98.equ MAS3, 627
99
100        LWI r3, 0x10030000
101        mtspr MAS0, r3
102        tlbre
103        LWI r4, ~0x00000008
104        mfspr r3, MAS2
105        and r3, r3, r4
106        mtspr MAS2, r3
107        tlbwe
108
109/*
110 * TODO, FIXME: Set MMU for the external SRAM
111 */
112
113        LWI r3, 0x10020000
114        mtspr MAS0, r3
115        tlbre
116        LWI r4, 0xfff
117        mfspr r3, MAS3
118        and r3, r3, r4
119        LWI r4, 0x20000000
120        or r3, r3, r4
121        mtspr MAS3, r3
122        tlbwe
123
124/*
125 * Zero RAM
126 */
127
128        /* Addresses */
129        LA r3, bsp_ram_start
130        LA r4, bsp_ram_end
131
132        /* Assert: Proper alignment of destination start */
133        andi. r6, r3, 0x37
134        bne twiddle
135
136        /* Assert: Proper alignment of destination end */
137        andi. r6, r4, 0x37
138        bne twiddle
139
140        /* Data size = destination end - destination start */
141        subf r4, r3, r4
142
143        /* Save time */
144        mftb r24
145
146        /* Zero */
147        bl SYM (mpc55xx_zero_32)
148
149        /* Save time and get time delta */
150        mftb r25
151        subf r24, r24, r25
152
153/*
154 * Copy data
155 */
156
157        /* Addresses */
158        LA r3, bsp_section_text_end
159        LA r4, bsp_section_data_start
160        LA r5, bsp_section_data_end
161
162        /* Assert: Proper alignment of source start */
163        andi. r6, r3, 0x7
164        bne twiddle
165
166        /* Assert: Proper alignment of destination start */
167        andi. r6, r4, 0x7
168        bne twiddle
169
170        /* Assert: Proper alignment of destination end */
171        andi. r6, r5, 0x7
172        bne twiddle
173
174        /* Data size = destination end - destination start */
175        subf r5, r4, r5
176
177        /* Copy */
178        bl SYM (mpc55xx_copy_8)
179
180        /* Save time and get time delta */
181        mftb r26
182        subf r25, r25, r26
183
184/*
185 * Prepare high level initialization
186 */
187        LA r3, bsp_ram_start
188        LA r4, ppc_exc_vector_base
189        stw r3, 0(r4)
190
191        /* Set global BSP clock speed variable */
192        bl SYM (mpc55xx_get_system_clock)
193        LA r4, bsp_clock_speed
194        stw r3, 0(r4)
195
196        /* Create NULL */
197        li r0, 0
198
199        /* Return address */
200        stw r0, 4(r1)
201
202        /* Back chain */
203        stw r0, 0(r1)
204
205        /* Read-only small data */
206        LA r2, _SDA2_BASE_
207
208        /* Read-write small data */
209        LA r13, _SDA_BASE_
210
211/*
212 * Start RTEMS
213 */
214
215        /* Clear command line */
216        xor r3, r3, r3
217       
218        /* Start RTEMS */
219        bl SYM (boot_card)
220
221        /* Spin around */
222        b twiddle
223
224.equ L1CSR0, 1010
225.equ L1CSR0_CINV, 0x2
226.equ L1CSR0_CABT, 0x4
227/* FIXME: CORG??? .equ L1CSR0_SETTINGS, 0x00180011 */
228.equ L1CSR0_SETTINGS, 0x00100001
229
230/*
231 * Configure cache
232 */
233config_cache:
234        /* Start cache invalidation */
235        LWI r5, L1CSR0_CINV
236        mtspr L1CSR0, r5
237
238        /* Bit masks to test and clear invalidation abortion (CABT) */
239        LWI r6, L1CSR0_CABT
240        not r7, r6
241
242        /* Wait for cache invalidation to complete */
243check_cache_invalidation:
244        mfspr r9, L1CSR0
245
246        /* Check if the invalidate was aborted */
247        and. r10, r9, r6
248        beq no_chache_invalidation_abort
249
250        /* Clear CABT bit */
251        and r10, r9, r7
252        mtspr L1CSR0, r10
253
254        /* Retry invalidation */
255        b config_cache
256
257no_chache_invalidation_abort:
258        /* Check CINV bit */
259        and. r10, r5, r9
260
261        /* Wait? */
262        bne check_cache_invalidation
263 
264        /* Enable cache */
265        LWI r6, L1CSR0_SETTINGS
266        mfspr r5, L1CSR0
267        or r5, r5, r6
268        msync
269        isync
270        mtspr L1CSR0, r5
271
272        /* Return */
273        blr   
274
275twiddle:                               
276        b       twiddle
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