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4.115

Last change on this file since c6d35ad4 was c6d35ad4, checked in by Sebastian Huber <sebastian.huber@…>, on 11/21/12 at 08:46:58
bsp/mpc55xx: Errata e4396 for e200z7
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File size: 5.6 KB

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1	/**
2	* @file
3	*
4	* @ingroup mpc55xx_asm
5	*
6	* @brief Boot and system start code.
7	*/
8
9	/*
10	* Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved.
11	*
12	* embedded brains GmbH
13	* Obere Lagerstr. 30
14	* 82178 Puchheim
15	* Germany
16	* <rtems@embedded-brains.de>
17	*
18	* The license and distribution terms for this file may be
19	* found in the file LICENSE in this distribution or at
20	* http://www.rtems.com/license/LICENSE.
21	*/
22
23	#include <bspopts.h>
24	#include <bsp/linker-symbols.h>
25	#include <libcpu/powerpc-utility.h>
26
27	#if MPC55XX_CHIP_FAMILY != 551
28	#define HAS_SPE
29	#endif
30
31	#if MPC55XX_CHIP_FAMILY == 564
32	#define INIT_REGISTERS_FOR_LSM
33	#endif
34
35	#ifdef HAS_SPE
36	#define ZERO_GPR(reg) evxor reg, reg, reg
37	#else
38	#define ZERO_GPR(reg) xor reg, reg, reg
39	#endif
40
41	.extern __eabi
42	.extern boot_card
43	.extern bsp_ram_start
44	.extern mpc55xx_start_config_mmu_early
45	.extern mpc55xx_start_config_mmu_early_count
46	.extern mpc55xx_start_early
47
48	.globl _start
49	.globl mpc55xx_start_load_section
50	.globl mpc55xx_start_mmu_apply_config
51
52	#ifdef MPC55XX_BOOTFLAGS
53	.globl mpc55xx_bootflag_0
54	.globl mpc55xx_bootflag_1
55	#endif
56
57	.section ".bsp_start_text", "ax"
58
59	/* BAM: RCHW */
60	.int 0x005a0000
61
62	/* BAM: Address of start instruction */
63	.int _start
64
65	#ifdef MPC55XX_BOOTFLAGS
66	/*
67	* We skip over the next two boot flag words to the next 64-bit
68	* aligned start address. It is 64-bit aligned to play well with
69	* FLASH programming. These boot flags can be set by debuggers
70	* and emulators to customize boot. Currently bit0 of
71	* bootflag_0 means to "skip setting up the MMU", allowing
72	* external MMU setup in a debugger before branching to 0x10.
73	* This can be used e.g., to map FLASH into RAM.
74	*/
75	mpc55xx_bootflag_0:
76	.int 0xffffffff
77	mpc55xx_bootflag_1:
78	.int 0xffffffff
79	#endif
80
81	_start:
82
83	#ifdef MPC55XX_NEEDS_LOW_LEVEL_INIT
84
85	/* Enable SPE */
86	#ifdef HAS_SPE
87	mfmsr r3
88	oris r3, r3, MSR_SPE >> 16
89	mtmsr r3
90	isync
91	#endif
92
93	/*
94	* Initialization of core registers according to "e200z4 Power
95	* Architecture Core Reference Manual" section 2.6 "Reset Settings"
96	* table 2-16 "Reset Settings of e200 Resources". This is necessary
97	* for lock step mode (LSM).
98	*/
99	ZERO_GPR(r0)
100	#ifdef INIT_REGISTERS_FOR_LSM
101	ZERO_GPR(r1)
102	ZERO_GPR(r2)
103	ZERO_GPR(r4)
104	ZERO_GPR(r5)
105	ZERO_GPR(r6)
106	ZERO_GPR(r7)
107	ZERO_GPR(r8)
108	ZERO_GPR(r9)
109	ZERO_GPR(r10)
110	ZERO_GPR(r11)
111	ZERO_GPR(r12)
112	ZERO_GPR(r13)
113	ZERO_GPR(r14)
114	ZERO_GPR(r15)
115	ZERO_GPR(r16)
116	ZERO_GPR(r17)
117	ZERO_GPR(r18)
118	ZERO_GPR(r19)
119	ZERO_GPR(r20)
120	ZERO_GPR(r21)
121	ZERO_GPR(r22)
122	ZERO_GPR(r23)
123	ZERO_GPR(r24)
124	ZERO_GPR(r25)
125	ZERO_GPR(r26)
126	ZERO_GPR(r27)
127	ZERO_GPR(r28)
128	ZERO_GPR(r29)
129	ZERO_GPR(r30)
130	ZERO_GPR(r31)
131	mtcrf 0xff, r0
132	mtcsrr0 r0
133	mtcsrr1 r0
134	mtctr r0
135	mtspr FSL_EIS_DBCNT, r0
136	mtspr DEAR_BOOKE, r0
137	mtdec r0
138	mtspr BOOKE_DECAR, r0
139	mtspr FSL_EIS_DSRR0, r0
140	mtspr FSL_EIS_DSRR1, r0
141	mtspr BOOKE_DVC1, r0
142	mtspr BOOKE_DVC2, r0
143	mtspr BOOKE_IVPR, r0
144	mtlr r0
145	mtspr FSL_EIS_MCAR, r0
146	mtmcsrr0 r0
147	mtmcsrr1 r0
148	mtspr SPRG0, r0
149	mtspr SPRG1, r0
150	mtspr SPRG2, r0
151	mtspr SPRG3, r0
152	mtspr SPRG4, r0
153	mtspr SPRG5, r0
154	mtspr SPRG6, r0
155	mtspr SPRG7, r0
156	mtspr FSL_EIS_SPRG8, r0
157	mtspr FSL_EIS_SPRG9, r0
158	mtsrr0 r0
159	mtsrr1 r0
160	mtspr USPRG0, r0
161	#ifdef HAS_SPE
162	evmra r0, r0
163	#endif
164	#endif /* INIT_REGISTERS_FOR_LSM */
165	mtspr TBWL, r0
166	mtspr TBWU, r0
167
168	/* Enable time base */
169	mfspr r3, HID0
170	ori r3, r3, 0x4000
171	mtspr HID0, r3
172
173	/*
174	* Enable branch prediction.
175	*
176	* Errata e4396: e200z7: Erroneous Address Fetch
177	*
178	* The propose workaround does not work.
179	*/
180	#if MPC55XX_CHIP_FAMILY != 567
181	LWI r3, FSL_EIS_BUCSR_BBFI \| FSL_EIS_BUCSR_BALLOC_ALL \| FSL_EIS_BUCSR_BPRED_NOT_TAKEN \| FSL_EIS_BUCSR_BPEN
182	mtspr FSL_EIS_BUCSR, r3
183	#endif
184
185	#endif /* MPC55XX_NEEDS_LOW_LEVEL_INIT */
186
187	/* MMU early initialization */
188	LA r3, mpc55xx_start_config_mmu_early
189	LW r4, mpc55xx_start_config_mmu_early_count
190	bl mpc55xx_start_mmu_apply_config
191
192	#ifdef MPC55XX_NEEDS_LOW_LEVEL_INIT
193
194	/* Initialize intermediate stack (ECC) */
195
196	LA r3, bsp_ram_start
197	addi r4, r3, MPC55XX_EARLY_STACK_SIZE
198
199	zero_intermediate_stack_loop:
200
201	#ifdef HAS_SPE
202	evstdd r0, 0(r3)
203	evstdd r0, 8(r3)
204	evstdd r0, 16(r3)
205	evstdd r0, 24(r3)
206	#else
207	stw r0, 0(r3)
208	stw r0, 4(r3)
209	stw r0, 8(r3)
210	stw r0, 12(r3)
211	stw r0, 16(r3)
212	stw r0, 20(r3)
213	stw r0, 24(r3)
214	stw r0, 28(r3)
215	#endif
216	addi r3, r3, 32
217	cmpw cr7, r3, r4
218	bne cr7, zero_intermediate_stack_loop
219	subi r1, r3, 16
220
221	#endif /* MPC55XX_NEEDS_LOW_LEVEL_INIT */
222
223	/* Next steps in C */
224	bl mpc55xx_start_early
225
226	/* Initialize start stack */
227	LA r1, start_stack_end
228	subi r1, r1, 16
229	li r0, 0
230	stw r0, 0(r1)
231
232	/*
233	* Load sections. This must be performed after the stack switch
234	* because it may overwrite the initial stack.
235	*/
236	LA r3, bsp_section_fast_text_begin
237	LA r4, bsp_section_fast_text_load_begin
238	LA r5, bsp_section_fast_text_size
239	bl mpc55xx_start_load_section
240	LA r3, bsp_section_fast_data_begin
241	LA r4, bsp_section_fast_data_load_begin
242	LA r5, bsp_section_fast_data_size
243	bl mpc55xx_start_load_section
244	LA r3, bsp_section_data_begin
245	LA r4, bsp_section_data_load_begin
246	LA r5, bsp_section_data_size
247	bl mpc55xx_start_load_section
248
249	/* Set up EABI and SYSV environment */
250	bl __eabi
251
252	/* Clear command line */
253	li r3, 0
254
255	/* Start RTEMS */
256	bl boot_card
257
258	/* Spin around */
259	twiddle:
260
261	b twiddle
262
263	mpc55xx_start_mmu_apply_config:
264
265	cmpwi cr7, r4, r0
266	beqlr cr7
267	mtctr r4
268
269	mmu_init_loop:
270
271	lwz r4, 0(r3)
272	lwz r5, 4(r3)
273	lwz r6, 8(r3)
274	lwz r7, 12(r3)
275	mtspr FSL_EIS_MAS0, r4
276	mtspr FSL_EIS_MAS1, r5
277	mtspr FSL_EIS_MAS2, r6
278	mtspr FSL_EIS_MAS3, r7
279	tlbwe
280	addi r3, r3, 16
281	bdnz mmu_init_loop
282	blr
283
284	mpc55xx_start_load_section:
285	cmpw cr7, r3, r4
286	beqlr cr7
287	b memcpy
288
289	/* Start stack area */
290
291	.section ".bsp_rwextra", "aw", @nobits
292	.align 4
293	.space 4096
294
295	start_stack_end:

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