1 | /** |
---|
2 | * @file |
---|
3 | * |
---|
4 | * @ingroup mpc55xx_asm |
---|
5 | * |
---|
6 | * @brief Boot and system start code. |
---|
7 | */ |
---|
8 | |
---|
9 | /* |
---|
10 | * Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved. |
---|
11 | * |
---|
12 | * embedded brains GmbH |
---|
13 | * Obere Lagerstr. 30 |
---|
14 | * 82178 Puchheim |
---|
15 | * Germany |
---|
16 | * <rtems@embedded-brains.de> |
---|
17 | * |
---|
18 | * The license and distribution terms for this file may be |
---|
19 | * found in the file LICENSE in this distribution or at |
---|
20 | * http://www.rtems.com/license/LICENSE. |
---|
21 | */ |
---|
22 | |
---|
23 | #include <bspopts.h> |
---|
24 | #include <bsp/linker-symbols.h> |
---|
25 | #include <libcpu/powerpc-utility.h> |
---|
26 | |
---|
27 | #if MPC55XX_CHIP_FAMILY != 551 |
---|
28 | #define HAS_SPE |
---|
29 | #endif |
---|
30 | |
---|
31 | #if MPC55XX_CHIP_FAMILY == 564 |
---|
32 | #define INIT_REGISTERS_FOR_LSM |
---|
33 | #endif |
---|
34 | |
---|
35 | #ifdef HAS_SPE |
---|
36 | #define ZERO_GPR(reg) evxor reg, reg, reg |
---|
37 | #else |
---|
38 | #define ZERO_GPR(reg) xor reg, reg, reg |
---|
39 | #endif |
---|
40 | |
---|
41 | .extern __eabi |
---|
42 | .extern boot_card |
---|
43 | .extern bsp_ram_start |
---|
44 | .extern mpc55xx_start_config_mmu_early |
---|
45 | .extern mpc55xx_start_config_mmu_early_count |
---|
46 | .extern mpc55xx_start_early |
---|
47 | |
---|
48 | .globl _start |
---|
49 | .globl mpc55xx_start_load_section |
---|
50 | .globl mpc55xx_start_mmu_apply_config |
---|
51 | |
---|
52 | #ifdef MPC55XX_BOOTFLAGS |
---|
53 | .globl mpc55xx_bootflag_0 |
---|
54 | .globl mpc55xx_bootflag_1 |
---|
55 | #endif |
---|
56 | |
---|
57 | .section ".bsp_start_text", "ax" |
---|
58 | |
---|
59 | /* BAM: RCHW */ |
---|
60 | .int 0x005a0000 |
---|
61 | |
---|
62 | /* BAM: Address of start instruction */ |
---|
63 | .int _start |
---|
64 | |
---|
65 | #ifdef MPC55XX_BOOTFLAGS |
---|
66 | /* |
---|
67 | * We skip over the next two boot flag words to the next 64-bit |
---|
68 | * aligned start address. It is 64-bit aligned to play well with |
---|
69 | * FLASH programming. These boot flags can be set by debuggers |
---|
70 | * and emulators to customize boot. Currently bit0 of |
---|
71 | * bootflag_0 means to "skip setting up the MMU", allowing |
---|
72 | * external MMU setup in a debugger before branching to 0x10. |
---|
73 | * This can be used e.g., to map FLASH into RAM. |
---|
74 | */ |
---|
75 | mpc55xx_bootflag_0: |
---|
76 | .int 0xffffffff |
---|
77 | mpc55xx_bootflag_1: |
---|
78 | .int 0xffffffff |
---|
79 | #endif |
---|
80 | |
---|
81 | _start: |
---|
82 | |
---|
83 | #ifdef MPC55XX_NEEDS_LOW_LEVEL_INIT |
---|
84 | |
---|
85 | /* Enable SPE */ |
---|
86 | #ifdef HAS_SPE |
---|
87 | mfmsr r3 |
---|
88 | oris r3, r3, MSR_SPE >> 16 |
---|
89 | mtmsr r3 |
---|
90 | isync |
---|
91 | #endif |
---|
92 | |
---|
93 | /* |
---|
94 | * Initialization of core registers according to "e200z4 Power |
---|
95 | * Architecture Core Reference Manual" section 2.6 "Reset Settings" |
---|
96 | * table 2-16 "Reset Settings of e200 Resources". This is necessary |
---|
97 | * for lock step mode (LSM). |
---|
98 | */ |
---|
99 | ZERO_GPR(r0) |
---|
100 | #ifdef INIT_REGISTERS_FOR_LSM |
---|
101 | ZERO_GPR(r1) |
---|
102 | ZERO_GPR(r2) |
---|
103 | ZERO_GPR(r4) |
---|
104 | ZERO_GPR(r5) |
---|
105 | ZERO_GPR(r6) |
---|
106 | ZERO_GPR(r7) |
---|
107 | ZERO_GPR(r8) |
---|
108 | ZERO_GPR(r9) |
---|
109 | ZERO_GPR(r10) |
---|
110 | ZERO_GPR(r11) |
---|
111 | ZERO_GPR(r12) |
---|
112 | ZERO_GPR(r13) |
---|
113 | ZERO_GPR(r14) |
---|
114 | ZERO_GPR(r15) |
---|
115 | ZERO_GPR(r16) |
---|
116 | ZERO_GPR(r17) |
---|
117 | ZERO_GPR(r18) |
---|
118 | ZERO_GPR(r19) |
---|
119 | ZERO_GPR(r20) |
---|
120 | ZERO_GPR(r21) |
---|
121 | ZERO_GPR(r22) |
---|
122 | ZERO_GPR(r23) |
---|
123 | ZERO_GPR(r24) |
---|
124 | ZERO_GPR(r25) |
---|
125 | ZERO_GPR(r26) |
---|
126 | ZERO_GPR(r27) |
---|
127 | ZERO_GPR(r28) |
---|
128 | ZERO_GPR(r29) |
---|
129 | ZERO_GPR(r30) |
---|
130 | ZERO_GPR(r31) |
---|
131 | mtcrf 0xff, r0 |
---|
132 | mtcsrr0 r0 |
---|
133 | mtcsrr1 r0 |
---|
134 | mtctr r0 |
---|
135 | mtspr FSL_EIS_DBCNT, r0 |
---|
136 | mtspr DEAR_BOOKE, r0 |
---|
137 | mtdec r0 |
---|
138 | mtspr BOOKE_DECAR, r0 |
---|
139 | mtspr FSL_EIS_DSRR0, r0 |
---|
140 | mtspr FSL_EIS_DSRR1, r0 |
---|
141 | mtspr BOOKE_DVC1, r0 |
---|
142 | mtspr BOOKE_DVC2, r0 |
---|
143 | mtspr BOOKE_IVPR, r0 |
---|
144 | mtlr r0 |
---|
145 | mtspr FSL_EIS_MCAR, r0 |
---|
146 | mtmcsrr0 r0 |
---|
147 | mtmcsrr1 r0 |
---|
148 | mtspr SPRG0, r0 |
---|
149 | mtspr SPRG1, r0 |
---|
150 | mtspr SPRG2, r0 |
---|
151 | mtspr SPRG3, r0 |
---|
152 | mtspr SPRG4, r0 |
---|
153 | mtspr SPRG5, r0 |
---|
154 | mtspr SPRG6, r0 |
---|
155 | mtspr SPRG7, r0 |
---|
156 | mtspr FSL_EIS_SPRG8, r0 |
---|
157 | mtspr FSL_EIS_SPRG9, r0 |
---|
158 | mtsrr0 r0 |
---|
159 | mtsrr1 r0 |
---|
160 | mtspr USPRG0, r0 |
---|
161 | #ifdef HAS_SPE |
---|
162 | evmra r0, r0 |
---|
163 | #endif |
---|
164 | #endif /* INIT_REGISTERS_FOR_LSM */ |
---|
165 | mtspr TBWL, r0 |
---|
166 | mtspr TBWU, r0 |
---|
167 | |
---|
168 | /* Enable time base */ |
---|
169 | mfspr r3, HID0 |
---|
170 | ori r3, r3, 0x4000 |
---|
171 | mtspr HID0, r3 |
---|
172 | |
---|
173 | /* Enable branch prediction */ |
---|
174 | LWI r3, FSL_EIS_BUCSR_BBFI | FSL_EIS_BUCSR_BPEN |
---|
175 | mtspr FSL_EIS_BUCSR, r3 |
---|
176 | |
---|
177 | #endif /* MPC55XX_NEEDS_LOW_LEVEL_INIT */ |
---|
178 | |
---|
179 | /* MMU early initialization */ |
---|
180 | LA r3, mpc55xx_start_config_mmu_early |
---|
181 | LW r4, mpc55xx_start_config_mmu_early_count |
---|
182 | bl mpc55xx_start_mmu_apply_config |
---|
183 | |
---|
184 | #ifdef MPC55XX_NEEDS_LOW_LEVEL_INIT |
---|
185 | |
---|
186 | /* Initialize intermediate stack (ECC) */ |
---|
187 | |
---|
188 | LA r3, bsp_ram_start |
---|
189 | addi r4, r3, MPC55XX_EARLY_STACK_SIZE |
---|
190 | |
---|
191 | zero_intermediate_stack_loop: |
---|
192 | |
---|
193 | #ifdef HAS_SPE |
---|
194 | evstdd r0, 0(r3) |
---|
195 | evstdd r0, 8(r3) |
---|
196 | evstdd r0, 16(r3) |
---|
197 | evstdd r0, 24(r3) |
---|
198 | #else |
---|
199 | stw r0, 0(r3) |
---|
200 | stw r0, 4(r3) |
---|
201 | stw r0, 8(r3) |
---|
202 | stw r0, 12(r3) |
---|
203 | stw r0, 16(r3) |
---|
204 | stw r0, 20(r3) |
---|
205 | stw r0, 24(r3) |
---|
206 | stw r0, 28(r3) |
---|
207 | #endif |
---|
208 | addi r3, r3, 32 |
---|
209 | cmpw cr7, r3, r4 |
---|
210 | bne cr7, zero_intermediate_stack_loop |
---|
211 | subi r1, r3, 16 |
---|
212 | |
---|
213 | #endif /* MPC55XX_NEEDS_LOW_LEVEL_INIT */ |
---|
214 | |
---|
215 | /* Next steps in C */ |
---|
216 | bl mpc55xx_start_early |
---|
217 | |
---|
218 | /* Initialize start stack */ |
---|
219 | LA r1, start_stack_end |
---|
220 | subi r1, r1, 16 |
---|
221 | li r0, 0 |
---|
222 | stw r0, 0(r1) |
---|
223 | |
---|
224 | /* Load sections */ |
---|
225 | LA r3, bsp_section_fast_text_begin |
---|
226 | LA r4, bsp_section_fast_text_load_begin |
---|
227 | LA r5, bsp_section_fast_text_size |
---|
228 | bl mpc55xx_start_load_section |
---|
229 | LA r3, bsp_section_fast_data_begin |
---|
230 | LA r4, bsp_section_fast_data_load_begin |
---|
231 | LA r5, bsp_section_fast_data_size |
---|
232 | bl mpc55xx_start_load_section |
---|
233 | LA r3, bsp_section_data_begin |
---|
234 | LA r4, bsp_section_data_load_begin |
---|
235 | LA r5, bsp_section_data_size |
---|
236 | bl mpc55xx_start_load_section |
---|
237 | |
---|
238 | /* Set up EABI and SYSV environment */ |
---|
239 | bl __eabi |
---|
240 | |
---|
241 | /* Clear command line */ |
---|
242 | li r3, 0 |
---|
243 | |
---|
244 | /* Start RTEMS */ |
---|
245 | bl boot_card |
---|
246 | |
---|
247 | /* Spin around */ |
---|
248 | twiddle: |
---|
249 | |
---|
250 | b twiddle |
---|
251 | |
---|
252 | mpc55xx_start_mmu_apply_config: |
---|
253 | |
---|
254 | cmpwi cr7, r4, r0 |
---|
255 | beqlr cr7 |
---|
256 | mtctr r4 |
---|
257 | |
---|
258 | mmu_init_loop: |
---|
259 | |
---|
260 | lwz r4, 0(r3) |
---|
261 | lwz r5, 4(r3) |
---|
262 | lwz r6, 8(r3) |
---|
263 | lwz r7, 12(r3) |
---|
264 | mtspr FSL_EIS_MAS0, r4 |
---|
265 | mtspr FSL_EIS_MAS1, r5 |
---|
266 | mtspr FSL_EIS_MAS2, r6 |
---|
267 | mtspr FSL_EIS_MAS3, r7 |
---|
268 | tlbwe |
---|
269 | addi r3, r3, 16 |
---|
270 | bdnz mmu_init_loop |
---|
271 | blr |
---|
272 | |
---|
273 | mpc55xx_start_load_section: |
---|
274 | cmpw cr7, r3, r4 |
---|
275 | beqlr cr7 |
---|
276 | b memcpy |
---|
277 | |
---|
278 | /* Start stack area */ |
---|
279 | |
---|
280 | .section ".bsp_rwextra", "aw", @nobits |
---|
281 | .align 4 |
---|
282 | .space 4096 |
---|
283 | |
---|
284 | start_stack_end: |
---|