1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup mpc55xx_asm |
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5 | * |
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6 | * @brief Boot and system start code. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2008 |
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11 | * Embedded Brains GmbH |
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12 | * Obere Lagerstr. 30 |
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13 | * D-82178 Puchheim |
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14 | * Germany |
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15 | * rtems@embedded-brains.de |
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16 | * |
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17 | * The license and distribution terms for this file may be found in the file |
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18 | * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE. |
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19 | */ |
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20 | |
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21 | /** |
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22 | * @defgroup mpc55xx_asm Assembler files |
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23 | * |
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24 | * @ingroup mpc55xx |
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25 | */ |
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26 | |
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27 | #include <libcpu/powerpc-utility.h> |
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28 | #include <mpc55xx/reg-defs.h> |
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29 | #include <bspopts.h> |
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30 | |
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31 | .section ".entry", "ax" |
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32 | PUBLIC_VAR (start) |
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33 | .globl fmpll_syncr_vals |
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34 | bam_rchw: |
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35 | /* |
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36 | * BAM |
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37 | */ |
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38 | |
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39 | /* BAM: RCHW */ |
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40 | .int 0x005a0000 |
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41 | |
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42 | /* BAM: Address of start instruction */ |
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43 | .int 0x8 |
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44 | |
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45 | /* |
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46 | * Enable time base |
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47 | */ |
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48 | start: |
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49 | li r0, 0 |
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50 | mtspr TBWU, r0 |
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51 | mtspr TBWL, r0 |
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52 | mfspr r2, HID0 |
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53 | ori r2, r2, 0x4000 |
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54 | mtspr HID0, r2 |
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55 | |
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56 | /* |
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57 | * System clock |
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58 | */ |
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59 | |
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60 | LWI r3,fmpll_syncr_vals |
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61 | bl SYM (mpc55xx_fmpll_reset_config) |
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62 | |
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63 | /* |
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64 | * Enable branch prediction |
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65 | */ |
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66 | |
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67 | LWI r2, BUCSR_BBFI | BUCSR_BPEN |
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68 | mtspr BUCSR, r2 |
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69 | |
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70 | /* |
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71 | * Basics |
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72 | */ |
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73 | |
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74 | /* Set stack start to end of ram */ |
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75 | LA r1, bsp_ram_end |
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76 | addi r1, r1, -8 |
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77 | |
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78 | /* Enable SPE */ |
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79 | mfmsr r2 |
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80 | oris r2, r2, 0x200 |
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81 | mtmsr r2 |
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82 | |
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83 | /* Config internal flash */ |
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84 | bl SYM (mpc55xx_flash_config) |
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85 | |
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86 | #if DATA_CACHE_ENABLE || INSTRUCTION_CACHE_ENABLE |
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87 | /* FIXME: Config cache */ |
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88 | bl config_cache |
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89 | #endif /* DATA_CACHE_ENABLE || INSTRUCTION_CACHE_ENABLE */ |
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90 | |
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91 | /* |
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92 | * TODO, FIXME: Enable cache in the MMU for the SRAM |
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93 | */ |
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94 | |
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95 | .equ MAS0, 624 |
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96 | .equ MAS1, 625 |
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97 | .equ MAS2, 626 |
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98 | .equ MAS3, 627 |
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99 | |
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100 | LWI r3, 0x10030000 |
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101 | mtspr MAS0, r3 |
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102 | tlbre |
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103 | LWI r4, ~0x00000008 |
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104 | mfspr r3, MAS2 |
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105 | and r3, r3, r4 |
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106 | mtspr MAS2, r3 |
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107 | tlbwe |
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108 | |
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109 | /* |
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110 | * TODO, FIXME: Set MMU for the external SRAM |
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111 | */ |
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112 | |
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113 | LWI r3, 0x10020000 |
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114 | mtspr MAS0, r3 |
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115 | tlbre |
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116 | LWI r4, 0xfff |
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117 | mfspr r3, MAS3 |
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118 | and r3, r3, r4 |
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119 | LWI r4, 0x20000000 |
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120 | or r3, r3, r4 |
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121 | mtspr MAS3, r3 |
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122 | tlbwe |
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123 | |
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124 | /* |
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125 | * Zero RAM (needed to get proper ECC) |
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126 | */ |
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127 | |
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128 | /* Addresses */ |
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129 | LA r3, bsp_ram_start |
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130 | LA r4, bsp_ram_end |
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131 | |
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132 | /* Assert: Proper alignment of destination start */ |
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133 | andi. r6, r3, 0x3f |
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134 | bne twiddle |
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135 | |
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136 | /* Assert: Proper alignment of destination end */ |
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137 | andi. r6, r4, 0x3f |
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138 | bne twiddle |
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139 | |
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140 | /* Data size = destination end - destination start */ |
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141 | subf r4, r3, r4 |
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142 | |
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143 | /* Save time */ |
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144 | mftb r24 |
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145 | |
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146 | /* Zero */ |
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147 | bl SYM (mpc55xx_zero_32) |
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148 | |
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149 | /* Save time and get time delta */ |
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150 | mftb r25 |
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151 | subf r24, r24, r25 |
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152 | |
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153 | /* |
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154 | * Copy data |
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155 | */ |
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156 | |
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157 | /* Addresses */ |
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158 | LA r3, bsp_section_text_end |
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159 | LA r4, bsp_section_data_start |
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160 | LA r5, bsp_section_data_end |
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161 | |
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162 | /* Assert: Proper alignment of source start */ |
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163 | andi. r6, r3, 0x7 |
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164 | bne twiddle |
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165 | |
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166 | /* Assert: Proper alignment of destination start */ |
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167 | andi. r6, r4, 0x7 |
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168 | bne twiddle |
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169 | |
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170 | /* Assert: Proper alignment of destination end */ |
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171 | andi. r6, r5, 0x7 |
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172 | bne twiddle |
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173 | |
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174 | /* Data size = destination end - destination start */ |
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175 | subf r5, r4, r5 |
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176 | |
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177 | /* Copy */ |
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178 | bl SYM (mpc55xx_copy_8) |
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179 | |
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180 | /* Save time and get time delta */ |
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181 | mftb r26 |
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182 | subf r25, r25, r26 |
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183 | |
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184 | /* |
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185 | * Prepare high level initialization |
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186 | */ |
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187 | |
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188 | /* Create NULL */ |
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189 | li r0, 0 |
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190 | |
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191 | /* Return address */ |
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192 | stw r0, 4(r1) |
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193 | |
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194 | /* Back chain */ |
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195 | stw r0, 0(r1) |
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196 | |
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197 | /* Read-only small data */ |
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198 | LA r2, _SDA2_BASE_ |
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199 | |
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200 | /* Read-write small data */ |
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201 | LA r13, _SDA_BASE_ |
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202 | |
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203 | /* |
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204 | * Start RTEMS |
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205 | */ |
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206 | |
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207 | /* Clear command line */ |
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208 | xor r3, r3, r3 |
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209 | |
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210 | /* Start RTEMS */ |
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211 | bl SYM (boot_card) |
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212 | |
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213 | /* Spin around */ |
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214 | b twiddle |
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215 | |
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216 | .equ L1CSR0, 1010 |
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217 | .equ L1CSR0_CINV, 0x2 |
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218 | .equ L1CSR0_CABT, 0x4 |
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219 | /* FIXME: CORG??? .equ L1CSR0_SETTINGS, 0x00180011 */ |
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220 | .equ L1CSR0_SETTINGS, 0x00100001 |
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221 | |
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222 | /* |
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223 | * Configure cache |
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224 | */ |
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225 | config_cache: |
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226 | /* Start cache invalidation */ |
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227 | LWI r5, L1CSR0_CINV |
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228 | mtspr L1CSR0, r5 |
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229 | |
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230 | /* Bit masks to test and clear invalidation abortion (CABT) */ |
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231 | LWI r6, L1CSR0_CABT |
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232 | not r7, r6 |
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233 | |
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234 | /* Wait for cache invalidation to complete */ |
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235 | check_cache_invalidation: |
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236 | mfspr r9, L1CSR0 |
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237 | |
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238 | /* Check if the invalidate was aborted */ |
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239 | and. r10, r9, r6 |
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240 | beq no_chache_invalidation_abort |
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241 | |
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242 | /* Clear CABT bit */ |
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243 | and r10, r9, r7 |
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244 | mtspr L1CSR0, r10 |
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245 | |
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246 | /* Retry invalidation */ |
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247 | b config_cache |
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248 | |
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249 | no_chache_invalidation_abort: |
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250 | /* Check CINV bit */ |
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251 | and. r10, r5, r9 |
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252 | |
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253 | /* Wait? */ |
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254 | bne check_cache_invalidation |
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255 | |
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256 | /* Enable cache */ |
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257 | LWI r6, L1CSR0_SETTINGS |
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258 | mfspr r5, L1CSR0 |
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259 | or r5, r5, r6 |
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260 | msync |
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261 | isync |
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262 | mtspr L1CSR0, r5 |
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263 | |
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264 | /* Return */ |
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265 | blr |
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266 | |
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267 | twiddle: |
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268 | b twiddle |
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